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In CMOS technology, there are a number of intrinsic bipolar junction transistors. In CMOS processes, these transistors can create problems when the combination of n-well/p-well and substrate results in the formation of parasitic n-p-n-p structures. Triggering these thyristor-like devices leads to a
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The latch-up does not have to happen between the power rails - it can happen at any place where the required parasitic structure exists. A common cause of latch-up is a positive or negative voltage spike on an input or output pin of a digital chip that exceeds the rail voltage by more than a diode
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Consider the n-well structure in the first figure. The n-p-n-p structure is formed by the source of the NMOS, the p-substrate, the n-well and the source of the PMOS. A circuit equivalent is also shown. When one of the two bipolar transistors gets forward biased (due to current flowing through the
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stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. The SCR
109:. This frequently happens in circuits which use multiple supply voltages that do not come up in the required sequence on power-up, leading to voltages on data lines exceeding the input rating of parts that have not yet reached a nominal supply voltage. Latch-ups can also be caused by an
332:. 2005. p. 7-7 to 7-8. quote: "CMOS inverters and gates inherently have ... parasitic bipolar transistors that form a silicon controlled rectifier (SCR). Although ... latch-up cannot be avoided, CMOS manufacturers design input and output circuits that are latch-up resistant"
185:) that surrounds both the NMOS and the PMOS transistors. This breaks the parasitic silicon-controlled rectifier (SCR) structure between these transistors. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed, such as
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Devices fabricated in lightly doped epitaxial layers grown on heavily doped substrates are also less susceptible to latch-up. The heavily doped layer acts as a current sink where excess minority carriers can quickly recombine.
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Also to avoid the latch, a separate tap connection is put for each transistor. But this will increase the size of the device so fabs give a minimum space to put a tap, for example, 10 μm in 130 nm technology.
136:, typically heavy ions or protons from cosmic rays or solar flares. Single-event latchup (SEL) can be completely eliminated by several manufacturing techniques, as part of
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well, or substrate), it feeds the base of the other transistor. This positive feedback increases the current until the circuit fails or burns out.
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shorting of the Vdd and GND lines, usually resulting in destruction of the chip, or a system failure that can only be resolved by power-down.
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Stephen A. Campbell, The
Science and Engineering of Microelectronic Fabrication, Oxford University Press (Indian Edition 2007) p.461
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parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.
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The invention of the now industry-standard technique to prevent CMOS latch-up was made by Hughes
Aircraft company in 1977.
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devices are inherently latch-up-resistant. Latch-up is the low resistance connection between tub and power supply rails.
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which makes this a significant issue in electronic products designed for space (or very high-altitude) applications. A
292:"Experimental study and Spice simulation of CMOS inverters latch-up effects due to high power microwave interference"
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Both CMOS integrated circuits and TTL integrated circuits are more susceptible to latch-up at higher temperatures.
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All CMOS ICs have latch-up paths, but there are several design techniques that reduce susceptibility to latch-up.
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It is possible to design chips to be resistant to latch-up by adding a layer of insulating oxide (called a
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R. Koga, K.B. Crawford, S.J. Hansel, B.M. Johnson, D.D. Lau, S.H. Penzin, S.D. Pinkerton, M.C. Maher.
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which disrupts proper functioning of the part, possibly even leading to its destruction due to
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drop. Another cause is the supply voltage exceeding the absolute maximum rating, often from a
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343:"Fairchild's Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic"
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Analog
Devices: Winning the battle against latchup in CMOS analog devices
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Maxwell
Technologies Microelectronics: Latchup Protection Technology
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46:(IC). More specifically, it is the inadvertent creation of a low-
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High-power microwave interference can also trigger latch ups.
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Intrinsic bipolar junction transistors in the CMOS technology
250:"AN-932 SEU and Latch Up Tolerant Advanced CMOS Technology"
412:"Silicon-on-insulator: materials aspects and applications"
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262:"Single-event latch-up protection of integrated circuits"
361:, Massachusetts Institute of Technology, Cambridge;
275:"The Next-Generation SC-7 RISC Spaceflight Computer"
73:The parasitic structure is usually equivalent to a
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27:Short circuit which can occur in MOSFET circuits
317:"Understanding Latch-Up in Advanced CMOS Logic"
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290:H. Wang, J. Li, H. Li, K. Xiao and H. Chen.
227:This standard is commonly referenced in IC
410:Plößl, Andreas; Kräuter, Gertrud (2000).
85:structure which acts as a PNP and an NPN
305:"High Temperature Schottky TTL latch-up"
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70:is required to correct this situation.
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357:, University of California, Berkeley;
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307:. doi: 10.1109/TNS.1978.4329568 1978.
124:Another common cause of latch-ups is
273:D. J. Shirley and M. K. McLelland.
158:Equivalent circuit of CMOS latch-up
101:in the power supply. It leads to a
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382:"Hughes Aircraft Patent US4173767"
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330:"Microelectronics 2nd Edition"
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495:Semiconductor device defects
303:Cooper, M.S.; Retzler, J.P.
279:Southwest Research Institute
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475:SCR Latchup Video Tutorial
132:is a latch-up caused by a
460:Latch-up in CMOS designs
416:Solid-State Electronics
111:electrostatic discharge
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58:circuit, triggering a
42:which can occur in an
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130:single event latch-up
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359:Anantha Chandrakasan
208:Testing for latch-up
198:silicon-on-insulator
490:Integrated circuits
328:Jerry C. Whitaker.
177:Preventing latch-up
138:radiation hardening
60:parasitic structure
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134:single event upset
126:ionizing radiation
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52:power supply rails
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236:References
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436:0038-1101
221:STANDARD
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103:breakdown
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75:thyristor
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441:5 August
187:hot swap
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