275:. The R5000 implements the multiply-add instruction of the MIPS IV ISA. Single-precision adds, multiplies and multiply-adds have a four-cycle latency and a one cycle throughput. Single-precision divides have a 21-cycle latency and a 19-cycle throughput, while square roots have a 26-cycle latency and a 38-cycle throughput. Division and square-root was not pipelined. Instructions that operate on double precision numbers have a significantly higher latency and lower throughput except for add, which has identical latency and throughput with single-precision add. Multiply and multiply-add have a five-cycle latency and a two-cycle throughput. Divide has a 36-cycle latency and a 34-cycle throughput. Square root has a 68-cycle latency and a 66-cycle throughput.
302:. The two levels of polysilicon enabled IDT to use a four-transistor SRAM cell, resulting in a transistor count of 3.6 million and a die that measured 8.7 mm by 9.7 mm (84.39 mm). NEC and NKK fabricated the R5000 in a process with one level of polysilicon and three levels of aluminium interconnect. Without an extra level of polysilicon, both companies had to use a six-transistor SRAM cell, resulting in a transistor count of 5.0 million and a larger die with an area of around 87 mm. Die sizes in the range of 80 to 90 mm were claimed by MTI. 0.8 million of the transistors in both versions were for logic, and the remainder contained in the caches. It was packaged in a 272-ball plastic
362:, the RM52xx and RM52x1 families were continued as PMC-Sierra products. PMC-Sierra introduced two RM52x1 derivatives, the RM5231A and RM5261A, on 4 April 2001. These microprocessors were fabricated by TSMC in its 0.18 μm process and differ from the previous devices by featuring higher clock rates and lower power consumption. The RM5231A was available at clock rates of 250 to 350 MHz, and the RM5261A from 250 to 400 MHz.
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150, 200, and 250 MHz; whereas the RM5261 and RM5271 were available at 250 and 266 MHz. On 6 July 1999, a 300 MHz RM5271 was introduced, priced at US$ 140 in quantities of 10,000. The RM52x1 improved upon the previous family with larger 32 KB primary caches and a faster SysAD bus that supported clock rates up to 125 MHz.
260:. Instructions were predecoded as they enter the instruction cache by appending four bits to each instruction. These four bits specify whether can be issued together and which execution unit they are executed by. This assisted superscalar instruction issue by moving some of the dependency and conflict checking out of the critical path.
319:
initially consisted of two models, the RM5230 and RM5260. These were announced on 24 March 1997. The RM5230 was initially available at 100 and 133 MHz, and the RM5260 at 133 and 150 MHz. On 29 September 1997, new 150 and 175 MHz RM5230s were introduced, as were 175 and 200 MHz RM5260s.
263:
The integer unit executes most instructions with a one cycle latency and throughput except for multiply and divide. 32-bit multiplies have a five-cycle latency and a four-cycle throughput. 64-bit multiplies have an extra four cycles of latency and half the throughput. Divides have a 36-cycle latency
354:
On 20 July 1998, the RM52x1 family was announced. The family consisted of the RM5231, RM5261, and RM5271. These microprocessors were derivatives of the corresponding devices from the RM52x0 family fabricated in a 0.25 μm process with four levels of metal. The RM5231 was initially available at
338:
The RM52xx family was later joined by the RM5270, which was announced at the
Embedded Systems Conference on 29 September 1997. Intended for high-end embedded applications, the RM5270 was available at 150 and 200 MHz. Improvements were the addition of an on-chip secondary cache controller that
318:
In the late 1990s, Quantum Effect Design acquired a license to manufacture and sell MIPS microprocessors from MTI and became a microprocessor vendor, changing its name to
Quantum Effect Devices to reflect its new business model. The company's first products were members of the RM52xx family, which
121:
used a derivative model, the RM5230 and RM5231. The Qube 2700 used the RM5230 microprocessor, whereas the Qube 2 used the RM5231. The original RaQ systems were equipped with RM5230 or RM5231 CPUs but later models used AMD K6-2 chips and then eventually Intel
Pentium III CPUs for the final models.
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Both the RM5230 and RM5260 are derivatives of the R5000 and differ in the size of their primary caches (16 KB each instead of 32 KB), the width of their system interfaces (the RM5230 has a 32-bit 67 MHz SysAD bus, and the RM5260 a 64-bit 75 MHz SysAD bus), and the addition of
130:
The original roadmap called for 200 MHz operation in early 1996, 250 MHz in late 1996, succeeded in 1997 by R5000A. The R5000 was introduced in
January 1996 and failed to achieve 200 MHz, topping out at 180 MHz. When positioned as a low-end workstation microprocessor, the
271:(FPU) was a fast single-precision (32-bit) design, for reduced cost and to benefit SGI, whose mid-range 3D graphics workstations relied mostly on single-precision math for 3D graphics applications. It was fully pipelined, which made it significantly better than that of the
278:
The R5000 had an integrated L2 cache controller that supported capacities of 512 KB, 1 MB and 2 MB. The L2 cache shares the SysAD bus with the external interface. The cache was built with custom synchronous SRAMs (SSRAMs). The microprocessor uses the SysAD
252:, a distinct characteristic of QED, whose designers favored simple designs with large caches. The R5000 had two L1 caches, one for instructions and the other for data. Both have a capacity of 32 KB. The caches are two-way
380:
compliant unlike FPUs used by R5000. It also has a second MIPS core which acted as a sync controller for specialized vector coprocessors, important for 3D math which at the time was principally computed on the CPU.
81:
as their flagship high-end embedded microprocessor. IDT marketed its version of the R5000 as the 79RV5000, NEC as VR5000, NKK as the NR5000, and
Toshiba as the TX5000. The R5000 was sold to
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supported up to 2 MB of cache. The SysAD bus is 64 bits wide and can operate at 100 MHz. It was packaged in a 304-pin Super-BGA (SBGA) that was pin-compatible with the
113:
such as network routers and high-end printers. The R5000 found its way into the arcade gaming industry, R5000 powered mainboards were used by Atari and Midway. Initially the
294:
QED was a fabless company and did not fabricate their own designs. The R5000 was fabricated by IDT, NEC and NKK. All three companies fabricated the R5000 in a 0.35 μm
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with a customized instruction/data cache arrangement and Sony's proprietary 107 vector SIMD Multimedia
Extensions(MMI). Its custom FPU is not
298:(CMOS) process, but with different process features. IDT fabricated the R5000 in a process with two levels of polysilicon and three levels of
287:(address and data share the same set of wires) and can operate at clock frequencies up to 100 MHz. The initial R5000 did not support
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for integer instructions and another for floating-point to save transistors and die area to reduce cost. The R5000 did not perform
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in the branch-likely instructions first introduced in the MIPS II architecture to determine how likely a branch is taken.
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497:
Quantum Effect
Devices (29 September 1997). "QED Introduces RM5270 Superscalar 64-bit Microprocessor". Press release.
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PMC-Sierra, Inc. (4 April 2001). "PMC-Sierra Ships Third
Generation R5200A MIPS Microprocessors". Press release.
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when the company acquired QED. Derivatives of the R5000 are still in production today for embedded systems.
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58:
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500:
Quantum Effect
Devices (20 July 1998). "QED Introduces The RM52x1 Microprocessor Family". Press release.
233:. The R5000 could simultaneously issue an integer and a floating-point instruction. It had one simple
494:
Quantum Effect
Devices (24 March 1997). "QED Introduces RM52xx Microprocessor Family". Press release.
324:
503:
Quantum Effect Devices (6 July 1999). "QED's RM5271 Available Immediately at 300MHz". Press release.
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in its Power-Quad 4 packages, the RM5230 in a 128-pin version, and the RM5260 in a 208-pin version.
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and throughput for 32-bit integers, and for 64-bit integers, they are increased to 68 cycles.
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for cost reasons. Instead it uses a static approach, utilizing the hints encoded by the
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Computergram (8 January 1996). "MIPS Ready With R5000 Successor to the 4600/4700".
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Gwennap, Linley (22 January 1996). "R5000 Improves FP for MIPS Midrange".
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310:(PGA). It was not pin-compatible with any previous MIPS microprocessor.
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that is also used by several other MIPS microprocessors. The bus is
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Halfhill, Tom R. (May 1996). "Mips R5000: Fast, Affordable 3-D".
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Users of the R5000 in workstation and server computers were
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applications. These microprocessors were fabricated by the
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57:(MTI), also the licensor. MTI then licensed the design to
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multiply-add and three-operand multiply instructions for
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Halfhill, Tom R. (April 1996). "R5000 Cuts 3-D Cost".
343:and was offered as a migration path to the RM7000.
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complementary metal–oxide–semiconductor
109:low-end workstations. The R5000 was also used in
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486:MIPS R5000 Microprocessor Technical Backgrounder
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424:"System 16 - Midway Seattle Hardware (Midway)"
372:is a modified version of R5000 CPU dubbed the
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399:"System 16 - Atari Seattle Hardware (Atari)"
180:. Unsourced material may be challenged and
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515:
329:Taiwan Semiconductor Manufacturing Company
131:competition included the IBM and Motorola
200:Learn how and when to remove this message
53:(QED) in 1996. The project was funded by
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1587:Quantum Effect Devices microprocessors
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1223:
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557:List of MIPS architecture processors
258:virtually indexed, physically tagged
256:, have a 32-byte line size, and are
178:adding citations to reliable sources
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38:, in-order execution 2-issue design
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229:design that executes instructions
14:
1608:
150:
597:LS3A4000/LS3A4000-I(LS3A4000-i)
594:LS3A3000/LS3A3000-I(LS3A3000-i)
588:LS3A1000/LS3A1000-I(LS3A1000-i)
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101:. SGI used the R5000 in their
73:. The R5000 succeeded the QED
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552:MIPS architecture processors
59:Integrated Device Technology
47:instruction set architecture
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1592:Superscalar microprocessors
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358:After QED was acquired by
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306:(BGA) or 223-pin ceramic
239:dynamic branch prediction
685:Velocity Micro T301 Cruz
682:Velocity Micro T103 Cruz
484:MIPS Technologies, Inc.
448:Computer Business Review
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248:The R5000 had large L1
225:The R5000 is a two-way
1597:64-bit microprocessors
1283:Loongson-based systems
1233:MIPS R3000A-compatible
1155:Alchemy Semiconductor
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300:aluminium interconnect
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95:Silicon Graphics, Inc.
55:MIPS Technologies, Inc
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911:88E6318 "Link Street"
456:Microprocessor Report
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51:Quantum Effect Design
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1582:MIPS implementations
1243:PlayStation Portable
764:Microchip Technology
537:MIPS microprocessors
350:QED RM52x1 die shot.
221:NEC VR5000 die shot.
174:improve this section
42:that implements the
694:Ainol Novo7 Paladin
591:LS3A2000/LS3A1500-I
269:floating-point unit
49:(ISA) developed by
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877:/Infineon/Lantiq
875:Texas Instruments
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802:Loongson 1 Series
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750:(embedded device)
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660:Skytone Alpha-400
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547:MIPS architecture
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190:February 2010
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159:This section
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30:is a 64-bit,
29:
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1556:H2 "Capitan"
1554:
1547:
1482:
652:Ben NanoNote
485:
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467:
460:
454:
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431:. Retrieved
427:
418:
406:. Retrieved
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266:
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196:
187:
172:Please help
160:
129:
92:
27:
25:
15:
1245:R4000-based
1237:Nintendo 64
1025:Fusiv Vx180
674:Game Gadget
667:Dingoo A320
626:Application
433:30 November
408:30 November
314:Derivatives
285:multiplexed
227:superscalar
213:Description
141:Pentium Pro
133:PowerPC 604
115:Cobalt Qube
36:superscalar
1576:Categories
1549:H1 "Beast"
1377:processors
1344:compatible
1321:compatible
1276:compatible
1239:NEC VR4300
1182:compatible
1129:compatible
921:24Kc/24KEc
838:Networking
795:compatible
718:compatible
637:compatible
628:processors
577:compatible
568:processors
385:References
360:PMC-Sierra
119:Cobalt RaQ
97:(SGI) and
83:PMC-Sierra
22:NEC VR5000
1312:Aerospace
161:does not
137:PA-7300LC
135:, the HP
32:bi-endian
1426:MIPS III
1299:SiCortex
1293:LS3B1000
1290:LS3A1000
1189:Broadcom
1136:Broadcom
1117:RTL8198C
1092:MediaTek
1071:Broadcom
1058:MediaTek
947:MediaTek
865:MediaTek
845:4Kc/4KEc
806:LS1A0300
776:4Kc/4KEc
701:GCW-Zero
698:NEOGEO-X
672:JZ4750 (
665:JZ4740 (
658:JZ4730 (
612:LS3B4000
609:LS3B3000
606:LS3B2000
603:LS3B1500
600:LS3B1000
378:IEEE 754
243:compiler
235:pipeline
231:in-order
1523:R16000A
1513:R14000A
1503:R12000A
1475:MIPS IV
1408:MIPS II
1375:Classic
1224:various
1193:various
1159:Alchemy
1150:various
1140:various
1113:Realtek
1075:BCM4706
1052:QCA9558
907:Marvell
815:LS1C101
812:LS1C300
784:Xilleon
767:PIC32MX
690:JZ4770
679:JZ4760
648:JZ4720
566:General
182:removed
167:sources
126:History
71:Toshiba
61:(IDT),
44:MIPS IV
1540:MIPS V
1528:R18000
1518:R16000
1508:R14000
1498:R12000
1493:R10000
1451:R4300i
1385:MIPS I
1355:LS1E04
1342:MIPS32
1319:MIPS64
1274:MIPS64
1217:Gaming
1203:Octeon
1199:Cavium
1180:MIPS64
1146:Cavium
1127:MIPS32
1106:1074Kc
1096:MT7621
1085:1004Kc
1065:RT3883
1062:RT3662
1049:AR9344
1018:Ikanos
1012:GRX388
1009:VRX288
1002:Lantiq
982:DANUBE
978:Lantiq
972:MT7688
969:MT7628
966:MT7620
963:RT6856
960:RT5350
957:RT3350
954:RT3052
951:RT3050
941:AR9331
938:AR9132
935:AR7161
932:AR7240
890:AMAZON
886:Lantiq
869:RT2880
859:AR2318
856:AR2313
793:MIPS32
716:MIPS64
706:JZ4780
635:MIPS32
575:MIPS64
367:Sony's
341:RM7000
250:caches
69:, and
1488:R8000
1483:R5000
1463:R4700
1458:R4600
1446:R4200
1439:R4400
1434:R4000
1416:R6000
1398:R3000
1393:R2000
1006:AR188
985:VINAX
273:R4700
89:Users
79:R4700
75:R4600
28:R5000
1361:LS1J
1038:74Kc
995:34Kc
824:LS1H
821:LS1G
818:LS1D
809:LS1B
729:LS2H
478:Byte
469:Byte
463:(1).
435:2015
410:2015
267:The
165:any
163:cite
117:and
107:Indy
105:and
77:and
26:The
1170:XLR
900:5Kc
880:AR7
757:M4K
281:bus
176:by
67:NKK
63:NEC
1578::
461:10
459:,
426:.
401:.
103:O2
65:,
34:,
676:)
669:)
662:)
530:e
523:t
516:v
488:.
472:.
450:.
437:.
412:.
203:)
197:(
192:)
188:(
184:.
170:.
143:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
