1355:, was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch.
1381:, were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixed
798:
2314:
241:(ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.
1655:. Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.
864:
part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBM
1474:
could be eliminated. The result was the RISC (Reduced
Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and
1473:
The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex
Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set
1234:
or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may
863:
Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different
308:
Prior to NPL , the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors
852:" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix (
226:, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the
1270:
enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and
1370:
such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful
761:
Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC
801:
One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add
Immediate" instruction, which allows selection of source and destination registers and inclusion of a small
1341:
Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles a cache line or virtual memory page boundary, for instance), and are therefore somewhat easier to optimize for speed.
369:(RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.
1385:, whereas a typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.
1350:
In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, the
1250:
measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be
309:
spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.
499:; however, the term is misleading). They are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation on it later. They are often called
673:
by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include:
1677:
The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typical
1299:
have minimum instruction sizes between 8 and 64 bits. The longest possible instruction on x86 is 15 bytes (120 bits). Within an instruction set, different instructions may have different lengths. In some architectures, notably most
1396:
typically exhibit very high density owing to a technique called code compression. This technique packs two 16-bit instructions into one 32-bit word, which is then unpacked at the decode stage and executed as two instructions.
770:
instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy
1576:, and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc.
1407:, where there are few separate instructions (8–32), so that multiple instructions can be fit into a single machine word. These types of cores often take little silicon to implement, so they can be easily realized in an
860:, not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.
1194:
Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR,
337:, implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see:
244:
An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute
1338:
variable encoding, that is two fixed, usually 32-bit and 16-bit encodings, where instructions cannot be mixed freely but must be switched between on a branch (or exception boundary in ARMv8).
669:
Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are
944:. For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.
1583:
of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind of
1415:
form. The code density of MISC is similar to the code density of RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task.
271:
techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the
1658:
Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of the
1366:). However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (using
230:
of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.
1587:
is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture. There are two basic ways to build a
3384:
775:
of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as
1832:
1358:
Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively named
248:
for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.
1031:
2356:
1186:
more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the
1239:). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.
3495:
2678:
2318:
1517:
3197:
2475:
461:
More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by
3354:
2920:
2737:
1702:
1572:
A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same
1441:
has the option -Os to optimize for small machine code size, and -O3 to optimize for execution speed at the cost of larger machine code.
3708:
2700:
385:
1595:
Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).
3349:
218:
running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing
3421:
1627:
4297:
3703:
3174:
1630:
129:
1622:
Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the
2074:
1935:
1527:
used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as a
961:: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit
4118:
3242:
2505:
2349:
2272:
868:
has a conditional store instruction. A few instruction sets include a predicate field in every instruction; this is called
4128:
3269:
2396:
1255:
into memory. Increasing the number of registers in an architecture decreases register pressure but increases the cost.
2199:
2107:
3436:
3264:
3237:
2616:
2290:
1815:
763:
726:
1437:
have options that control whether to optimize code generation for execution speed or for code density. For instance
495:
data from a memory location or a register to a memory location or a register (a machine instruction is often called
4287:
4251:
3814:
2707:
2673:
2668:
2587:
2552:
1927:
1563:
1400:
1378:
1363:
1301:
1262:
suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like
838:
401:
366:
362:
170:
or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an
4292:
4226:
4123:
3524:
3431:
3232:
2453:
2342:
1458:
1179:
Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.
1862:
Schlansker, Michael S.; Rau, B. Ramakrishna (February 2000). "EPIC: Explicitly
Parallel Instruction Computing".
222:
between implementations. This enables multiple implementations of an ISA that differ in characteristics such as
3252:
2971:
2406:
2162:
1840:
1773:
1740:
full systems simulator providing ability to create/model/emulate any instruction set using C and standard APIs
3426:
3274:
3247:
3108:
2722:
2683:
2540:
1641:
1408:
1150:
RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed:
734:, a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated
390:
3863:
3625:
3101:
3062:
2717:
2712:
2458:
1732:
1535:
405:
238:
3490:
3187:
2885:
2582:
1663:
1543:
365:(CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A
1235:
differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the
4140:
3787:
3204:
2695:
2663:
2433:
2421:
2401:
2282:
2018:
1753:
1707:
1584:
1538:
algorithms are much easier to implement if the instruction set includes support for something such as "
1284:
857:
827:
373:
122:
1226:
Each instruction specifies some number of operands (registers, memory locations, or immediate values)
4231:
4194:
4184:
2572:
1722:
849:
697:
619:
86:
2139:
357:
An ISA may be classified in a number of different ways. A common classification is by architectural
4302:
4246:
3653:
3589:
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3416:
3378:
3214:
3164:
3159:
2636:
2530:
2438:
1679:
1637:
1615:
338:
251:
The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in
4199:
3982:
3876:
3840:
3757:
3741:
3583:
3372:
3331:
3319:
3182:
3096:
3017:
2782:
2443:
2386:
1687:
1652:
1449:
The instructions constituting a program are rarely specified using their internal, numeric form (
1438:
1204:
962:
853:
834:
architectures, multiple simultaneous opcodes and operands are specified in a single instruction.
705:
647:
another block of code, while saving the location of the next instruction as a point to return to.
334:
163:
1686:
that can fetch an instruction and two data words simultaneously, and it requires a single-cycle
1230:. Some instructions give one or both operands implicitly, such as by being stored on top of the
4005:
3977:
3887:
3852:
3601:
3595:
3577:
3311:
3305:
3209:
3113:
3004:
2943:
2805:
2448:
2134:
1611:
1419:
1231:
279:
275:
1967:
1203:. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the
4179:
4088:
3834:
3546:
3364:
3123:
3091:
3049:
2961:
2762:
2577:
2567:
2557:
2547:
2517:
2500:
2365:
1712:
1423:
776:
754:
115:
20:
538:
the values of two registers, placing the result in a register, possibly setting one or more
4209:
4145:
3731:
3453:
3343:
3290:
2822:
2535:
2391:
2373:
2062:
1683:
1667:
1659:
1434:
1315:
326:
223:
219:
8:
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4241:
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3912:
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3858:
3846:
3500:
3447:
3224:
3140:
3022:
2877:
2772:
2631:
1864:
1490:
1389:
954:
581:
575:
286:
188:
103:
2066:
1279:
The size or length of an instruction varies widely, from as little as four bits in some
918:: All arithmetic operations take place using the top one or two positions on the stack:
4113:
4105:
3957:
3932:
3736:
3611:
3135:
3076:
2956:
2688:
2416:
1804:
1486:
1292:
869:
819:
748:
627:
486:
444:
196:
98:
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to implement this description (although many designs use middle ways or compromises):
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4033:
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3772:
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1454:
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1263:
1252:
1212:
767:
745:
570:
264:
227:
1046:; This requires a load/store pair for any memory movement regardless of whether the
16:
Set of abstract symbols that describe a computer program's operations to a processor
4236:
4169:
4155:
4010:
3917:
3871:
3678:
3673:
3668:
3663:
3658:
3648:
3518:
3485:
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3391:
3300:
3152:
3147:
3130:
3118:
3057:
2621:
2599:
2485:
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2381:
2268:
2256:
2144:
2033:
1873:
1743:
1603:
1567:
1559:
1547:
1516:
Fast virtual machines are much easier to implement if an instruction set meets the
1311:
597:
two values in registers (for example, to see if one is less, or if they are equal).
587:
539:
408:(OISC). These are theoretically important types, but have not been commercialized.
268:
234:
155:
143:
65:
4150:
4135:
4083:
3987:
3962:
3799:
3792:
3643:
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3633:
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3480:
3470:
3192:
3027:
2979:
2742:
2626:
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2495:
2490:
2411:
2276:
1727:
1367:
1280:
958:
823:
772:
635:
543:
452:
314:
200:
192:
91:
4261:
4095:
4078:
4071:
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3824:
3561:
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2989:
2951:
2900:
2895:
2890:
2604:
2428:
2244:
1506:
865:
500:
204:
172:
53:
2324:
2148:
1662:
only allow a single memory load or memory store per instruction, leading to a
4281:
4056:
3972:
3012:
2994:
2787:
2480:
1539:
1404:
1296:
915:
845:
735:
2915:
2329:
2091:
1481:
Some instruction set designers reserve one or more opcodes for some kind of
4266:
4204:
4020:
3997:
3809:
3530:
2468:
2093:
Harnessing ISA Diversity: Design of a
Heterogeneous-ISA Chip Multiprocessor
1588:
1450:
741:
690:
657:
Load/store data to and from a coprocessor or exchanging with CPU registers.
462:
416:
245:
215:
208:
180:
58:
29:
4051:
4015:
3726:
3698:
3556:
3411:
2334:
1482:
701:
686:
297:
2037:
3937:
3927:
3922:
3904:
3804:
3777:
3039:
2872:
2842:
2562:
1748:
1671:
1528:
1412:
1127:
CISC — Or, on machines limited to two memory operands per instruction,
679:
643:
400:
Architectures with even less complexity have been studied, such as the
301:
81:
899:
are (direct or calculated) addresses referring to memory cells, while
880:
Instruction sets may be categorized by the maximum number of operands
4028:
4025:
3767:
2837:
2815:
1877:
1599:
1524:
1498:
1475:
1267:
1259:
1216:
1200:
1196:
831:
822:, memory locations, or literal data. The operand specifiers may have
709:
342:
330:
322:
252:
184:
2217:
4043:
2862:
1830:
1781:
1717:
1648:
1623:
1462:
1430:
1323:
1073:
RISC — Requiring explicit memory loads, the instructions would be:
670:
427:. On the processing architecture, a given instruction may specify:
394:
318:
296:, distinct from the design of a specific machine, was developed by
159:
1995:
1993:
1949:
1947:
992:
2-operand — many CISC and RISC machines fall under this category:
837:
Some exotic instruction sets do not have an opcode field, such as
678:
transferring multiple registers to or from memory (especially the
623:
to another location in the program and execute instructions there.
2852:
2810:
2247:(July–August 1985). "Standard Microprocessor Programming Cards".
1666:(RISC). For another example, some early ways of implementing the
815:
784:
2179:
473:
Examples of operations common to many instruction sets include:
2867:
2832:
2797:
2313:
2108:"Intel® 64 and IA-32 Architectures Software Developer's Manual"
2096:. 41st Annual International Symposium on Computer Architecture.
1990:
1944:
1922:
Gilreath, William F.; Laplante, Phillip A. (December 6, 2012).
1737:
807:
780:
717:
431:
282:
167:
48:
1978:
1422:
as a mechanism for improving code density. The mathematics of
797:
3325:
2857:
2827:
1831:
Crystal Chen; Greg Novick; Kirk
Shimano (December 16, 2006).
1393:
1327:
1236:
1220:
1208:
1050:
result is an augmentation stored to a different place, as in
757:
operations with an operand from memory rather than a register
272:
1802:
Pugh, Emerson W.; Johnson, Lyle R.; Palmer, John H. (1991).
4189:
3337:
3257:
2847:
1319:
1021:. This effectively 'stores' the result without an explicit
965:
as the left operand (and the destination if there is one):
713:
346:
2218:"Great Microprocessors of the Past and Present (V 13.4.0)"
389:(EPIC) architectures. These architectures seek to exploit
2777:
2767:
1607:
1187:
806:
On traditional architectures, an instruction includes an
585:
of corresponding bits in a pair of registers, taking the
2325:
Programming
Textfiles: Bowen's Instruction Summary Cards
826:
determining their meaning or may be in fixed fields. In
263:
An instruction set architecture is distinguished from a
476:
434:(the instruction to be performed) e.g. add, copy, test
289:, but they have radically different internal designs.
2133:. IEEE International Conference on Computer Design.
564:
in some ISAs, saving operand fetch in trivial cases.
393:
with less hardware than RISC and CISC by making the
1429:In practice, code density is also dependent on the
1310:, typically corresponding with that architecture's
1271:register-to-register spills) that CISC ISAs offer.
2330:Mark Smotherman's Historical Computer Designs Page
1803:
517:
397:responsible for instruction issue and scheduling.
2267:
2185:
2059:A Practical Introduction to Computer Architecture
2017:Cocke, John; Markstein, Victoria (January 1990).
1999:
1984:
1953:
1801:
1553:
1453:); they may be specified by programmers using an
810:that specifies the operation to perform, such as
631:to another location if a certain condition holds.
4279:
1921:
1893:"On the Classification of Computer Architecture"
1924:Computer Architecture: A Minimalist Perspective
1897:International Journal of Science and Technology
1602:routines or tables (or both) to do this, using
1109:CISC — It becomes either a single instruction:
2278:Computer Architecture: A Quantitative Approach
2016:
1774:"GLOSSARY: Instruction Set Architecture (ISA)"
1518:Popek and Goldberg virtualization requirements
856:) operations that work only on the expression
376:(VLIW) architectures, and the closely related
2350:
2089:
1861:
1426:describes the challenges and limits of this.
123:
2129:Weaver, Vincent M.; McKee, Sally A. (2009).
1891:Shaout, Adnan; Eldos, Taisir (Summer 2003).
1501:uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF
1314:. In other architectures, instructions have
3355:Computer performance by orders of magnitude
2131:Code density concerns for new architectures
2128:
1890:
1703:Comparison of instruction set architectures
651:
285:implement nearly identical versions of the
2364:
2357:
2343:
1106:3-operand, allowing better reuse of data:
612:
166:in a computer or a family of computers. A
130:
116:
2138:
2090:Venkat, Ashish; Tullsen, Dean M. (2014).
2019:"The evolution of RISC technology at IBM"
1457:or, more commonly, may be generated from
1190:"POLY" polynomial evaluation instruction.
957:, include early computers and many small
830:(VLIW) architectures, which include many
608:for arithmetic on floating-point numbers.
386:explicitly parallel instruction computing
352:
345:implemented the x86 instruction set atop
179:In general, an ISA defines the supported
2012:
2010:
2008:
1258:While embedded instruction sets such as
796:
19:For broader coverage of this topic, see
2197:
2026:IBM Journal of Research and Development
1382:
903:and so on refer to machine registers.)
792:
664:
4280:
2122:
2057:Page, Daniel (2009). "11. Compilers".
2338:
2243:
2005:
1972:Introduction to Computer Science CS 0
1534:On systems with multiple processors,
1478:efficiency, or simplify programming.
1274:
875:
211:model of implementations of the ISA.
3326:Floating-point operations per second
2056:
1968:"Instruction Set Architecture (ISA)"
1318:, typically integral multiples of a
1242:
685:moving large blocks of memory (e.g.
468:
237:maintains a standard and compatible
195:, fundamental features (such as the
191:, the hardware support for managing
2198:Ganssle, Jack (February 26, 2001).
1795:
477:Data handling and memory operations
13:
2237:
1965:
1833:"RISC Architecture: RISC vs. CISC"
812:add contents of memory to register
300:at IBM during the design phase of
14:
4314:
2306:
1509:use codes in the range A000..AFFF
1444:
1401:Minimal instruction set computers
1375:Reduced instruction-set computers
1360:Complex Instruction Set Computers
1302:reduced instruction set computers
1283:to many hundreds of bits in some
839:transport triggered architectures
214:An ISA specifies the behavior of
4252:Semiconductor device fabrication
2312:
2249:Microprocessors and Microsystems
1564:Semiconductor device fabrication
1459:high-level programming languages
1388:Certain embedded RISC ISAs like
402:minimal instruction set computer
367:reduced instruction set computer
363:complex instruction set computer
4227:History of general-purpose CPUs
2454:Nondeterministic Turing machine
2210:
2191:
2155:
2100:
2083:
2050:
1928:Springer Science+Business Media
1806:IBM's 360 and Early 370 Systems
1345:
1307:instructions are a fixed length
1054:, or the same memory location:
660:Perform coprocessor operations.
518:Arithmetic and logic operations
411:
2407:Deterministic finite automaton
1959:
1915:
1884:
1855:
1824:
1766:
1642:field-programmable gate arrays
1554:Instruction set implementation
1403:(MISC) are commonly a form of
887:(In the examples that follow,
818:specifiers, which may specify
1:
4298:Instruction set architectures
3198:Simultaneous and heterogenous
2319:Instruction set architectures
2186:Hennessy & Patterson 2003
2000:Hennessy & Patterson 2003
1985:Hennessy & Patterson 2003
1954:Hennessy & Patterson 2003
1760:
1418:There has been research into
1032:limited to one memory operand
391:instruction-level parallelism
3882:Integrated memory controller
3864:Translation lookaside buffer
3063:Memory dependence prediction
2506:Random-access stored program
2459:Probabilistic Turing machine
2261:10.1016/0141-9331(85)90116-4
1733:No instruction set computing
1536:non-blocking synchronization
1287:systems. Processors used in
406:one-instruction set computer
349:processors in this fashion.
239:application binary interface
148:instruction set architecture
7:
3338:Synaptic updates per second
1696:
1544:load-link/store-conditional
884:specified in instructions.
513:data from hardware devices.
258:
158:that generally defines how
10:
4319:
3742:Heterogeneous architecture
2664:Orthogonal instruction set
2434:Alternating Turing machine
2422:Quantum cellular automaton
2283:Morgan Kaufmann Publishers
1754:Register transfer language
1708:Compressed instruction set
1585:register transfer language
1557:
1030:CISC — Often machines are
828:very long instruction word
753:instructions that perform
603:Floating-point instruction
591:of each bit in a register.
489:to a fixed constant value.
419:is built up from discrete
374:very long instruction word
18:
4232:Microprocessor chronology
4219:
4195:Dynamic frequency scaling
4168:
4104:
4042:
3996:
3948:
3903:
3823:
3750:
3719:
3624:
3545:
3509:
3463:
3363:
3350:Cache performance metrics
3289:
3223:
3173:
3084:
3075:
3048:
3003:
2970:
2942:
2933:
2753:
2656:
2645:
2516:
2372:
2149:10.1109/ICCD.2009.5413117
2061:. Springer. p. 464.
1723:Instruction set simulator
1682:(DSP) must use a kind of
1468:
762:instruction sets include
698:floating-point arithmetic
4247:Hardware security module
3590:Digital signal processor
3567:Graphics processing unit
3379:Graphics processing unit
1680:digital signal processor
1638:reconfigurable computing
841:(TTA), only operand(s).
706:transcendental functions
696:complicated integer and
652:Coprocessor instructions
339:Just-in-time compilation
4288:Central processing unit
4200:Dynamic voltage scaling
3983:Memory address register
3877:Branch target predictor
3841:Address generation unit
3584:Physics processing unit
3373:Central processing unit
3332:Transactions per second
3320:Instructions per second
3243:Array processing (SIMT)
2387:Stored-program computer
1664:load–store architecture
1199:, and some versions of
854:reverse Polish notation
613:Control flow operations
449:literal/constant values
335:Common Language Runtime
4293:Instruction processing
4006:Hardwired control unit
3888:Memory management unit
3853:Memory management unit
3602:Secure cryptoprocessor
3596:Tensor Processing Unit
3578:Vision processing unit
3312:Cycles per instruction
3306:Instructions per cycle
3253:Associative processing
2944:Instruction pipelining
2366:Processor technologies
1612:writable control store
1546:" (LL/SC), or "atomic
1420:executable compression
1160:add reg1+reg2->reg3
803:
437:any explicit operands:
353:Classification of ISAs
311:
267:, which is the set of
4089:Sum-addressed decoder
3835:Arithmetic logic unit
2962:Classic RISC pipeline
2916:Epiphany architecture
2763:Motorola 68000 series
2200:"Proactive Debugging"
1713:Computer architecture
1598:Other designs employ
1424:Kolmogorov complexity
912:zero-address machines
800:
744:instruction or other
740:performing an atomic
455:used to access memory
379:long instruction word
321:as their ISA such as
306:
21:Computer architecture
4210:Performance per watt
3788:replacement policies
3454:Package on a package
3344:Performance per watt
3248:Pipelined processing
3018:Tomasulo's algorithm
2823:Clipper architecture
2679:Application-specific
2392:Finite-state machine
2321:at Wikimedia Commons
1843:on February 21, 2015
1684:Harvard architecture
1668:instruction pipeline
1660:instruction pipeline
1435:optimizing compilers
1326:. Some, such as the
955:accumulator machines
951:one-address machines
793:Instruction encoding
665:Complex instructions
639:to another location.
628:Conditionally branch
372:Other types include
327:Java virtual machine
220:binary compatibility
4242:Digital electronics
3895:Instruction decoder
3847:Floating-point unit
3501:Soft microprocessor
3448:System in a package
3023:Reservation station
2553:Transport-triggered
2273:Patterson, David A.
2110:. Intel Corporation
2067:2009pica.book.....P
2038:10.1147/rd.341.0004
1688:multiply–accumulate
1647:An ISA can also be
1579:When designing the
1491:MOS Technology 6502
573:, e.g., taking the
287:x86 instruction set
104:Execute instruction
4114:Integrated circuit
3958:Processor register
3612:Baseband processor
2957:Operand forwarding
2417:Cellular automaton
2281:(Third ed.).
2245:Bowen, Jonathan P.
1651:in software by an
1636:CPUs designed for
1626:processor and the
1487:software interrupt
1383:instruction length
1289:personal computers
1275:Instruction length
1066:three instructions
985:three instructions
876:Number of operands
870:branch predication
814:—and zero or more
804:
749:atomic instruction
571:bitwise operations
292:The concept of an
228:microarchitectures
197:memory consistency
99:Repeat instruction
4275:
4274:
4164:
4163:
3783:Instruction cache
3773:Scratchpad memory
3620:
3619:
3607:Network processor
3536:Network on a chip
3491:Ultra-low-voltage
3442:Multi-chip module
3285:
3284:
3071:
3070:
3058:Branch prediction
3035:Register renaming
2929:
2928:
2911:VISC architecture
2733:Quantum computing
2728:VISC architecture
2610:Secondary storage
2526:Microarchitecture
2486:Register machines
2317:Media related to
2269:Hennessy, John L.
2076:978-1-84882-255-9
1937:978-1-4615-0237-1
1581:microarchitecture
1574:programming model
1455:assembly language
1248:Register pressure
1243:Register pressure
1174:four instructions
1097:four instructions
1034:per instruction:
942:four instructions
746:read-modify-write
636:Indirectly branch
469:Instruction types
265:microarchitecture
140:
139:
4310:
4237:Processor design
4129:Power management
4011:Instruction unit
3872:Branch predictor
3821:
3820:
3519:System on a chip
3461:
3460:
3301:Transistor count
3225:Flynn's taxonomy
3082:
3081:
2940:
2939:
2743:Addressing modes
2654:
2653:
2600:Memory hierarchy
2464:Hypercomputation
2382:Abstract machine
2359:
2352:
2345:
2336:
2335:
2316:
2302:
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2014:
2003:
1997:
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1957:
1951:
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1941:
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1913:
1912:
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1888:
1882:
1881:
1878:10.1109/2.820037
1859:
1853:
1852:
1850:
1848:
1839:. Archived from
1828:
1822:
1821:
1809:
1799:
1793:
1792:
1790:
1789:
1780:. Archived from
1770:
1744:Processor design
1568:Silicon compiler
1560:Processor design
1548:compare-and-swap
1368:addressing modes
1309:
1308:
1281:microcontrollers
1171:
1165:
1161:
1157:
1153:
1143:two instructions
1140:
1134:
1130:
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1112:
1094:
1088:
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1080:
1076:
1063:
1057:
1053:
1049:
1045:
1041:
1037:
1019:two instructions
1016:
1006:
998:
982:
976:
972:
968:
959:microcontrollers
939:
933:
929:
925:
921:
824:addressing modes
731:
730:
605:
604:
562:
561:
554:
553:
453:addressing modes
417:Machine language
382:
315:virtual machines
269:processor design
235:operating system
201:addressing modes
144:computer science
132:
125:
118:
36:General concepts
26:
25:
4318:
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4313:
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4309:
4308:
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4303:Microprocessors
4278:
4277:
4276:
4271:
4257:Tick–tock model
4215:
4171:
4160:
4100:
4084:Address decoder
4038:
3992:
3988:Program counter
3963:Status register
3944:
3899:
3859:Load–store unit
3826:
3819:
3746:
3715:
3616:
3573:Image processor
3548:
3541:
3511:
3505:
3481:Microcontroller
3471:Embedded system
3459:
3359:
3292:
3281:
3219:
3169:
3067:
3044:
3028:Re-order buffer
2999:
2980:Data dependency
2966:
2925:
2755:
2749:
2648:
2647:Instruction set
2641:
2627:Multiprocessing
2595:Cache hierarchy
2588:Register/memory
2512:
2412:Queue automaton
2368:
2363:
2309:
2297:
2295:
2293:
2240:
2238:Further reading
2235:
2226:
2224:
2216:
2215:
2211:
2196:
2192:
2184:
2180:
2171:
2169:
2167:cs.stanford.edu
2163:"RISC vs. CISC"
2161:
2160:
2156:
2140:10.1.1.398.1967
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1837:cs.stanford.edu
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1800:
1796:
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1771:
1767:
1763:
1728:Micro-operation
1699:
1570:
1558:Main articles:
1556:
1512:
1504:
1496:
1489:. For example,
1471:
1447:
1348:
1332:Thumb-extension
1316:variable length
1306:
1305:
1277:
1245:
1223:architectures.
1169:
1163:
1159:
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1132:
1128:
1120:one instruction
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773:parallelization
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544:status register
540:condition codes
520:
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261:
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92:Indirect branch
44:Instruction set
24:
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4262:Pin grid array
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4108:
4102:
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4099:
4098:
4096:Barrel shifter
4093:
4092:
4091:
4086:
4079:Binary decoder
4076:
4075:
4074:
4064:
4059:
4054:
4048:
4046:
4040:
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4013:
4008:
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3990:
3985:
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3975:
3970:
3968:Stack register
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3564:
3562:AI accelerator
3559:
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3533:
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3525:Multiprocessor
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3498:
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3483:
3478:
3476:Microprocessor
3473:
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3465:
3464:By application
3458:
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3407:Tile processor
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3193:Hyperthreading
3185:
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3175:Multithreading
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2952:Pipeline stall
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2901:z/Architecture
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2605:Virtual memory
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1966:Durand, Paul.
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1507:Motorola 68000
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1445:Representation
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1371:instructions.
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1297:supercomputers
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866:z/Architecture
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127:
120:
112:
109:
108:
107:
106:
101:
96:
95:
94:
84:
76:
75:
71:
70:
69:
68:
63:
62:
61:
56:
54:Illegal opcode
46:
38:
37:
33:
32:
15:
9:
6:
4:
3:
2:
4315:
4304:
4301:
4299:
4296:
4294:
4291:
4289:
4286:
4285:
4283:
4268:
4265:
4263:
4260:
4258:
4255:
4253:
4250:
4248:
4245:
4243:
4240:
4238:
4235:
4233:
4230:
4228:
4225:
4224:
4222:
4218:
4211:
4208:
4206:
4203:
4201:
4198:
4196:
4193:
4191:
4188:
4186:
4183:
4181:
4178:
4177:
4175:
4173:
4167:
4157:
4154:
4152:
4149:
4147:
4144:
4142:
4139:
4137:
4134:
4130:
4127:
4125:
4122:
4120:
4117:
4116:
4115:
4112:
4111:
4109:
4107:
4103:
4097:
4094:
4090:
4087:
4085:
4082:
4081:
4080:
4077:
4073:
4070:
4069:
4068:
4065:
4063:
4060:
4058:
4057:Demultiplexer
4055:
4053:
4050:
4049:
4047:
4045:
4041:
4035:
4032:
4030:
4027:
4024:
4022:
4019:
4017:
4014:
4012:
4009:
4007:
4004:
4003:
4001:
3999:
3995:
3989:
3986:
3984:
3981:
3979:
3978:Memory buffer
3976:
3974:
3973:Register file
3971:
3969:
3966:
3964:
3961:
3959:
3956:
3955:
3953:
3951:
3947:
3939:
3936:
3934:
3931:
3930:
3929:
3926:
3924:
3921:
3919:
3916:
3914:
3913:Combinational
3911:
3910:
3908:
3906:
3902:
3896:
3893:
3889:
3886:
3885:
3883:
3880:
3878:
3875:
3873:
3870:
3865:
3862:
3860:
3857:
3856:
3854:
3851:
3848:
3845:
3842:
3839:
3836:
3833:
3832:
3830:
3828:
3822:
3816:
3813:
3811:
3808:
3806:
3803:
3801:
3798:
3794:
3791:
3789:
3786:
3784:
3781:
3779:
3776:
3774:
3771:
3769:
3766:
3765:
3764:
3761:
3759:
3756:
3755:
3753:
3749:
3743:
3740:
3738:
3735:
3733:
3730:
3728:
3725:
3724:
3722:
3718:
3710:
3707:
3706:
3705:
3702:
3700:
3697:
3695:
3692:
3690:
3687:
3685:
3682:
3680:
3677:
3675:
3672:
3670:
3667:
3665:
3662:
3660:
3657:
3655:
3652:
3650:
3647:
3645:
3642:
3640:
3637:
3635:
3632:
3631:
3629:
3627:
3623:
3613:
3610:
3608:
3605:
3603:
3600:
3597:
3594:
3591:
3588:
3585:
3582:
3579:
3576:
3574:
3571:
3568:
3565:
3563:
3560:
3558:
3555:
3554:
3552:
3550:
3544:
3537:
3534:
3532:
3529:
3526:
3523:
3520:
3517:
3516:
3514:
3508:
3502:
3499:
3497:
3494:
3492:
3489:
3487:
3484:
3482:
3479:
3477:
3474:
3472:
3469:
3468:
3466:
3462:
3455:
3452:
3449:
3446:
3443:
3440:
3438:
3435:
3433:
3430:
3428:
3425:
3423:
3420:
3418:
3415:
3413:
3410:
3408:
3405:
3403:
3400:
3398:
3395:
3393:
3390:
3386:
3383:
3382:
3380:
3377:
3374:
3371:
3370:
3368:
3366:
3362:
3356:
3353:
3351:
3348:
3345:
3342:
3339:
3336:
3333:
3330:
3327:
3324:
3321:
3318:
3313:
3310:
3309:
3307:
3304:
3302:
3299:
3298:
3296:
3294:
3288:
3276:
3273:
3272:
3271:
3268:
3266:
3263:
3259:
3256:
3254:
3251:
3249:
3246:
3244:
3241:
3240:
3239:
3236:
3234:
3231:
3230:
3228:
3226:
3222:
3216:
3213:
3211:
3208:
3206:
3203:
3199:
3196:
3194:
3191:
3190:
3189:
3186:
3184:
3181:
3180:
3178:
3176:
3172:
3166:
3163:
3161:
3158:
3154:
3151:
3150:
3149:
3146:
3142:
3139:
3137:
3134:
3133:
3132:
3129:
3125:
3122:
3120:
3117:
3116:
3115:
3112:
3110:
3107:
3103:
3100:
3098:
3095:
3094:
3093:
3090:
3089:
3087:
3083:
3080:
3078:
3074:
3064:
3061:
3059:
3056:
3055:
3053:
3051:
3047:
3041:
3038:
3036:
3033:
3029:
3026:
3024:
3021:
3020:
3019:
3016:
3014:
3013:Scoreboarding
3011:
3010:
3008:
3006:
3002:
2996:
2995:False sharing
2993:
2991:
2988:
2986:
2983:
2981:
2978:
2977:
2975:
2973:
2969:
2963:
2960:
2958:
2955:
2953:
2950:
2949:
2947:
2945:
2941:
2938:
2936:
2932:
2922:
2919:
2917:
2914:
2912:
2909:
2906:
2902:
2899:
2897:
2894:
2892:
2889:
2887:
2884:
2883:
2881:
2879:
2876:
2874:
2871:
2869:
2866:
2864:
2861:
2859:
2856:
2854:
2851:
2849:
2846:
2844:
2841:
2839:
2836:
2834:
2831:
2829:
2826:
2824:
2821:
2817:
2814:
2812:
2809:
2807:
2804:
2803:
2801:
2799:
2796:
2794:
2791:
2789:
2788:Stanford MIPS
2786:
2784:
2781:
2779:
2776:
2774:
2771:
2769:
2766:
2764:
2761:
2760:
2758:
2752:
2744:
2741:
2740:
2739:
2736:
2734:
2731:
2729:
2726:
2724:
2721:
2719:
2716:
2714:
2711:
2709:
2706:
2702:
2699:
2698:
2697:
2694:
2690:
2687:
2686:
2685:
2682:
2680:
2677:
2675:
2672:
2670:
2667:
2665:
2662:
2661:
2659:
2655:
2652:
2650:
2649:architectures
2644:
2638:
2635:
2633:
2630:
2628:
2625:
2623:
2620:
2618:
2617:Heterogeneous
2615:
2611:
2608:
2606:
2603:
2602:
2601:
2598:
2596:
2593:
2589:
2586:
2584:
2581:
2579:
2576:
2574:
2571:
2570:
2569:
2568:Memory access
2566:
2564:
2561:
2559:
2556:
2554:
2551:
2549:
2546:
2542:
2539:
2538:
2537:
2534:
2532:
2529:
2527:
2524:
2523:
2521:
2519:
2515:
2507:
2504:
2502:
2501:Random-access
2499:
2497:
2494:
2492:
2489:
2488:
2487:
2484:
2482:
2481:Stack machine
2479:
2477:
2474:
2470:
2467:
2465:
2462:
2460:
2457:
2455:
2452:
2450:
2447:
2445:
2442:
2440:
2437:
2435:
2432:
2431:
2430:
2427:
2423:
2420:
2418:
2415:
2413:
2410:
2408:
2405:
2403:
2400:
2398:
2397:with datapath
2395:
2394:
2393:
2390:
2388:
2385:
2383:
2380:
2379:
2377:
2375:
2371:
2367:
2360:
2355:
2353:
2348:
2346:
2341:
2340:
2337:
2331:
2328:
2326:
2323:
2320:
2315:
2311:
2310:
2294:
2292:1-55860-724-2
2288:
2284:
2280:
2279:
2274:
2270:
2266:
2262:
2258:
2254:
2250:
2246:
2242:
2241:
2223:
2219:
2213:
2205:
2201:
2194:
2187:
2182:
2168:
2164:
2158:
2150:
2146:
2141:
2136:
2132:
2125:
2109:
2103:
2095:
2094:
2086:
2078:
2072:
2068:
2064:
2060:
2053:
2039:
2035:
2031:
2027:
2020:
2013:
2011:
2009:
2002:, p. 93.
2001:
1996:
1994:
1987:, p. 92.
1986:
1981:
1973:
1969:
1962:
1955:
1950:
1948:
1939:
1933:
1929:
1925:
1918:
1902:
1898:
1894:
1887:
1879:
1875:
1871:
1867:
1866:
1858:
1842:
1838:
1834:
1827:
1819:
1817:0-262-16123-0
1813:
1810:. MIT Press.
1808:
1807:
1798:
1784:on 2023-11-11
1783:
1779:
1775:
1769:
1765:
1755:
1752:
1750:
1747:
1745:
1742:
1739:
1736:
1734:
1731:
1729:
1726:
1724:
1721:
1719:
1716:
1714:
1711:
1709:
1706:
1704:
1701:
1700:
1694:
1692:
1689:
1685:
1681:
1675:
1673:
1669:
1665:
1661:
1656:
1654:
1650:
1645:
1643:
1639:
1634:
1632:
1629:
1625:
1617:
1613:
1609:
1605:
1601:
1597:
1594:
1593:
1592:
1590:
1586:
1582:
1577:
1575:
1569:
1565:
1561:
1551:
1549:
1545:
1541:
1540:fetch-and-add
1537:
1532:
1530:
1526:
1521:
1519:
1514:
1508:
1500:
1492:
1488:
1484:
1479:
1477:
1466:
1464:
1460:
1456:
1452:
1442:
1440:
1436:
1432:
1427:
1425:
1421:
1416:
1414:
1410:
1406:
1405:stack machine
1402:
1398:
1395:
1391:
1386:
1384:
1380:
1376:
1372:
1369:
1365:
1361:
1356:
1354:
1343:
1339:
1337:
1333:
1329:
1325:
1321:
1317:
1313:
1303:
1298:
1294:
1290:
1286:
1282:
1272:
1269:
1265:
1261:
1256:
1254:
1249:
1240:
1238:
1233:
1229:
1224:
1222:
1218:
1214:
1210:
1206:
1202:
1198:
1189:
1185:
1178:
1175:
1168:
1167:
1149:
1144:
1137:
1136:
1126:
1121:
1114:
1113:
1108:
1107:
1105:
1098:
1091:
1090:
1083:add reg1,reg2
1072:
1067:
1060:
1059:
1033:
1029:
1024:
1020:
1013:
1012:
1010:
1002:
994:
993:
991:
986:
979:
978:
964:
960:
956:
953:), so called
952:
948:
943:
936:
935:
917:
914:), so called
913:
909:
908:
904:
902:
898:
894:
890:
885:
883:
873:
871:
867:
861:
859:
855:
851:
847:
842:
840:
835:
833:
829:
825:
821:
817:
813:
809:
799:
790:
788:
786:
782:
778:
774:
769:
765:
756:
752:
750:
747:
743:
739:
737:
733:
728:
722:
719:
715:
711:
707:
703:
699:
695:
692:
688:
684:
681:
677:
676:
675:
672:
659:
656:
655:
646:
645:
641:
638:
637:
633:
630:
629:
625:
622:
621:
617:
616:
607:
599:
596:
593:
590:
589:
584:
583:
578:
577:
572:
568:
563:
555:
548:
547:
545:
541:
537:
533:
529:
525:
522:
521:
512:
508:
505:
502:
498:
494:
491:
488:
484:
481:
480:
474:
466:
464:
454:
451:
448:
446:
443:
442:
441:
440:
436:
433:
430:
429:
428:
426:
422:
418:
409:
407:
403:
398:
396:
392:
388:
387:
380:
375:
370:
368:
364:
360:
350:
348:
344:
340:
336:
332:
328:
324:
320:
317:that support
316:
310:
305:
303:
299:
295:
290:
288:
284:
281:
277:
274:
270:
266:
256:
254:
249:
247:
242:
240:
236:
231:
229:
225:
221:
217:
212:
210:
206:
202:
198:
194:
190:
186:
182:
177:
176:of that ISA.
175:
174:
169:
165:
162:controls the
161:
157:
153:
149:
145:
133:
128:
126:
121:
119:
114:
113:
111:
110:
105:
102:
100:
97:
93:
90:
89:
88:
85:
83:
80:
79:
78:
77:
73:
72:
67:
64:
60:
57:
55:
52:
51:
50:
47:
45:
42:
41:
40:
39:
35:
34:
31:
28:
27:
22:
4267:Chip carrier
4205:Clock gating
4124:Mixed-signal
4021:Write buffer
3998:Control unit
3810:Clock signal
3549:accelerators
3531:Cypress PSoC
3188:Simultaneous
3005:Out-of-order
2646:
2637:Neuromorphic
2518:Architecture
2476:Belt machine
2469:Zeno machine
2402:Hierarchical
2296:. Retrieved
2277:
2252:
2248:
2225:. Retrieved
2222:cpushack.net
2221:
2212:
2204:embedded.com
2203:
2193:
2181:
2170:. Retrieved
2166:
2157:
2130:
2124:
2112:. Retrieved
2102:
2092:
2085:
2058:
2052:
2041:. Retrieved
2029:
2025:
1980:
1971:
1961:
1923:
1917:
1905:. Retrieved
1900:
1896:
1886:
1872:(2): 37–45.
1869:
1863:
1857:
1847:February 21,
1845:. Retrieved
1841:the original
1836:
1826:
1805:
1797:
1786:. Retrieved
1782:the original
1777:
1768:
1676:
1657:
1646:
1635:
1621:
1606:or writable
1589:control unit
1578:
1571:
1533:
1522:
1515:
1480:
1472:
1451:machine code
1448:
1428:
1417:
1399:
1387:
1374:
1373:
1359:
1357:
1353:code density
1352:
1349:
1346:Code density
1340:
1335:
1331:
1278:
1257:
1247:
1246:
1227:
1225:
1193:
1173:
1164:store reg3,c
1142:
1133:add reg1,b,c
1119:
1096:
1087:store reg2,c
1065:
1044:store reg1,c
1025:instruction.
1022:
1018:
1008:
1000:
984:
950:
941:
911:
900:
896:
892:
888:
886:
881:
879:
862:
843:
836:
811:
805:
789:
760:
742:test-and-set
723:
691:DMA transfer
668:
642:
634:
626:
618:
600:
594:
586:
580:
574:
557:
549:
535:
531:
527:
523:
510:
506:
496:
492:
482:
472:
463:control flow
460:
425:instructions
424:
420:
415:
412:Instructions
399:
384:
378:
371:
358:
356:
312:
307:
294:architecture
293:
291:
262:
250:
246:machine code
243:
232:
216:machine code
213:
209:input/output
181:instructions
178:
171:
151:
147:
141:
74:Instructions
59:Opcode table
43:
30:Machine code
4052:Multiplexer
4016:Data buffer
3727:Single-core
3699:bit slicing
3557:Coprocessor
3412:Coprocessor
3293:performance
3215:Cooperative
3205:Speculative
3165:Distributed
3124:Superscalar
3109:Instruction
3077:Parallelism
3050:Speculative
2882:System/3x0
2754:Instruction
2531:Von Neumann
2444:Post–Turing
2032:(1): 4–11.
1653:interpreter
1483:system call
1156:load b,reg2
1152:load a,reg1
1129:move a,reg1
1079:load b,reg2
1075:load a,reg1
1036:load a,reg1
963:accumulator
949:1-operand (
910:0-operand (
729:instruction
702:square root
687:string copy
582:disjunction
576:conjunction
503:operations.
404:(MISC) and
298:Fred Brooks
224:performance
207:), and the
193:main memory
4282:Categories
4172:management
4067:Multiplier
3928:Logic gate
3918:Sequential
3825:Functional
3805:Clock rate
3778:Data cache
3751:Components
3732:Multi-core
3720:Core count
3210:Preemptive
3114:Pipelining
3097:Bit-serial
3040:Wide-issue
2985:Structural
2907:Tilera ISA
2873:MicroBlaze
2843:ETRAX CRIS
2738:Comparison
2583:Load–store
2563:Endianness
2298:2023-03-04
2227:2014-07-25
2172:2021-12-18
2043:2022-10-05
1788:2024-02-03
1761:References
1749:Simulation
1691:multiplier
1672:delay slot
1618:, or both.
1413:multi-core
1293:mainframes
1228:explicitly
1040:add b,reg1
882:explicitly
421:statements
359:complexity
302:System/360
185:data types
4106:Circuitry
4026:Microcode
3950:Registers
3793:coherence
3768:CPU cache
3626:Word size
3291:Processor
2935:Execution
2838:DEC Alpha
2816:Power ISA
2632:Cognitive
2439:Universal
2135:CiteSeerX
2114:5 October
1670:led to a
1644:(FPGAs).
1600:microcode
1525:NOP slide
1499:Zilog Z80
1463:compilers
1312:word size
1217:Power ISA
1201:ARM Thumb
1197:TI MSP430
1111:add a,b,c
850:0-operand
832:microcode
820:registers
802:constant.
710:logarithm
682:) at once
560:decrement
552:increment
445:registers
343:Transmeta
331:Microsoft
323:Smalltalk
253:computing
189:registers
4044:Datapath
3737:Manycore
3709:variable
3547:Hardware
3183:Temporal
2863:OpenRISC
2558:Cellular
2548:Dataflow
2541:modified
2275:(2003).
1907:March 2,
1865:Computer
1718:Emulator
1697:See also
1649:emulated
1640:may use
1624:Rekursiv
1431:compiler
1411:or in a
1324:halfword
1304:(RISC),
906:C = A+B
708:such as
671:typified
588:negation
569:Perform
532:multiply
528:subtract
487:register
395:compiler
319:bytecode
278:and the
259:Overview
160:software
154:) is an
4220:Related
4151:Quantum
4141:Digital
4136:Boolean
4034:Counter
3933:Quantum
3694:512-bit
3689:256-bit
3684:128-bit
3527:(MPSoC)
3512:on chip
3510:Systems
3328:(FLOPS)
3141:Process
2990:Control
2972:Hazards
2858:Itanium
2853:Unicore
2811:PowerPC
2536:Harvard
2496:Pointer
2491:Counter
2449:Quantum
2063:Bibcode
1778:arm.com
1493:uses 00
1433:. Most
1253:spilled
1170:C = A+B
1139:C = A+B
1116:C = A+B
1093:C = A+B
1062:C = A+B
1056:A = A+B
1052:C = A+B
1015:C = A+B
1003:; then
995:CISC —
981:C = A+B
975:store c
938:C = A+B
816:operand
785:AltiVec
720:, etc.)
595:Compare
276:Pentium
66:Operand
4156:Switch
4146:Analog
3884:(IMC)
3855:(MMU)
3704:others
3679:64-bit
3674:48-bit
3669:32-bit
3664:24-bit
3659:16-bit
3654:15-bit
3649:12-bit
3486:Mobile
3402:Stream
3397:Barrel
3392:Vector
3381:(GPU)
3340:(SUPS)
3308:(IPC)
3160:Memory
3153:Vector
3136:Thread
3119:Scalar
2921:Others
2868:RISC-V
2833:SuperH
2802:Power
2798:MIPS-X
2773:PDP-11
2622:Fabric
2374:Models
2289:
2137:
2073:
1934:
1814:
1738:OVPsim
1566:, and
1505:while
1469:Design
1295:, and
1219:, and
1172:needs
1141:needs
1118:needs
1095:needs
1064:needs
1017:needs
997:move A
983:needs
967:load a
940:needs
924:push b
920:push a
895:, and
848:have "
808:opcode
783:, and
781:3DNow!
768:vector
718:cosine
700:(e.g.
620:Branch
536:divide
432:opcode
329:, and
325:, the
283:Athlon
233:If an
168:device
87:Branch
49:Opcode
4212:(PPW)
4170:Power
4062:Adder
3938:Array
3905:Logic
3866:(TLB)
3849:(FPU)
3843:(AGU)
3837:(ALU)
3827:units
3763:Cache
3644:8-bit
3639:4-bit
3634:1-bit
3598:(TPU)
3592:(DSP)
3586:(PPU)
3580:(VPU)
3569:(GPU)
3538:(NoC)
3521:(SoC)
3456:(PoP)
3450:(SiP)
3444:(MCM)
3385:GPGPU
3375:(CPU)
3365:Types
3346:(PPW)
3334:(TPS)
3322:(IPS)
3314:(CPI)
3085:Level
2896:S/390
2891:S/370
2886:S/360
2828:SPARC
2806:POWER
2689:TRIPS
2657:Types
2022:(PDF)
1756:(RTL)
1628:Imsys
1476:cache
1394:AVR32
1390:Thumb
1336:mixed
1334:have
1330:with
1322:or a
1268:Alpha
1260:Thumb
1237:arity
1232:stack
1221:SPARC
1209:AVR32
1023:store
1005:add B
971:add b
932:pop c
858:stack
844:Most
704:, or
680:stack
542:in a
534:, or
511:write
381:(LIW)
313:Some
273:Intel
146:, an
4190:ACPI
3923:Glue
3815:FIFO
3758:Core
3496:ASIP
3437:CPLD
3432:FPOA
3427:FPGA
3422:ASIC
3275:SPMD
3270:MIMD
3265:MISD
3258:SWAR
3238:SIMD
3233:SISD
3148:Data
3131:Task
3102:Word
2848:M32R
2793:MIPS
2756:sets
2723:ZISC
2718:NISC
2713:OISC
2708:MISC
2701:EPIC
2696:VLIW
2684:EDGE
2674:RISC
2669:CISC
2578:HUMA
2573:NUMA
2287:ISBN
2116:2022
2071:ISBN
1932:ISBN
1909:2023
1849:2015
1812:ISBN
1631:Cjip
1616:PLAs
1608:RAMs
1604:ROMs
1542:", "
1523:The
1409:FPGA
1392:and
1379:RISC
1364:CISC
1320:byte
1285:VLIW
1266:and
1264:MIPS
1213:MIPS
901:reg1
764:SIMD
727:SIMD
714:sine
644:Call
579:and
509:and
507:Read
497:move
493:Copy
383:and
361:. A
347:VLIW
4185:APM
4180:PMU
4072:CPU
4029:ROM
3800:Bus
3417:PAL
3092:Bit
2878:LMC
2783:ARM
2778:x86
2768:VAX
2257:doi
2145:doi
2034:doi
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1874:doi
1633:).
1614:),
1550:".
1529:NOP
1513:.
1485:or
1461:by
1439:GCC
1328:ARM
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1188:VAX
1048:add
1007:to
999:to
928:add
777:MMX
766:or
755:ALU
689:or
524:Add
483:Set
423:or
341:).
333:'s
280:AMD
164:CPU
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