225:, the system was later redeployed to the Army Corps of Engineers in Vicksburg, Mississippi, for dam stress analysis. ASC #4 was used by NOAA at Princeton University for developing weather forecasting models. ASC systems #5 and #6 were installed at TI's main plant in Austin and also used by GSI for seismic data processing. ASC #7 went to the Naval Research Lab in Washington, D.C. for plasma physics studies.
152:
allowing the CPU to produce one to four vector results every cycle, depending on the number of vector lanes installed. The vector lanes were also used for scalar instructions, and each lane could keep up to 12 scalar instructions in-flight simultaneously. The CPU, with four lanes, allowed up to 36 instructions in total across the entire CPU.
126:-based memory for the eight processor ports, and handling all communications to the 24-bit address space in main memory. The MCU was designed to operate asynchronously, allowing it to work at a variety of speeds and scale across a number of performance points. For instance, main memory could be constructed out of slower but less expensive
118:. Memory was accessed solely under the control of the memory control unit (MCU). The MCU was a two-way, 256-bit per channel parallel network that could support up to eight independent processors, with a ninth channel for accessing "main memory" (referred to as "extended memory"). The MCU also acted as a
220:
The ASC #1 prototype was a one pipe system and brought up in Austin, Texas, off site from TI's main plant for proprietary information reasons. It was later upgraded to two pipes and renamed as ASC # 1A. It was then used by TI's GSI division for seismic data processing. ASC #2 was leased to Shell Oil
163:
tended to be memory bandwidth-limited, that is, they could process data faster than they could get it from memory. This remains a major problem on modern SIMD designs as well, which is why considerable effort has been put into increasing memory throughput in modern computer designs (although largely
155:
The processor had forty-eight 32-bit registers, a huge number for the time. 16 of the registers were used for addressing, 16 for scalar operations, 8 for index offsets, and 8 for specifying the various parameters for vector instructions. Data was moved between the registers and memory by load/store
176:
and registers, and the system could thus run eight programs at the same time, limited only by memory accesses. Keeping eight programs running allowed the system to shuffle execution of programs on the CPU depending on what data was available on the memory bus at that time, minimizing "dead time"
151:
arithmetic and mathematical instructions that operated on scalars, vectors, or matrices. The vector processing facilities had a memory-to-memory architecture; where the vector operands were read from, and the resulting vector written to, memory. The CPU could have one, two, or four vector lanes,
211:
was announced in 1975. The Cray-1 dedicated almost all of its design to sustained high-speed access to memory, including over one million 64-bit words of semiconductor memory and a cycle time that was one-fifth that of the ASC (12.5 ns). Although the ASC was in some ways a more expandable
58:
supercomputer, announced in 1975 that would fully realize and popularize vector processing. The more successful implementation of vector processing in the Cray-1 would demarcate the ASC (and STAR-100) as first-generation vector processors, with the Cray-1 belonging in the second.
130:, although this was not used in practice. At the fastest, it could sustain transfer rates of 80 million 32-bit words per second per port, for a total transfer rate of 640 million words per second. This was well beyond the capabilities of even the fastest memories of the era.
212:
design, in the supercomputer market speed is preferred, and the Cray-1 was much faster. ASC sales ended almost overnight, and although an upgraded ASC had been designed with a cycle time one-fifth that of the original, Texas
Instruments decided to exit the market.
50:
supercomputer (which was introduced in the same year), were the first computers to feature vector processing. However, this technique's potential was not fully realized by either the ASC or STAR-100 due to an insufficient understanding of the technique; it was the
164:
unsuccessfully). In the ASC this was improved somewhat with a lookahead unit that predicted upcoming memory accesses and loaded them into the scalar registers invisibly, using a memory interface in the CPU called the memory buffer unit (MBU).
191:(FFTs). By the time the ASC was in production, better FFT algorithms had been developed that did not require this operation. TI offered a bounty to the first person to come up with a valid use for this instruction, but was never collected.
171:
and programs running within it, as well as feeding data to the CPU. The PP was built out of eight "virtual processors" (VPs), which were designed to handle instructions and basic integer arithmetic only. Each VP had its own
221:
Company in the
Netherlands and also used for seismic data processing. ASC #3 was installed at the Redstone Arsenal in Huntsville, Alabama, for Anti Ballistic Missile Interception technology development. With the
180:
The PP also included a set of sixty-four 32-bit communications registers (CRs). The CRs stored the state required for communication between the various parts of the ASC: the CPU, VPs, and
79:
companies. GSI was now a subsidiary of TI, and TI wanted to apply the latest computer technology to the processing and analysis of seismic datasets. The ASC project started as the
83:. As the project developed, TI decided to expand its scope. "Seismic" was replaced by "Scientific" in the name, allowing the project to retain the designation ASC.
98:, under direction of George R. Trimble, Jr. but later taken over by TI itself. Southern Methodist University in Dallas developed an ALGOL compiler for the ASC.
353:
373:
199:
When ASC machines first became available in the early 1970s, they outperformed almost all other machines, including the
68:
222:
378:
259:
242:
187:
The ASC instruction set include a bit-reverse instruction that was intended to speed up the calculation of
147:
supercomputer. The CPU had an extremely advanced architecture and organization for its era, supporting
133:
The CPU had a 60 ns clock cycle (16.67 MHz clock frequency) and its logic was built from 20-
281:
George R. Trimble Jr. (Summer 2001). "A brief history of computing. Memoirs of living on the edge".
106:
The ASC was based around a single high-speed shared memory, which was accessed by the CPU and eight
44:
43:, a performance-enhancing technique which was key to its high-performance. The ASC, along with the
36:
188:
95:
137:
72:
167:
The "Peripheral
Processor" was a separate system dedicated entirely to quickly running the
8:
340:
298:
181:
140:
32:
302:
290:
168:
160:
87:
40:
156:
instructions, which could transfer from 4–64 bits (two registers) at a time.
173:
76:
367:
123:
52:
28:
316:
200:
111:
47:
127:
107:
134:
294:
354:
The TI ASC: A Highly
Modular and Flexible Super Computer Architecture
204:
148:
144:
119:
358:
115:
91:
208:
55:
203:, and under certain conditions matched that of the one-off
280:
257:
177:
where the CPU had to wait for data from the memory.
247:. McGraw-Hill Publishing Company. 1973. p. 36.
207:. However, only seven had been installed when the
215:
365:
122:controller, offering high-speed access to a
110:controllers, in an organization similar to
337:The Architecture of Pipelined Computers
283:IEEE Annals of the History of Computing
258:George R. Trimble Jr. (June 24, 2005).
251:
366:
94:compiler, were done under contract by
86:Originally the software, including an
35:(TI) between 1966 and 1973. The ASC's
359:TI ASC documentation at bitsavers.org
289:(3). IEEE Computer Society: 44–59.
194:
143:originally developed by TI for the
13:
14:
390:
347:
71:(GSI), a company that performed
69:Geophysical Service Incorporated
101:
309:
274:
235:
216:Vector processing applications
1:
317:"ASC No. 6 used for GSI data"
228:
31:designed and manufactured by
21:Advanced Scientific Computer
7:
374:Texas Instruments computers
10:
395:
67:TI began as a division of
62:
343:. pp. 159–162.
262:. Computer History Museum
81:Advanced Seismic Computer
45:Control Data Corporation
335:Peter M. Kogge (1981).
189:fast Fourier transforms
37:central processing unit
96:Computer Usage Company
379:Vector supercomputers
138:emitter-coupled logic
341:Taylor & Francis
182:channel controllers
141:integrated circuits
114:'s groundbreaking
295:10.1109/85.948905
161:vector processors
41:vector processing
33:Texas Instruments
386:
328:
327:
325:
323:
313:
307:
306:
278:
272:
271:
269:
267:
255:
249:
248:
239:
195:Market reception
169:operating system
88:operating system
39:(CPU) supported
394:
393:
389:
388:
387:
385:
384:
383:
364:
363:
350:
332:
331:
321:
319:
315:
314:
310:
279:
275:
265:
263:
256:
252:
241:
240:
236:
231:
218:
197:
174:program counter
104:
77:oil exploration
65:
17:
12:
11:
5:
392:
382:
381:
376:
362:
361:
356:
349:
348:External links
346:
345:
344:
330:
329:
308:
273:
250:
233:
232:
230:
227:
217:
214:
196:
193:
103:
100:
64:
61:
15:
9:
6:
4:
3:
2:
391:
380:
377:
375:
372:
371:
369:
360:
357:
355:
352:
351:
342:
338:
334:
333:
318:
312:
304:
300:
296:
292:
288:
284:
277:
261:
260:"CUC History"
254:
246:
245:
238:
234:
226:
224:
213:
210:
206:
202:
192:
190:
185:
183:
178:
175:
170:
165:
162:
157:
153:
150:
146:
142:
139:
136:
131:
129:
125:
124:semiconductor
121:
117:
113:
109:
99:
97:
93:
89:
84:
82:
78:
74:
70:
60:
57:
54:
53:Cray Research
49:
46:
42:
38:
34:
30:
29:supercomputer
26:
22:
16:Supercomputer
336:
320:. Retrieved
311:
286:
282:
276:
264:. Retrieved
253:
243:
237:
219:
201:CDC STAR-100
198:
186:
179:
166:
158:
154:
132:
112:Seymour Cray
105:
102:Architecture
85:
80:
75:surveys for
66:
24:
20:
18:
244:Electronics
223:SALT Treaty
128:core memory
108:I/O channel
368:Categories
322:August 10,
229:References
149:microcoded
205:ILLIAC IV
145:ILLIAC IV
116:CDC 6600
48:STAR-100
303:5259268
266:May 30,
92:FORTRAN
73:seismic
63:History
27:) is a
301:
209:Cray-1
90:and a
56:Cray-1
299:S2CID
159:Most
120:cache
324:2024
268:2010
135:gate
19:The
291:doi
25:ASC
370::
339:.
297:.
287:23
285:.
184:.
326:.
305:.
293::
270:.
23:(
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.