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reduced costs of around ÂŁ5,000 per design plus manufacturing costs of ÂŁ1-2 per chip in high volumes, in contrast to the ÂŁ15,000 design costs incurred by engaging
Ferranti's services for the design process. Based on a PDP-11/23 minicomputer running RSX/11M, together with graphical display, keyboard, "digitalizing board", control desk and optional plotter, the solution aimed to satisfy the design needs of gate arrays from 100 to 10,000 gates, with the design being undertaken entirely by the organisation acquiring the solution, starting with a "logic plan", proceeding through the layout of the logic in the gate array itself, and concluding with the definition of a test specification for verification of the logic and for establishing an automated testing regime. Verification of completed designs was performed by "external specialists" after the transfer of the design to a "CAD center" in Manchester, England or Sunnyvale, California, potentially over the telephone network. Prototyping completed designs took an estimated 3 to 4 weeks. The minicomputer itself was also adaptable to run as a laboratory or office system where appropriate.
405:
editing capabilities". The software itself was available separately for organisations already likely to be using VAX-11/780 systems to provide a multi-user environment, but the "standalone system" package of hardware and software was intended to provide a more affordable solution with a "faster response" during the design process. The suite of tools involved in the use of the product included logic entry and test schedule definition (using
Ferranti's own description languages), logic simulation, layout definition and checking, and mask generation for prototype gate arrays. The system also sought to support completely auto-routed designs, utilising architectural features of Ferranti's auto-routable (AR) arrays to deliver a "100-percent success auto-layout system" with this convenience incurring an increase in silicon area of approximately 25 percent.
335:
They were also well under the performance of the existing dominant logic technology, transistor–transistor logic families. However, there were many niche applications where they were invaluable, particularly in low power, size reduction, portable and aerospace applications as well as time-to-market sensitive products. Even these small arrays could replace a board full of transistor–transistor logic gates if performance were not an issue. A common application was combining a number of smaller circuits that were supporting a larger LSI circuit on a board was affectionately known as "garbage collection". And the low cost of development and custom tooling made the technology available to the most modest budgets. Early gate arrays played a large part in the
319:
448:(CPLD), metal configurable standard cells (MCSC), and structured ASICs. Whereas a gate array required a back-end semiconductor wafer foundry to deposit and etch the interconnections, the FPGA and CPLD had user-programmable interconnections. Today's approach is to make the prototypes by FPGAs, as the risk is low and the functionality can be verified quickly. For smaller devices, production costs are sufficiently low. But for large FPGAs, production is very expensive, power-hungry, and in many cases, do not reach the required speed. To address these issues, several ASIC companies like BaySand, Faraday, Gigoptics, and others offer FPGA to ASIC conversion services.
358:. Their initial intention was to commercialize emitter coupled logic gate arrays, but discovered the market was quickly moving towards CMOS. Instead, they licensed CDI's silicon gate CMOS line as a second source. This product established them in the market while they developed their own proprietary 5-micron 2-layer metal line. This latter product line was the first commercial gate array product amenable to full automation. LSI developed a suite of proprietary development tools that allowed users to design their own chip from their own facility by remote login to LSI Logic's system.
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densities of up to 1,200 gates. A couple of years later, CDI followed up with "channel-less" gate arrays that reduced the row blockages caused by a more complex silicon underlayer that pre-wired the individual transistor connections to locations needed for common logic functions, simplifying the first-level metal interconnect. This increased chip densities by 40%, significantly reducing manufacturing costs.
306:
drawings were still manual and then "hand" digitized. PC boards, meanwhile, had moved from custom rubylith to PC tape for interconnects. IMI created to-scale photo enlargements of the base layers. Using decals of logic gate connections and PC tape to interconnect these gates, custom circuits could be quickly laid out by hand for these relatively small circuits, and photo-reduced using existing technologies.
1522:
554:. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. The creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a
409:
broadly similar to those of
Ferranti's products including automatic layout, routing, rule checking and simulation functionality for the design of gate arrays. Qudos employed electron beam lithography, etching designs onto Ferranti ULA devices that formed the physical basis of these custom chips. Typical prototype production costs were stated as ÂŁ100 per chip. Quickchip was subsequently ported to the
22:
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to keep their fab plants full and afford constant modernization in a fast-moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on production revenues.
301:
somewhat tedious and error-prone due to the lack of good software tools. IMI tapped into PC board development techniques to minimize manual customization effort. Chips at the time were designed by hand, drawing all components and interconnecting on precision gridded Mylar sheets, using colored pencils to delineate each processing layer.
249:
around 30 percent. Ferranti's "major competitors" were other
British companies such as Marconi and Plessey, both of which had licensed technology from another British company, Micro Circuit Engineering. A contemporary initiative, UK5000, also sought to produce a CMOS gate array with "5,000 usable gates", with involvement from
277:) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp in 1974 for International Microcircuits, Inc. (IMI) a Sunnyvale photo-mask shop started by Frank Deverse, Jim Tuttle and Charlie Allen, ex-IBM employees. This first product line employed
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and associated SRAMs and DRAMs, the bulk of the system logic is implemented in
Fujitsu CG61 0.35-ÎĽm gate arrays, as shown in Table I. (Processor Interface, Crossbar, Memory Interface, Node-to-Node Interface) One additional gate array is implemented in the much less expensive CG51 0.5-ÎĽm process. (I/O
464:
As of the early 21st century, the gate array market was a remnant of its former self, driven by the FPGA conversions done for cost or performance reasons. IMI moved out of gate arrays into mixed-signal circuits and was later acquired by
Cypress Semiconductor in 2001; CDI closed its doors in 1989; and
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during the 1980s that created a boom-bust cycle. The 1980 and 1981–1982 general recessions were followed by high-interest rates that curbed capital spending. This reduction played havoc on the semiconductor business, which at the time was highly dependent on capital spending. Manufacturers desperate
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Early gate arrays were low-performance and relatively large and expensive compared to state-of-the-art n-MOS technology then being used for custom chips. CMOS technology was being driven by very low-power applications such as watch chips and battery-operated portable instrumentation, not performance.
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To reduce the IC count on the video card, a PLA (programmable logic array) and a TTL gate array are used. The gate array implements most of the circuitry of the graphics controller section, including control of the RAM. Compared to discrete circuitry, the gate array consumes one fifth the space, one
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By the early 1980s, gate arrays were starting to move out of their niche applications to the general market. Several factors in technology and markets were converging. Size and performance were increasing; automation was maturing; technology became "hot" when in 1981 IBM introduced its new flagship
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An application circuit must be built on a gate array that has enough gates, wiring, and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many
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Ferranti followed up on the ULA Designer with the
Silicon Design System product based on the VAX-11/730 with 1 MB of RAM, 120 MB Winchester disk, and utilising a high-resolution display driven by a graphics unit with 500 KB of its own memory for "high speed windowing, painting, and
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sheets were then cut and peeled to create a (typically) 200x to 400x scale representation of the process layer. This was then photo-reduced to make a 1x mask. Digitization rather than rubylith cutting was just coming in as the latest technology, but initially, it only removed the rubylith stage;
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All modules utilize LSI Logic LCA100K series gate arrays for the system bus interface and for on-board logic functions. The LSI Logic LCA100K features up to 235K two-input NAND gates. All modules use the same custom I/O driver circuit within their respective gate arrays to drive and receive the
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Other
British companies developed products for gate array design and fabrication. Qudos Limited, a spin-off from Cambridge University, offered a chip design product called Quickchip available for VAX and MicroVAX II systems and as a complete $ 11,000 turnkey solution, providing a suite of tools
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in 1972, expanding to "practically all
European camera manufacturers" as users of the technology, led to the company's dominance in this particular market throughout the 1970s. However, by 1982, as many as 30 companies had started to compete with Ferranti, reducing the company's market share to
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with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is
400:
In an attempt to reduce the costs and increase the accessibility of gate array design and production, Ferranti introduced in 1982 a computer-aided design tool for their uncommitted logic array (ULA) product called ULA Designer. Although costing ÂŁ46,500 to acquire, this tool promised to deliver
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in 2-3 row pairs across the chip; and running all interconnect on grids rather than minimum custom spacing, which had been the standard until then. This later innovation paved the way to full automation when coupled with the development of 2-layer CMOS arrays. Customizing these first parts was
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After a falling out with IMI, Robert Lipp went on to start
California Devices, Inc. (CDI) in 1978 with two silent partners, Bernie Aronson, and Brian Tighe. CDI quickly developed a product line competitive to IMI and, shortly thereafter, a 5-micron silicon gate single-layer product line with
396:
took over much of the personal computer market, and the sales volumes made full-custom chips more economical. Commodore's Amiga series used gate arrays for the Gary and Gayle custom chips, as their code names may suggest.
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system bus. A custom 419-pin pin grid array (PGA) package was developed to house all bus interface gate arrays. ... A minimal DEC 7000 system includes 430,000 gates of logic contained in gate arrays, whereas a minimal
204:, etc.) according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.
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costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced — the same test fixtures can be used for all gate array products manufactured on the same
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are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than
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ULA technology, offering circuits of "100 to 10,000 gates and above" by 1983. The company's early lead in semi-custom chips, with the initial application of a ULA integrated circuit involving a camera from
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The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However, this style is often a viable approach for low production volumes.
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In the UK, Ferranti, with their bipolar collector diffused isolation (CDI) arrays, pioneered the commercial use of gate arrays and for many years this was by far the most widely used technology.
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Designers still wished for a way to create their own complex chips without the expense of full-custom design, and eventually, this wish was granted with the arrival of not only the FPGA, but
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Similar technologies have also been employed to design and manufacture analog, analog-digital, and structured arrays, but, in general, these are not called gate arrays.
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mainframe with CPU comprising gate arrays,; they were used in a consumer product, the ZX81; and new entrants to the market increased visibility and credibility.
289:(CAD) technology at the time was very rudimentary due to the low processing power available, so the design of these first products was only partially automated.
259:
developed proprietary bipolar master slices that it used in mainframe manufacturing in the late 1970s and early 1980s, but never commercialized them externally.
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gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a
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This product pioneered several features that went on to become standard in future designs. The most important were: the strict organization of
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was founded in 1984, and its first products were much like early gate arrays, slow and expensive, fit only for some niche markets. However,
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were implemented by gate arrays as were some graphic terminal functions. Some supporting hardware in at least 1990s
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614:; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.
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as well as a vehicle for the introduction of other later mass-produced products such as modems and cell phones.
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While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling
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The PA 8000s will initially run at 180 MHz, with the rest of the system running at 120 MHz. Except for the
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Bening, L.C.; Brewer, T.M.; Foster, H.D.; Quigley, J.S.; Sussman, R.A.; Vogel, P.F.; Wells, A.W. (1997).
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1340:"Hardware Design of the HP 150 Personal Computer...it's really two products — a computer and a terminal"
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having no predetermined function. These transistors can be connected by metal layers to form standard
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LSI Logic abandoned the market in favor of standard products and was eventually acquired by Broadcom.
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quickly made them a force and, by the early 1990s, were seriously disrupting the gate array market.
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Quick Reference Guide: Discrete Semiconductors, Integrated Circuits, Power Mosfets
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1404:"Physical Design of 0.35-ÎĽm Gate Arrays for Symmetric Multiprocessing Servers"
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chip with components that are later interconnected into logic devices (e.g.
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1455:. Ferranti Semiconductoras. 1983. pp. 147– – via Bitsavers.org.
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CMOS Channeled Gate Arrays: 1991 Data Book and Design Evaluation Guide
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Hardware expansion and software applications for the Archimedes system
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design. The gate array approach reduces the non-recurring engineering
585:) gate arrays were later developed and came to dominate the industry.
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Watkins, J.E.; Brown, P.A.; Szeman, G.; Carrie, S.E. (August 1984).
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The Series 37 CPU chip is a CMOS gate array using nearly 8000 gates.
893:"Silicon Micro-Electronics at British Telecom Research Laboratories"
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1508:. LSI Logic. 1991. pp. 41–54. 13000 – via Bitsavers.org.
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Channelless Gate Arrays: 1990 Data Book and Design Evaluation Guide
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1535:"Inside an unusual 7400-series chip implemented with a gate array"
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and transistor-transistor logic called Micromosaic and Polycell.
1370:"Technical description of the DEC 7000 and DEC 10000 AXP family"
751:. Ferranti Electronic Components Division. March 1977. p. 1
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Gate array master slices with unfinished chips arrayed across a
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843:
Ferranti Discrete and Integrated Circuits Quick Reference Guide
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354:, Bill O'Meara, Rob Walker, and Mitchell "Mick" Bohn founded
1468:. Texas Instruments. 1988. SRG006A – via BitSavers.org.
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single-level metal CMOS technology and ranged from 50 to 400
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size. Gate arrays were the predecessor of the more complex
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also flirted briefly in the late 1960s with bipolar arrays
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and a number of other major British technology companies.
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A gate array is a prefabricated silicon chip with most
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Indirect competition arose with the development of the
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Gate arrays had several concurrent development paths.
1265:. Acorn Computers Limited. September 1988. p. 22
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1086:— article about the ZX Spectrum ULA compatible chip
218:), which also offered linear circuit functions, and
627:determined by estimates such as those derived from
376:. A compatible chip was made in Russia as T34VG1.
101:. Unsourced material may be challenged and removed.
31:
may be too technical for most readers to understand
1311:"Simplicity in a Microcoded Computer Architecture"
1180:"An emerging market for British engineering tools"
1011:The ZX Spectrum ULA: How To Design A Microcomputer
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867:"Great Britain Develops Semicustom and Custom ICs"
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1126:"Ferranti Introduces CAD System for Gate Arrays"
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388:. Many other manufacturers from the time of the
188:is an approach to the design and manufacture of
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1462:TGC100 Series 1-ÎĽm CMOS Gate Arrays Data Sheet
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772:"The Use of Gate Arrays in Telecommunications"
1153:"Automation Cuts Design Time for Gate Arrays"
392:boom period used ULAs in their machines. The
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682:in the early to mid 1980s, including in the
1066:. Computer History Museum. 30 November 2011
507:. Unsourced material may be challenged and
1494:. Fujitsu. 1991 – via Bitsavers.org.
1481:. Fujitsu. 1990 – via Bitsavers.org.
763:
1206:"Universities choose chip design on Beeb"
1132:. No. 105. February 1982. p. 54
631:or by experiments with existing designs.
565:, usually configured as high-performance
527:Learn how and when to remove this message
161:Learn how and when to remove this message
59:Learn how and when to remove this message
43:, without removing the technical details.
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1356:fourth the power, and one half the cost.
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812:"Everybody's talking about Ferranti ICs"
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729:servers was implemented by gate arrays.
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190:application-specific integrated circuits
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897:British Telecommunications Engineering
776:British Telecommunications Engineering
1368:Allison, B.R.; Van Ingen, C. (1992).
1007:
748:The 224 Cell Uncommitted Array Family
41:make it understandable to non-experts
1178:Coffey, Margaret (15 October 1986).
951:
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865:Turmaine, Bradley (6 October 1982).
678:Gate arrays were used widely in the
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505:adding citations to reliable sources
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239:in the UK pioneered commercializing
210:Gate arrays have also been known as
99:adding citations to reliable sources
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561:The earliest gate arrays comprised
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622:requires much more routing than a
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1159:. pp. 197–198, 200, 202, 204
1151:Walker, Anthony V. (March 1984).
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446:complex programmable logic device
413:, with a low-end version for the
384:, and later a single ULA for the
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1309:Amerson, F.C. (September 1985).
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1446:"3. Uncommitted Logic Arrays".
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846:. Ferranti. 1982. pp. IC4
380:used several ULA chips in the
372:, and later used a ULA in the
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770:Grierson, J. R. (July 1983).
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431:field-programmable gate array
368:design to a ULA chip for the
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1533:Shirriff, Ken (March 2024).
1063:LSI Logic oral history panel
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1238:. September 1986. p. 7
567:transistor–transistor logic
411:Acorn Cambridge Workstation
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1130:Wuerzburg Elektronikpraxis
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173:Type of integrated circuit
1377:Digital Technical Journal
1291:. Computer History Museum
990:. Computer History Museum
583:metal–oxide–semiconductor
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275:metal–oxide–semiconductor
1212:. April 1986. p. 15
1106:. March 1982. p. 17
709:In the 1980s, the Forth
212:uncommitted logic arrays
1502:Short Form Catalog 1991
1411:Hewlett-Packard Journal
1347:Hewlett Packard Journal
1318:Hewlett Packard Journal
1014:. ZX Design and Media.
963:Computer History Museum
932:Computer History Museum
899:: 230–236. October 1986
816:British Telecom Journal
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261:Fairchild Semiconductor
1390:includes 94,000 gates.
1044:"Uncommitted IC logic"
958:Lipp, Bob oral history
577:logic configurations.
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265:diode–transistor logic
181:
1499:"Array Based ASICS".
1008:Smith, Chris (2010).
717:Series 37 CPUs, both
571:emitter-coupled logic
556:printed circuit board
337:CB craze in the 1970s
321:
298:p-channel transistors
287:Computer-aided design
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1529:at Wikimedia Commons
1100:"Make chips at home"
1050:. EDN. 5 April 1980.
501:improve this section
95:improve this article
1184:Electronic Business
563:bipolar transistors
364:ported an enhanced
328:Timex Sinclair 1000
1388:VAX 6000 Model 200
1289:The Silicon Engine
988:The Silicon Engine
965:. 14 February 2017
928:The Silicon Engine
658:. You can help by
575:current-mode logic
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1525:Media related to
1186:. pp. 46, 48
822:(4). January 1983
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1527:Gate arrays
1383:(4): 100–.
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1285:"Companies"
850:23 February
793:26 February
755:23 February
711:Novix N4016
688:ZX Spectrum
629:Rent's rule
599:full custom
552:logic gates
541:transistors
439:Moore's Law
374:ZX Spectrum
330:motherboard
231:Development
1424:Interface)
1295:2018-01-28
1242:10 October
1236:Acorn User
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1210:Acorn User
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733:References
700:Advance 86
517:April 2023
458:recessions
314:Innovation
279:7.5 micron
202:flip-flops
198:NAND gates
186:gate array
151:April 2023
121:newspapers
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1439:Databooks
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692:BBC Micro
667:June 2022
488:does not
415:BBC Micro
382:BBC Micro
356:LSI Logic
350:In 1981,
322:Ferranti
294:n-channel
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1269:25 April
984:"People"
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237:Ferranti
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135:scholar
35:Please
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