265:
220:
185:
175:
160:
150:
140:
130:
295:
285:
275:
250:
240:
230:
205:
195:
315:
92:: The block is the only copy of the memory and it is incoherent. This copy was written one or more times. This is the only state that generates a write-back when the block is replaced in the cache.
100:(they are simply listed in reverse order), but this is a simplified form of it that avoids the Read for Ownership operation. Instead, all invalidation is done by writes to main memory.
399:: A partial cache line write is handled as a read miss (if necessary to fetch the unwritten portion of the cache line) followed by a write hit. This leaves all other caches in the
411:
This is a variant of the MESI protocol, but there is no explicit read-for-ownership or broadcast invalidate operation to bring a line into cache in the
35:
defined. It has the optimization of executing write-through on the first write and a write-back on all subsequent writes, reducing the overall
351:
state, the read is interrupted long enough to write the data back to memory before it is allowed to continue. Any copies in the
488:
Archibald, J.; Baer, J. L. (November 1986). "Cache coherence protocols: Evaluation using a multiprocessor simulation model".
423:) cache line performs a write through to memory, which implicitly invalidates other caches. After that, the line is in the
103:
For any given pair of caches, the permitted states of a given cache line are as follows (abbreviated in the order above):
86:: The block is the only copy of the memory, but it is still coherent. No write-back is needed if the block is replaced.
534:
385:
state, a write-through operation is executed updating the block and the memory and the block state is changed to
80:: This block has a coherent copy of the memory. The data may be possibly shared, but its content is not modified.
521:. International Symposium on Computer Architecture: Stockholm, Sweden, June 13–17, 1983. pp. 124–131.
17:
431:) state, and further writes can be done without reference to main memory, leaving the cache line in the
48:
553:
52:
325:
state is erroneous; the write must be written through to memory and so leaves the line in the
519:
Proceedings of the 10th annual international symposium on
Computer architecture - ISCA '83
8:
505:
530:
522:
497:
469:
44:
40:
509:
36:
24:
517:
Goodman, J. R. (1983). "Using cache memory to reduce processor-memory traffic".
314:
67:
In this protocol, each block in the local cache is in one of these four states:
547:
97:
32:
415:
state without performing a main memory write. Instead, the first write to a
474:
457:
344:
526:
501:
96:
These states have exactly the same meanings as the four states of the
56:
337:: The information is supplied by the current cache. No state change.
377:
state, the cache line is updated in place and its state is set to
47:
in (1983). Cache coherence protocols are an important issue in
311:
The protocol follows some transition rules for each event:
458:"Using cache memory to reduce processor-memory traffic"
389:. Other caches snoop the write and set their copies to
347:
by other caches; if any of them have the line in the
381:without updating memory. If the information is in
74:: This block has an incoherent copy of the memory.
343:: The data is read from main memory. The read is
545:
487:
473:
369:: If the information in the cache is in
313:
516:
455:
546:
462:ACM Sigarch Computer Architecture News
39:traffic in consecutive writes to the
403:state, and the current cache in the
13:
14:
565:
293:
283:
273:
263:
248:
238:
228:
218:
203:
193:
183:
173:
158:
148:
138:
128:
449:
306:
1:
442:
321:The "WM" transition from the
319:Write-Once Transition Diagram
43:. It was first described by
7:
18:Write once (disambiguation)
10:
570:
456:Goodman, James R. (1983).
15:
62:
49:Symmetric multiprocessing
490:ACM Trans. Comput. Syst
475:10.1145/1067651.801647
359:states are set to the
330:
527:10.1145/800046.801647
317:
27:protocol literature,
51:systems, where each
16:For other uses, see
331:
502:10.1145/6513.6514
304:
303:
561:
540:
513:
480:
479:
477:
453:
300:
297:
296:
290:
287:
286:
280:
277:
276:
270:
267:
266:
255:
252:
251:
245:
242:
241:
235:
232:
231:
225:
222:
221:
210:
207:
206:
200:
197:
196:
190:
187:
186:
180:
177:
176:
165:
162:
161:
155:
152:
151:
145:
142:
141:
135:
132:
131:
106:
105:
45:James R. Goodman
569:
568:
564:
563:
562:
560:
559:
558:
554:Cache coherency
544:
543:
537:
484:
483:
454:
450:
445:
320:
309:
298:
294:
288:
284:
278:
274:
268:
264:
253:
249:
243:
239:
233:
229:
223:
219:
208:
204:
198:
194:
188:
184:
178:
174:
163:
159:
153:
149:
143:
139:
133:
129:
65:
59:of the memory.
41:computer memory
25:cache coherency
21:
12:
11:
5:
567:
557:
556:
542:
541:
535:
514:
496:(4): 273–298.
482:
481:
468:(3): 124–131.
447:
446:
444:
441:
409:
408:
394:
364:
338:
318:
308:
305:
302:
301:
291:
281:
271:
261:
260: D
257:
256:
246:
236:
226:
216:
215: R
212:
211:
201:
191:
181:
171:
170: V
167:
166:
156:
146:
136:
126:
125: I
122:
121:
120: D
118:
115:
112:
109:
94:
93:
87:
81:
75:
64:
61:
31:was the first
9:
6:
4:
3:
2:
566:
555:
552:
551:
549:
538:
536:0-89791-101-6
532:
528:
524:
520:
515:
511:
507:
503:
499:
495:
491:
486:
485:
476:
471:
467:
463:
459:
452:
448:
440:
438:
434:
430:
426:
422:
418:
414:
406:
402:
398:
395:
392:
388:
384:
380:
376:
372:
368:
365:
362:
358:
354:
350:
346:
342:
339:
336:
333:
332:
328:
324:
316:
312:
292:
282:
272:
262:
259:
258:
247:
237:
227:
217:
214:
213:
202:
192:
182:
172:
169:
168:
157:
147:
137:
127:
124:
123:
119:
117: R
116:
114: V
113:
111: I
110:
108:
107:
104:
101:
99:
98:MESI protocol
91:
88:
85:
82:
79:
76:
73:
70:
69:
68:
60:
58:
54:
50:
46:
42:
38:
34:
33:MESI protocol
30:
26:
19:
518:
493:
489:
465:
461:
451:
436:
432:
428:
424:
420:
416:
412:
410:
404:
400:
396:
390:
386:
382:
378:
374:
370:
366:
360:
356:
352:
348:
340:
334:
326:
322:
310:
102:
95:
89:
83:
77:
71:
66:
55:maintains a
28:
22:
307:Transitions
443:References
397:Write miss
29:Write-Once
439:) state.
429:Exclusive
413:Exclusive
367:Write hit
341:Read miss
548:Category
437:Modified
425:Reserved
419:(a.k.a.
405:Reserved
387:Reserved
375:Reserved
357:Reserved
335:Read hit
327:Reserved
84:Reserved
401:Invalid
391:Invalid
345:snooped
323:Invalid
72:Invalid
533:
510:713808
508:
421:Shared
407:state.
363:state.
329:state.
63:States
506:S2CID
433:Dirty
417:Valid
383:Valid
379:Dirty
371:Dirty
361:Valid
353:Dirty
349:Dirty
90:Dirty
78:Valid
57:cache
531:ISBN
523:doi
498:doi
470:doi
373:or
355:or
53:CPU
37:bus
23:In
550::
529:.
504:.
492:.
466:11
464:.
460:.
539:.
525::
512:.
500::
494:4
478:.
472::
435:(
427:(
393:.
299:N
289:N
279:N
269:Y
254:N
244:N
234:N
224:Y
209:N
199:N
189:Y
179:Y
164:Y
154:Y
144:Y
134:Y
20:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
