328:. Since determining the order of execution of operations (including which operations can execute simultaneously) is handled by the compiler, the processor does not need the scheduling hardware that the three methods described above require. Thus, VLIW CPUs offer more computing with less hardware complexity (but greater compiler complexity) than do most superscalar CPUs. This is also complementary to the idea that as many computations as possible should be done before the program is executed, at compile time.
671:
36:
480:(DSP) applications since the application execution and datasets were simple, well ordered and predictable, allowing designers to fully exploit the parallel execution advantages enabled by VLIW. In VLIW mode, the i860 could maintain floating-point performance in the range of 20-40 double-precision MFLOPS; a very high value for its time and for a processor running at 25-50Mhz.
1211:
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dependence relationships and resource requirements. It then schedules the instructions according to those constraints. In this process, independent instructions can be scheduled in parallel. Because VLIWs typically represent instructions scheduled in parallel with a longer instruction word that incorporates the individual instructions, this results in a much longer
764:, thus relieving the hardware from calculating this dependency information. Having this dependency information encoded in the instruction stream allows wider implementations to issue multiple non-dependent VLIW instructions in parallel per cycle, while narrower implementations would issue a smaller number of VLIW instructions per cycle.
321:. For example, if a first instruction's result is used as a second instruction's input, then they cannot execute at the same time and the second instruction cannot execute before the first. Modern out-of-order processors have increased the hardware resources which schedule instructions and determine interdependencies.
246:
methods to identify parallelism beyond basic blocks. Trace scheduling is such a method, and involves scheduling the most likely path of basic blocks first, inserting compensating code to deal with speculative motions, scheduling the second most likely trace, and so on, until the schedule is complete.
340:
In contrast, one VLIW instruction encodes multiple operations, at least one operation for each execution unit of a device. For example, if a VLIW device has five execution units, then a VLIW instruction for the device has five operation fields, each field specifying what operation should be done on
250:
Fisher's second innovation was the notion that the target CPU architecture should be designed to be a reasonable target for a compiler; that the compiler and the architecture for a VLIW processor must be codesigned. This was inspired partly by the difficulty Fisher observed at Yale of compiling for
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that operate independently. Contemporary VLIWs usually have four to eight main execution units. Compilers generate initial instruction sequences for the VLIW CPU in roughly the same manner as for traditional CPUs, generating a sequence of RISC-like instructions. The compiler analyzes this code for
569:
LX2 processor incorporates a technology named
Flexible Length Instruction eXtensions (FLIX) that allows multi-operation instructions. The Xtensa C/C++ compiler can freely intermix 32- or 64-bit FLIX instructions with the Xtensa processor's one-operation RISC instructions, which are 16 or 24 bits
487:
processor family. They found that the CPU could be greatly simplified by removing the complex dispatch logic from the CPU and placing it in the compiler. Compilers of the day were far more complex than those of the 1980s, so the added complexity in the compiler was considered to be a small cost.
400:
the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch. If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative
364:
CPUs use hardware to decide which operations can run in parallel at runtime, while VLIW CPUs use software (the compiler) to decide which operations can run in parallel in advance. Because the complexity of instruction scheduling is moved into the compiler, complexity of hardware can be reduced
288:
Multiflow was too early to catch the following wave, when chip architectures began to allow multiple-issue CPUs. The major semiconductor companies recognized the value of
Multiflow technology in this context, so the compiler and architecture were subsequently licensed to most of these firms.
593:
appear as the only examples of a widely used VLIW CPU architectures. However, EPIC architecture is sometimes distinguished from a pure VLIW architecture, since EPIC advocates full instruction predication, rotating register files, and a very long instruction word that can encode non-parallel
723:
When silicon technology allowed for wider implementations (with more execution units) to be built, the compiled programs for the earlier generation would not run on the wider implementations, as the encoding of binary instructions depended on the number of execution units of the machine.
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architecture (among others) solved the backward-compatibility problem with a more general mechanism. Within each of the multiple-opcode instructions, a bit field is allocated to denote dependency on the prior VLIW instruction within the program instruction stream. These bits are set at
468:
In the early 1990s, Intel introduced the i860 RISC microprocessor. This simple chip had two modes of operation: a scalar mode and a VLIW mode. In the VLIW mode, the processor always fetched two instructions and assumed that one was an integer instruction and the other floating-point.
259:(CISC) architecture that separated instruction initiation from the instructions that saved the result, needing very complex scheduling algorithms. Fisher developed a set of principles characterizing a proper VLIW design, such as self-draining pipelines, wide multi-port
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wide. By packing multiple operations into a wide 32- or 64-bit instruction word and allowing these multi-operation instructions to intermix with shorter RISC instructions, FLIX allows SoC designers to realize VLIW's performance advantages while eliminating the
301:
scalar architecture) may use processor resources inefficiently, yielding potential poor performance. The performance can be improved by executing different substeps of sequential instructions simultaneously (termed
336:
In superscalar designs, the number of execution units is invisible to the instruction set. Each instruction encodes one operation only. For most superscalar designs, the instruction width is 32 bits or fewer.
178:
In contrast, the VLIW method depends on the programs providing all the decisions regarding which instructions to execute simultaneously and how to resolve conflicts. As a practical matter, this means that the
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based on his
Sixties work on military-oriented M-9 and M-10 computers. His ideas were later developed and published as a part of a textbook two years before Fisher's seminal paper, but because of the
781:
Since the number of transistors on a chip has grown, the perceived disadvantages of the VLIW have diminished in importance. VLIW architectures are growing in popularity, especially in the
155:(CPUs) mostly allow programs to specify instructions to execute in sequence only. VLIW is intended to allow higher performance without the complexity inherent in some other designs.
744:
architecture. This mechanism was advertised to basically recompile, optimize, and translate x86 opcodes at runtime into the CPU's internal machine code. Thus, the
Transmeta chip is
175:). These methods all complicate hardware (larger circuits, higher cost and energy use) because the processor must make all of the decisions internally for these methods to work.
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158:
The traditional means to improve performance in processors include dividing instructions into substeps so the instructions can be executed partly at the same time (termed
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which branch will be taken even before the calculation is complete, so that they can load the instructions for the branch, or (in some architectures) even start to
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that corresponding execution unit. To accommodate these operation fields, VLIW instructions are usually at least 64 bits wide, and far wider on some architectures.
464:, their first 64-bit microprocessor, and the first processor to implement VLIW on one chip. This processor could operate in both simple RISC mode and VLIW mode:
285:, packaged in cabinets, a technology obsoleted as it grew more cost-effective to integrate all of the components of a processor (excluding memory) on one chip.
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of early VLIW architectures. The
Infineon Carmel DSP is another VLIW processor core intended for SoC. It uses a similar code density improvement method called
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instructions. This occurs when there are dependencies in the code and the instruction pipelines must be allowed to drain before later operations can proceed.
281:, shipping their first machines in 1987. Multiflow's VLIW could issue 28 operations in parallel per instruction. The TRACE system was implemented in a mix of
348:(SHARC). In one cycle, it does a floating-point multiply, a floating-point add, and two autoincrement loads. All of this fits in one 48-bit instruction:
243:
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These three methods all raise hardware complexity. Before executing any operations in parallel, the processor must verify that the instructions have no
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architectures. Further improvement can be achieved by executing instructions in an order different from that in which they occur in a program, termed
220:
457:, founder of Cydrome, also joined HP after Cydrome failed. These two would lead computer architecture research at Hewlett-Packard during the 1990s.
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The first VLIW compiler was described in a Ph.D. thesis by John Ellis, supervised by Fisher. The compiler was named
Bulldog, after Yale's mascot.
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345:
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927:
Kartsev, Mikhail (1970). "Вопросы построения многопроцессорных вычислительных систем" [Building the multiprocessor computer systems].
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393:(RISC) designs has been eroded. VLIW lacks this logic, and thus lacks its energy use, possible design defects, and other negative aspects.
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1803:
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183:(software used to create the final programs) becomes more complex, but the hardware is simpler than in many other means of parallelism.
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Fisher's innovations involved developing a compiler that could target horizontal microcode from programs written in an ordinary
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219:. Before Fisher the theoretical aspects of what would be later called VLIW were developed by the Soviet computer scientist
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from Improv
Systems, the HiveFlex series from Silicon Hive, and the MPPA Manycore family by Kalray. The Texas Instruments
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family. These contemporary VLIW CPUs are mainly successful as embedded media processors for consumer electronic devices.
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A similar problem occurs when the result of a parallelizable instruction is used as input for a branch. Most modern CPUs
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442:(ECL) integrated circuits in the same timeframe (late 1980s). This company, like Multiflow, failed after a few years.
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1104:"EEMBC Publishes Benchmark Scores for Infineon Technologies' Carmel - DSP Core and TriCore - TC11IB Microcontroller"
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by STMicroelectronics based on the Lx architecture (designed in Josh Fisher's HP lab by Paolo
Faraboschi), the
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In contrast, VLIW executes operations in parallel, based on a fixed schedule, determined when programs are
140:
162:), dispatching individual instructions to be executed independently, in different parts of the processor (
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The Neo by REX Computing is a processor consisting of a 2D mesh of VLIW cores aimed at power efficiency.
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277:, along with cofounders John O'Donnell and John Ruttenberg. Multiflow produced the TRACE series of VLIW
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medium-scale integration (MSI), large-scale integration (LSI), and very large-scale integration (VLSI)
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and instruction-level parallelism in software was well established in the practice of developing
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In the 1990s, Hewlett-Packard researched this problem as a side effect of ongoing work on their
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and because
Kartsev's work was mostly military-related it remained largely unknown in the West.
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that occurs when one or more execution unit(s) have no useful work to do and thus must execute
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Along with the above systems, during the same time (1989–1990), Intel implemented VLIW in the
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have since moved to RISC architectures to improve performance on non-graphics workloads.
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147:(ILP). A VLIW processor allows programs to explicitly specify instructions to execute in
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addressed this issue by including a binary-to-binary software compiler layer (termed
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376:. If the CPU guesses wrong, all of these instructions and their context need to be
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machine, it would be necessary to find parallelism beyond that generally within a
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A similar VLIW architecture, with a parallelizing compiler directed toward LISP.
649:) and its successors are Russian 512-bit wide VLIW microprocessors developed by
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Proceedings of the 10th annual international symposium on
Computer architecture
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Since the earliest days of computer architecture, some CPUs have added several
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as a compiling method for VLIW was developed when he was a graduate student at
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market, where it is possible to customize a processor for an application in a
594:
instruction groups. VLIWs also gained significant consumer penetration in the
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2939:
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1895:
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A processor that executes every instruction one after the other (i.e., a non-
260:
1798:
1026:"An Introduction To Very-Long Instruction Word (VLIW) Computer Architecture"
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3087:
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2413:
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520:
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169:), and even executing instructions in an order different from the program (
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885:
638:
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306:), or even executing multiple instructions entirely simultaneously as in
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892:. International Symposium on Computer Architecture. New York, NY, USA:
775:
768:
695: in this section. Unsourced material may be challenged and removed.
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VLIW features have also been added to configurable processor cores for
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532:
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420:
235:
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888:(1983). "Very Long Instruction Word architectures and the ELI-512".
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415:) can be combined with the VLIW architecture such as in the Fujitsu
35:
2926:
1745:
1124:
816:
540:
325:
267:. These principles made it easier for compilers to emit fast code.
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1180:
Book on the history of Multiflow Computer, VLIW pioneering company
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1202:
FR500 VLIW-architecture High-performance Embedded Microprocessor
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ISCA "Best Papers" Retrospective On Paper That Introduced VLIWs
998:"Control Data 6400/6500/6600 Computer Systems Reference Manual"
599:
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544:
497:
352:
f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3), f4 = pm(i8, m9);
627:
In December 2015, the first shipment of PCs based on VLIW CPU
2208:
1740:
1710:
1053:
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family, to look more like a VLIW, in contrast to the earlier
1207:
Historical background for EPIC instruction set architectures
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2220:
2140:
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a VLIW processor, effectively decoupled from the x86 CISC
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This has led to increasingly complex instruction-dispatch
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603:
27:
Processor design that offloads complexity to the compiler
234:. He realized that to get good performance and target a
1196:
819: – American computer processor chip design company
929:
Radioelectronic Matters, Electronic Computing Technics
438:
was a company producing VLIW numeric processors using
1146:"The Tiny Chip That Could Disrupt Exascale Computing"
344:
For example, the following is an instruction for the
273:
Fisher left Yale in 1984 to found a startup company,
767:
Another perceived deficiency of VLIW designs is the
445:
One of the licensees of the Multiflow technology is
807: – Line of Soviet and Russian computer systems
60:. Unsourced material may be challenged and removed.
831: – Execution model used in parallel computing
491:VLIW CPUs are usually made of multiple RISC-like
3162:
861:"Very Long Instruction Word (VLIW) Architecture"
203:in the early 1980s. His original development of
517:Super Harvard Architecture Single-Chip Computer
507:Examples of contemporary VLIW CPUs include the
382:and the correct ones loaded, which takes time.
346:Super Harvard Architecture Single-Chip Computer
191:The concept of VLIW architecture, and the term
944:Вычислительные системы и синхронная арифметика
813: – Family of 64-bit Intel microprocessors
1233:
1212:DIS: an Architecture for fast LISP execution.
948:Compuring systems and synchronous arythmetics
581:Outside embedded processing markets, Intel's
504:) to specify what executes on a given cycle.
473:The i860's VLIW mode was used extensively in
2238:Computer performance by orders of magnitude
941:
396:In a VLIW, the compiler uses heuristics or
211:. Before VLIW, the notion of prescheduling
1247:
1240:
1226:
1152:. Stackhouse Publishing Inc. 12 March 2015
950:] (in Russian). Moscow: Radio i Svyaz.
1042:
983:Bulldog: A Compiler for VLIW Architecture
942:Kartsev, Mikhail; Brik, Vladimir (1981).
901:
837: – Type of computer processor design
799:Explicitly parallel instruction computing
711:Learn how and when to remove this message
660:
587:explicitly parallel instruction computing
120:Learn how and when to remove this message
1031:. Philips Semiconductors. Archived from
565:(SoC) designs. For example, Tensilica's
954:
926:
515:(formerly Philips Semiconductors), the
401:results to preserve program semantics.
14:
3163:
962:"ACM 1985 Doctoral Dissertation Award"
920:
884:
387:logic that attempts to guess correctly
1221:
1096:
1020:
1018:
878:
389:, and the simplicity of the original
3171:Very long instruction word computing
2209:Floating-point operations per second
1117:
855:
853:
851:
829:Single instruction, multiple threads
801: – Instruction set architecture
693:adding citations to reliable sources
664:
624:(GPUs) is a VLIW microarchitecture.
58:adding citations to reliable sources
29:
966:Association for Computing Machinery
894:Association for Computing Machinery
825: – Type of parallel processing
651:Moscow Center of SPARC Technologies
519:(SHARC) DSP by Analog Devices, the
419:microprocessor, further increasing
24:
1015:
576:configurable long instruction word
430:
25:
3202:
1168:
1081:. Silicon Hive BV. Archived from
848:
823:Single instruction, multiple data
453:joined after Multiflow's demise.
391:reduced instruction set computing
257:complex instruction set computing
3135:Semiconductor device fabrication
835:Transport triggered architecture
669:
34:
3110:History of general-purpose CPUs
1337:Nondeterministic Turing machine
1138:
680:needs additional citations for
45:needs additional citations for
1290:Deterministic finite automaton
1067:
990:
935:
13:
1:
3186:Instruction set architectures
2081:Simultaneous and heterogenous
841:
292:
145:instruction-level parallelism
143:that are designed to exploit
141:instruction set architectures
2765:Integrated memory controller
2747:Translation lookaside buffer
1946:Memory dependence prediction
1389:Random-access stored program
1342:Probabilistic Turing machine
1197:VLIW and Embedded Processing
1050:"Pixelworks | BSP15/16"
1000:. 1969-02-21. Archived from
398:profile information to guess
69:"Very long instruction word"
7:
2221:Synaptic updates per second
1175:Paper That Introduced VLIWs
792:
360:(ALUs) to run in parallel.
10:
3207:
2625:Heterogeneous architecture
1547:Orthogonal instruction set
1317:Alternating Turing machine
1305:Quantum cellular automaton
598:(GPU) market, though both
407:cores (designed for large
374:compute them speculatively
186:
133:Very long instruction word
3176:Digital signal processing
3115:Microprocessor chronology
3102:
3078:Dynamic frequency scaling
3051:
2987:
2925:
2879:
2831:
2786:
2706:
2633:
2602:
2507:
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2392:
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2233:Cache performance metrics
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1967:
1958:
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931:(in Russian) (5–6): 3–19.
896:(ACM). pp. 140–150.
653:(MCST) and fabricated by
646:
622:graphics processing units
550:line has evolved, in its
331:
199:in his research group at
3130:Hardware security module
2473:Digital signal processor
2450:Graphics processing unit
2262:Graphics processing unit
596:graphics processing unit
478:digital signal processor
153:central processing units
3083:Dynamic voltage scaling
2866:Memory address register
2760:Branch target predictor
2724:Address generation unit
2467:Physics processing unit
2256:Central processing unit
2215:Transactions per second
2203:Instructions per second
2126:Array processing (SIMT)
1270:Stored-program computer
1075:"silicon hive Products"
151:, whereas conventional
3181:Instruction processing
2889:Hardwired control unit
2771:Memory management unit
2736:Memory management unit
2485:Secure cryptoprocessor
2479:Tensor Processing Unit
2461:Vision processing unit
2195:Cycles per instruction
2189:Instructions per cycle
2136:Associative processing
1827:Instruction pipelining
1249:Processor technologies
740:implementation of the
661:Backward compatibility
620:microarchitecture for
614:Advanced Micro Devices
471:
409:one-dimensional arrays
358:arithmetic logic units
312:out-of-order execution
255:' FPS164, which had a
253:Floating Point Systems
172:out-of-order execution
2972:Sum-addressed decoder
2718:Arithmetic logic unit
1845:Classic RISC pipeline
1799:Epiphany architecture
1646:Motorola 68000 series
981:For his dissertation
968:(ACM). Archived from
903:10.1145/800046.801649
466:
440:emitter-coupled logic
3093:Performance per watt
2671:replacement policies
2337:Package on a package
2227:Performance per watt
2131:Pipelined processing
1901:Tomasulo's algorithm
1706:Clipper architecture
1562:Application-specific
1275:Finite-state machine
689:improve this article
631:was made in Russia.
531:, the BSP15/16 from
511:media processors by
265:memory architectures
242:. He also developed
232:programming language
217:horizontal microcode
54:improve this article
3125:Digital electronics
2778:Instruction decoder
2730:Floating-point unit
2384:Soft microprocessor
2331:System in a package
1906:Reservation station
1436:Transport-triggered
251:architectures like
209:New York University
195:, were invented by
3191:Parallel computing
2997:Integrated circuit
2841:Processor register
2495:Baseband processor
1840:Operand forwarding
1300:Cellular automaton
1190:2012-03-10 at the
752:that it executes.
279:minisupercomputers
3158:
3157:
3047:
3046:
2666:Instruction cache
2656:Scratchpad memory
2503:
2502:
2490:Network processor
2419:Network on a chip
2374:Ultra-low-voltage
2325:Multi-chip module
2168:
2167:
1954:
1953:
1941:Branch prediction
1918:Register renaming
1812:
1811:
1794:VISC architecture
1616:Quantum computing
1611:VISC architecture
1493:Secondary storage
1409:Microarchitecture
1369:Register machines
1150:The Next Platform
886:Fisher, Joseph A.
805:Elbrus (computer)
721:
720:
713:
319:interdependencies
244:region scheduling
130:
129:
122:
104:
16:(Redirected from
3198:
3120:Processor design
3012:Power management
2894:Instruction unit
2755:Branch predictor
2704:
2703:
2402:System on a chip
2344:
2343:
2184:Transistor count
2108:Flynn's taxonomy
1965:
1964:
1823:
1822:
1626:Addressing modes
1537:
1536:
1483:Memory hierarchy
1347:Hypercomputation
1265:Abstract machine
1242:
1235:
1228:
1219:
1218:
1162:
1161:
1159:
1157:
1142:
1136:
1135:
1133:
1132:
1121:
1115:
1114:
1112:
1111:
1100:
1094:
1093:
1091:
1090:
1071:
1065:
1064:
1062:
1061:
1052:. Archived from
1046:
1040:
1039:
1037:
1030:
1022:
1013:
1012:
1010:
1009:
994:
988:
987:
978:
977:
958:
952:
951:
939:
933:
932:
924:
918:
917:
905:
882:
876:
875:
873:
872:
857:
787:system-on-a-chip
716:
709:
705:
702:
696:
673:
665:
648:
610:ATI Technologies
563:system-on-a-chip
405:Vector processor
353:
205:trace scheduling
125:
118:
114:
111:
105:
103:
62:
38:
30:
21:
3206:
3205:
3201:
3200:
3199:
3197:
3196:
3195:
3161:
3160:
3159:
3154:
3140:Tick–tock model
3098:
3054:
3043:
2983:
2967:Address decoder
2921:
2875:
2871:Program counter
2846:Status register
2827:
2782:
2742:Load–store unit
2709:
2702:
2629:
2598:
2499:
2456:Image processor
2431:
2424:
2394:
2388:
2364:Microcontroller
2354:Embedded system
2342:
2242:
2175:
2164:
2102:
2052:
1950:
1927:
1911:Re-order buffer
1882:
1863:Data dependency
1849:
1808:
1638:
1632:
1531:
1530:Instruction set
1524:
1510:Multiprocessing
1478:Cache hierarchy
1471:Register/memory
1395:
1295:Queue automaton
1251:
1246:
1192:Wayback Machine
1171:
1166:
1165:
1155:
1153:
1144:
1143:
1139:
1130:
1128:
1123:
1122:
1118:
1109:
1107:
1102:
1101:
1097:
1088:
1086:
1073:
1072:
1068:
1059:
1057:
1048:
1047:
1043:
1035:
1028:
1024:
1023:
1016:
1007:
1005:
996:
995:
991:
975:
973:
960:
959:
955:
940:
936:
925:
921:
914:
883:
879:
870:
868:
859:
858:
849:
844:
795:
783:embedded system
750:instruction set
717:
706:
700:
697:
686:
674:
663:
539:from CEVA, the
493:execution units
447:Hewlett-Packard
433:
431:Implementations
411:of data called
365:substantially.
351:
334:
295:
221:Mikhail Kartsev
213:execution units
201:Yale University
189:
126:
115:
109:
106:
63:
61:
51:
39:
28:
23:
22:
15:
12:
11:
5:
3204:
3194:
3193:
3188:
3183:
3178:
3173:
3156:
3155:
3153:
3152:
3147:
3145:Pin grid array
3142:
3137:
3132:
3127:
3122:
3117:
3112:
3106:
3104:
3100:
3099:
3097:
3096:
3090:
3085:
3080:
3075:
3070:
3065:
3059:
3057:
3049:
3048:
3045:
3044:
3042:
3041:
3036:
3031:
3026:
3021:
3016:
3015:
3014:
3009:
3004:
2993:
2991:
2985:
2984:
2982:
2981:
2979:Barrel shifter
2976:
2975:
2974:
2969:
2962:Binary decoder
2959:
2958:
2957:
2947:
2942:
2937:
2931:
2929:
2923:
2922:
2920:
2919:
2914:
2906:
2901:
2896:
2891:
2885:
2883:
2877:
2876:
2874:
2873:
2868:
2863:
2858:
2853:
2851:Stack register
2848:
2843:
2837:
2835:
2829:
2828:
2826:
2825:
2824:
2823:
2818:
2808:
2803:
2798:
2792:
2790:
2784:
2783:
2781:
2780:
2775:
2774:
2773:
2762:
2757:
2752:
2751:
2750:
2744:
2733:
2727:
2721:
2714:
2712:
2701:
2700:
2695:
2690:
2685:
2680:
2679:
2678:
2673:
2668:
2663:
2658:
2653:
2643:
2637:
2635:
2631:
2630:
2628:
2627:
2622:
2617:
2612:
2606:
2604:
2600:
2599:
2597:
2596:
2595:
2594:
2584:
2579:
2574:
2569:
2564:
2559:
2554:
2549:
2544:
2539:
2534:
2529:
2524:
2519:
2513:
2511:
2505:
2504:
2501:
2500:
2498:
2497:
2492:
2487:
2482:
2476:
2470:
2464:
2458:
2453:
2447:
2445:AI accelerator
2442:
2436:
2434:
2426:
2425:
2423:
2422:
2416:
2411:
2408:Multiprocessor
2405:
2398:
2396:
2390:
2389:
2387:
2386:
2381:
2376:
2371:
2366:
2361:
2359:Microprocessor
2356:
2350:
2348:
2347:By application
2341:
2340:
2334:
2328:
2322:
2317:
2312:
2307:
2302:
2297:
2292:
2290:Tile processor
2287:
2282:
2277:
2272:
2271:
2270:
2259:
2252:
2250:
2244:
2243:
2241:
2240:
2235:
2230:
2224:
2218:
2212:
2206:
2200:
2199:
2198:
2186:
2180:
2178:
2170:
2169:
2166:
2165:
2163:
2162:
2161:
2160:
2150:
2145:
2144:
2143:
2138:
2133:
2128:
2118:
2112:
2110:
2104:
2103:
2101:
2100:
2095:
2090:
2085:
2084:
2083:
2078:
2076:Hyperthreading
2068:
2062:
2060:
2058:Multithreading
2054:
2053:
2051:
2050:
2045:
2040:
2039:
2038:
2028:
2027:
2026:
2021:
2011:
2010:
2009:
2004:
1994:
1989:
1988:
1987:
1982:
1971:
1969:
1962:
1956:
1955:
1952:
1951:
1949:
1948:
1943:
1937:
1935:
1929:
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1920:
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1908:
1898:
1892:
1890:
1884:
1883:
1881:
1880:
1875:
1870:
1865:
1859:
1857:
1851:
1850:
1848:
1847:
1842:
1837:
1835:Pipeline stall
1831:
1829:
1820:
1814:
1813:
1810:
1809:
1807:
1806:
1801:
1796:
1791:
1788:
1787:
1786:
1784:z/Architecture
1781:
1776:
1771:
1763:
1758:
1753:
1748:
1743:
1738:
1733:
1728:
1723:
1718:
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1554:
1549:
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1541:
1534:
1526:
1525:
1523:
1522:
1517:
1512:
1507:
1502:
1497:
1496:
1495:
1490:
1488:Virtual memory
1480:
1475:
1474:
1473:
1468:
1463:
1458:
1448:
1443:
1438:
1433:
1428:
1427:
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1394:
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1361:
1356:
1355:
1354:
1349:
1344:
1339:
1334:
1329:
1324:
1319:
1312:Turing machine
1309:
1308:
1307:
1302:
1297:
1292:
1287:
1282:
1272:
1267:
1261:
1259:
1253:
1252:
1245:
1244:
1237:
1230:
1222:
1216:
1215:
1209:
1204:
1199:
1194:
1182:
1177:
1170:
1169:External links
1167:
1164:
1163:
1137:
1116:
1095:
1066:
1041:
1038:on 2011-09-29.
1014:
989:
953:
934:
919:
912:
877:
846:
845:
843:
840:
839:
838:
832:
826:
820:
814:
808:
802:
794:
791:
719:
718:
677:
675:
668:
662:
659:
432:
429:
333:
330:
294:
291:
261:register files
188:
185:
128:
127:
42:
40:
33:
26:
9:
6:
4:
3:
2:
3203:
3192:
3189:
3187:
3184:
3182:
3179:
3177:
3174:
3172:
3169:
3168:
3166:
3151:
3148:
3146:
3143:
3141:
3138:
3136:
3133:
3131:
3128:
3126:
3123:
3121:
3118:
3116:
3113:
3111:
3108:
3107:
3105:
3101:
3094:
3091:
3089:
3086:
3084:
3081:
3079:
3076:
3074:
3071:
3069:
3066:
3064:
3061:
3060:
3058:
3056:
3050:
3040:
3037:
3035:
3032:
3030:
3027:
3025:
3022:
3020:
3017:
3013:
3010:
3008:
3005:
3003:
3000:
2999:
2998:
2995:
2994:
2992:
2990:
2986:
2980:
2977:
2973:
2970:
2968:
2965:
2964:
2963:
2960:
2956:
2953:
2952:
2951:
2948:
2946:
2943:
2941:
2940:Demultiplexer
2938:
2936:
2933:
2932:
2930:
2928:
2924:
2918:
2915:
2913:
2910:
2907:
2905:
2902:
2900:
2897:
2895:
2892:
2890:
2887:
2886:
2884:
2882:
2878:
2872:
2869:
2867:
2864:
2862:
2861:Memory buffer
2859:
2857:
2856:Register file
2854:
2852:
2849:
2847:
2844:
2842:
2839:
2838:
2836:
2834:
2830:
2822:
2819:
2817:
2814:
2813:
2812:
2809:
2807:
2804:
2802:
2799:
2797:
2796:Combinational
2794:
2793:
2791:
2789:
2785:
2779:
2776:
2772:
2769:
2768:
2766:
2763:
2761:
2758:
2756:
2753:
2748:
2745:
2743:
2740:
2739:
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2734:
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2728:
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2711:
2705:
2699:
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2681:
2677:
2674:
2672:
2669:
2667:
2664:
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2659:
2657:
2654:
2652:
2649:
2648:
2647:
2644:
2642:
2639:
2638:
2636:
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2623:
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2618:
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2613:
2611:
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2607:
2605:
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2589:
2588:
2585:
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2580:
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2563:
2560:
2558:
2555:
2553:
2550:
2548:
2545:
2543:
2540:
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2535:
2533:
2530:
2528:
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2523:
2520:
2518:
2515:
2514:
2512:
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2506:
2496:
2493:
2491:
2488:
2486:
2483:
2480:
2477:
2474:
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2468:
2465:
2462:
2459:
2457:
2454:
2451:
2448:
2446:
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2427:
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2417:
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2400:
2399:
2397:
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2355:
2352:
2351:
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2338:
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2329:
2326:
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2318:
2316:
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2308:
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2257:
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2222:
2219:
2216:
2213:
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2201:
2196:
2193:
2192:
2190:
2187:
2185:
2182:
2181:
2179:
2177:
2171:
2159:
2156:
2155:
2154:
2151:
2149:
2146:
2142:
2139:
2137:
2134:
2132:
2129:
2127:
2124:
2123:
2122:
2119:
2117:
2114:
2113:
2111:
2109:
2105:
2099:
2096:
2094:
2091:
2089:
2086:
2082:
2079:
2077:
2074:
2073:
2072:
2069:
2067:
2064:
2063:
2061:
2059:
2055:
2049:
2046:
2044:
2041:
2037:
2034:
2033:
2032:
2029:
2025:
2022:
2020:
2017:
2016:
2015:
2012:
2008:
2005:
2003:
2000:
1999:
1998:
1995:
1993:
1990:
1986:
1983:
1981:
1978:
1977:
1976:
1973:
1972:
1970:
1966:
1963:
1961:
1957:
1947:
1944:
1942:
1939:
1938:
1936:
1934:
1930:
1924:
1921:
1919:
1916:
1912:
1909:
1907:
1904:
1903:
1902:
1899:
1897:
1896:Scoreboarding
1894:
1893:
1891:
1889:
1885:
1879:
1878:False sharing
1876:
1874:
1871:
1869:
1866:
1864:
1861:
1860:
1858:
1856:
1852:
1846:
1843:
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1824:
1821:
1819:
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1697:
1695:
1692:
1690:
1687:
1686:
1684:
1682:
1679:
1677:
1674:
1672:
1671:Stanford MIPS
1669:
1667:
1664:
1662:
1659:
1657:
1654:
1652:
1649:
1647:
1644:
1643:
1641:
1635:
1627:
1624:
1623:
1622:
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1617:
1614:
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1609:
1607:
1604:
1602:
1599:
1597:
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1582:
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1580:
1577:
1573:
1570:
1569:
1568:
1565:
1563:
1560:
1558:
1555:
1553:
1550:
1548:
1545:
1544:
1542:
1538:
1535:
1533:
1532:architectures
1527:
1521:
1518:
1516:
1513:
1511:
1508:
1506:
1503:
1501:
1500:Heterogeneous
1498:
1494:
1491:
1489:
1486:
1485:
1484:
1481:
1479:
1476:
1472:
1469:
1467:
1464:
1462:
1459:
1457:
1454:
1453:
1452:
1451:Memory access
1449:
1447:
1444:
1442:
1439:
1437:
1434:
1432:
1429:
1425:
1422:
1421:
1420:
1417:
1415:
1412:
1410:
1407:
1406:
1404:
1402:
1398:
1390:
1387:
1385:
1384:Random-access
1382:
1380:
1377:
1375:
1372:
1371:
1370:
1367:
1365:
1364:Stack machine
1362:
1360:
1357:
1353:
1350:
1348:
1345:
1343:
1340:
1338:
1335:
1333:
1330:
1328:
1325:
1323:
1320:
1318:
1315:
1314:
1313:
1310:
1306:
1303:
1301:
1298:
1296:
1293:
1291:
1288:
1286:
1283:
1281:
1280:with datapath
1278:
1277:
1276:
1273:
1271:
1268:
1266:
1263:
1262:
1260:
1258:
1254:
1250:
1243:
1238:
1236:
1231:
1229:
1224:
1223:
1220:
1213:
1210:
1208:
1205:
1203:
1200:
1198:
1195:
1193:
1189:
1186:
1183:
1181:
1178:
1176:
1173:
1172:
1151:
1147:
1141:
1126:
1120:
1105:
1099:
1085:on 2012-01-28
1084:
1080:
1076:
1070:
1056:on 1996-12-24
1055:
1051:
1045:
1034:
1027:
1021:
1019:
1004:on 2014-01-02
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972:on 2008-04-02
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913:0-89791-101-6
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865:GeeksforGeeks
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678:This section
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65:Find sources:
59:
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43:This article
41:
37:
32:
31:
19:
3150:Chip carrier
3088:Clock gating
3007:Mixed-signal
2904:Write buffer
2881:Control unit
2693:Clock signal
2432:accelerators
2414:Cypress PSoC
2071:Simultaneous
1888:Out-of-order
1578:
1520:Neuromorphic
1401:Architecture
1359:Belt machine
1352:Zeno machine
1285:Hierarchical
1154:. Retrieved
1149:
1140:
1129:. Retrieved
1119:
1108:. Retrieved
1098:
1087:. Retrieved
1083:the original
1079:Silicon Hive
1078:
1069:
1058:. Retrieved
1054:the original
1044:
1033:the original
1006:. Retrieved
1002:the original
992:
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974:. Retrieved
970:the original
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869:. Retrieved
867:. 2020-12-01
864:
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773:No Operation
772:
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762:compile time
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707:
698:
687:Please help
682:verification
679:
647:Эльбрус 2000
636:
633:
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612:' (ATI) and
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521:ST200 family
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52:Please help
47:verification
44:
2935:Multiplexer
2899:Data buffer
2610:Single-core
2582:bit slicing
2440:Coprocessor
2295:Coprocessor
2176:performance
2098:Cooperative
2088:Speculative
2048:Distributed
2007:Superscalar
1992:Instruction
1960:Parallelism
1933:Speculative
1765:System/3x0
1637:Instruction
1414:Von Neumann
1327:Post–Turing
1106:. eembc.org
736:) in their
639:Elbrus 2000
591:Elbrus 2000
589:(EPIC) and
451:Josh Fisher
362:Superscalar
308:superscalar
240:basic block
197:Josh Fisher
165:superscalar
3165:Categories
3055:management
2950:Multiplier
2811:Logic gate
2801:Sequential
2708:Functional
2688:Clock rate
2661:Data cache
2634:Components
2615:Multi-core
2603:Core count
2093:Preemptive
1997:Pipelining
1980:Bit-serial
1923:Wide-issue
1868:Structural
1790:Tilera ISA
1756:MicroBlaze
1726:ETRAX CRIS
1621:Comparison
1466:Load–store
1446:Endianness
1131:2016-07-28
1110:2016-07-28
1089:2012-01-28
1060:2016-07-28
1008:2013-11-07
976:2007-10-15
871:2022-10-14
842:References
769:code bloat
746:internally
572:code bloat
537:CEVA-X DSP
533:Pixelworks
462:Intel i860
421:throughput
304:pipelining
293:Motivation
236:wide-issue
160:pipelining
110:March 2014
80:newspapers
2989:Circuitry
2909:Microcode
2833:Registers
2676:coherence
2651:CPU cache
2509:Word size
2174:Processor
1818:Execution
1721:DEC Alpha
1699:Power ISA
1515:Cognitive
1322:Universal
1127:. tass.ru
728:Transmeta
701:June 2016
629:Elbrus-4s
618:TeraScale
502:very long
299:pipelined
275:Multiflow
2927:Datapath
2620:Manycore
2592:variable
2430:Hardware
2066:Temporal
1746:OpenRISC
1441:Cellular
1431:Dataflow
1424:modified
1188:Archived
1156:26 April
817:Movidius
793:See also
755:Intel's
616:' (AMD)
578:(CLIW).
541:Jazz DSP
509:TriMedia
500:(termed
475:embedded
449:, which
326:compiled
181:compiler
149:parallel
3103:Related
3034:Quantum
3024:Digital
3019:Boolean
2917:Counter
2816:Quantum
2577:512-bit
2572:256-bit
2567:128-bit
2410:(MPSoC)
2395:on chip
2393:Systems
2211:(FLOPS)
2024:Process
1873:Control
1855:Hazards
1741:Itanium
1736:Unicore
1694:PowerPC
1419:Harvard
1379:Pointer
1374:Counter
1332:Quantum
811:Itanium
757:Itanium
643:Russian
583:Itanium
529:Fujitsu
485:PA-RISC
455:Bob Rau
436:Cydrome
413:vectors
379:flushed
187:History
94:scholar
3039:Switch
3029:Analog
2767:(IMC)
2738:(MMU)
2587:others
2562:64-bit
2557:48-bit
2552:32-bit
2547:24-bit
2542:16-bit
2537:15-bit
2532:12-bit
2369:Mobile
2285:Stream
2280:Barrel
2275:Vector
2264:(GPU)
2223:(SUPS)
2191:(IPC)
2043:Memory
2036:Vector
2019:Thread
2002:Scalar
1804:Others
1751:RISC-V
1716:SuperH
1685:Power
1681:MIPS-X
1656:PDP-11
1505:Fabric
1257:Models
1125:"ТАСС"
910:
738:Crusoe
600:Nvidia
585:IA-64
567:Xtensa
545:TMS320
535:, the
498:opcode
332:Design
263:, and
96:
89:
82:
75:
67:
3095:(PPW)
3053:Power
2945:Adder
2821:Array
2788:Logic
2749:(TLB)
2732:(FPU)
2726:(AGU)
2720:(ALU)
2710:units
2646:Cache
2527:8-bit
2522:4-bit
2517:1-bit
2481:(TPU)
2475:(DSP)
2469:(PPU)
2463:(VPU)
2452:(GPU)
2421:(NoC)
2404:(SoC)
2339:(PoP)
2333:(SiP)
2327:(MCM)
2268:GPGPU
2258:(CPU)
2248:Types
2229:(PPW)
2217:(TPS)
2205:(IPS)
2197:(CPI)
1968:Level
1779:S/390
1774:S/370
1769:S/360
1711:SPARC
1689:POWER
1572:TRIPS
1540:Types
1036:(PDF)
1029:(PDF)
946:[
556:C5000
552:C6000
527:from
425:speed
370:guess
101:JSTOR
87:books
3073:ACPI
2806:Glue
2698:FIFO
2641:Core
2379:ASIP
2320:CPLD
2315:FPOA
2310:FPGA
2305:ASIC
2158:SPMD
2153:MIMD
2148:MISD
2141:SWAR
2121:SIMD
2116:SISD
2031:Data
2014:Task
1985:Word
1731:M32R
1676:MIPS
1639:sets
1606:ZISC
1601:NISC
1596:OISC
1591:MISC
1584:EPIC
1579:VLIW
1567:EDGE
1557:RISC
1552:CISC
1461:HUMA
1456:NUMA
1158:2021
908:ISBN
655:TSMC
637:The
602:and
525:FR-V
423:and
417:FR-V
193:VLIW
137:VLIW
73:news
18:VLIW
3068:APM
3063:PMU
2955:CPU
2912:ROM
2683:Bus
2300:PAL
1975:Bit
1761:LMC
1666:ARM
1661:x86
1651:VAX
898:doi
776:NOP
742:x86
691:by
604:AMD
548:DSP
513:NXP
56:by
3167::
3002:3D
1148:.
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1017:^
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