33:
965:
this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex.
1516:
2337:
2349:
972:. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditions
1324:
Data is clocked on rising and falling edges for 1000 Mbit/s, and on rising edges only for 10/100 Mbit/s. The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the
1320:
The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication
655:
The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered
520:
Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already
1332:
clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay,
991:
Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the
National DP83848 which supplies the decoded
964:
There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so
1086:). The interface operates at speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s.
516:
The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate
1149:
There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or 100 Mbit/s operation, the TXCLK is
671:
The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists.
742:
The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.
1150:
supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses a single clock signal recovered from the incoming data.
114:
in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include:
659:
The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost.
758:
Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context of
1764:
767:, multiport switches or repeaters, and PC motherboard chipsets. Four things were changed compared to the MII standard to achieve this. These changes mean that RMII uses about half the number of signals compared to MII.
528:
frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an
771:
The two clocks TXCLK and RXCLK are replaced by a single clock. This clock is an input to the PHY rather than an output, which allows the clock signal to be shared among all PHYs in a multiport device, such as a
663:
Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a
1479:. Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (
675:
In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.
1771:
930:
clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is sampled on the rising edge only (i.e. it is
84:, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission medium.
1820:"2.5 V ± 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits, JESD8-5A.01"
1257:
The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the
Extended Status register.
808:
Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY, or may be driven from the PHY to the MAC
264:
Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode.
1499:
The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a 5 Gbit/s interface. QSGMII, like SGMII, uses
2123:
968:
The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the
1881:
1750:
919:
This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.
17:
1483:
may be used alternatively). 10/100 Mbit/s
Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.
517:
without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.
1491:
The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to 2.5 Gbit/s.
1912:
1503:(LVDS) for the TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections.
1089:
The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.
871:
Carrier Sense (CRS) and RX_Data Valid (RX_DV) multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles.
1328:
The transmit clock signal is always provided by the MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line.
1837:"High Speed Transceiver Logic (HSTL). A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, JESD8-6"
521:
started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.
1901:
1620:
205:(MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using
2317:
1875:
1733:
1562:. XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz
1692:
87:
The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip on the same
2312:
92:
1652:
1467:
It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from
775:
The clock frequency is doubled from 25 MHz to 50 MHz, while the data paths are narrowed from 4 bits to 2 bits.
1944:
1500:
1795:
106:
standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a
1527:
2163:
1890:
1062:
resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under
32:
209:, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.
1449:
684:
202:
1558:(PCB). It is now typically used for on-chip connections. PCB connections are now mostly accomplished with
2257:
2252:
1609:
1603:
2302:
2100:
2090:
1917:
1614:
77:
2353:
2292:
2214:
1922:
1579:
530:
2380:
2276:
2023:
1987:
969:
107:
1819:
2158:
1937:
2385:
2038:
1555:
1079:
656:(i.e. when the medium is silent), the PHY must present a free-running clock as a substitute.
88:
61:
1836:
948:
mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in
2234:
2209:
2002:
1040:
752:
8:
2229:
2219:
2199:
2194:
2178:
2085:
1997:
1992:
1551:
402:
267:
The MII Status Word is the most useful datum, since it may be used to detect whether an
2095:
1957:
1329:
1059:
65:
1905:
1870:
980:
cannot be detected, and it is difficult or impossible to support shared media such as
2375:
2341:
2069:
1930:
1744:
1688:
1044:
916:
The receiver signals are referenced to the REF_CLK, same as the transmitter signals.
1460:
The serial gigabit media-independent interface (SGMII) is a variant of MII used for
2204:
2007:
1982:
1972:
1680:
1563:
1461:
952:
mode. The receiver (PHY or MAC) samples the input signals only every ten cycles in
340:
316:
37:
76:
means that different types of PHY devices for connecting to different media (i.e.
2271:
2028:
1865:
1721:
1707:
1684:
1632:
1593:
1333:
obviating the need for the PCB designer to add delay; this is known as RGMII-ID.
1325:
falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s.
760:
367:
206:
2266:
2224:
2043:
1597:
1480:
99:
2369:
1977:
1876:
hp.com – RGMIIv2_0_final_hp.pdf RGMII 2002-04-01 Version 2.0
1321:
signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27.
934:
731:
53:
1592:
recommendation that uses the term MII to refer to the interface between the
1802:
1390:
1173:
1078:
The gigabit media-independent interface (GMII) is an interface between the
268:
2244:
2048:
1143:
Transmitter error (used to intentionally corrupt a packet, if necessary)
1001:
81:
69:
1546:
10 gigabit media-independent interface (XGMII) is a standard defined in
1515:
2297:
2064:
1547:
726:
MDC and MDIO constitute a synchronous serial data interface similar to
328:
304:
293:
1952:
2173:
2168:
2143:
2138:
2133:
2033:
1653:"KSZ8001L/S 1.8V, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver"
272:
1448:
RGMII version 1.3 uses 2.5V CMOS, whereas RGMII version 2 uses 1.5V
2105:
1953:
1024:
tolerant, however, some popular chips with RMII interfaces are not
103:
1494:
1486:
1047:. However, the IEEE version of the related MII standard specifies
2153:
2148:
2128:
1796:"Reduced Gigabit Media Independent Interface (RGMII) Version 1.3"
1734:"Reduced Gigabit Media Independent Interface (RGMII) Version 2.0"
1554:(10GbE) ports to each other and to other electronic devices on a
985:
981:
2262:
1476:
1472:
111:
1260:
727:
52:) was originally defined as a standard interface to connect a
1913:
Altera 10 Gb
Ethernet IP with XGMII and XAUI interfaces
1589:
1455:
2322:
1871:
1626:
1585:
1567:
1559:
1468:
1434:
1246:
764:
110:(CRC). The original MII transfers network data using 4-bit
1415:
Multiplexing of data received is valid and receiver error
838:
When high, clock data on TXD0 and TXD1 to the transmitter
1506:
1378:
Multiplexing of transmitter enable and transmitter error
1275:
1083:
1866:
1739:. 2002-04-01. Archived from the original on 2016-03-03.
1073:
746:
778:
RXDV and CRS signals are multiplexed into one signal.
242:
Auto-Negotiation Link
Partner Received Next Page (#8)
233:
Auto-Negotiation Link
Partner Base Page Ability (#5)
217:
The standard MII features a small set of registers:
72:
and connects different types of PHYs to MACs. Being
1111:Clock signal for gigabit TX signals (125 MHz)
786:Reduced media-independent interface (RMII) signals
734:so MDC and MDIO can be shared among multiple PHYs.
1883:Serial-GMII Specification Revision 1.7 (ENG-46158)
1020:. The specification states that inputs should be
2367:
1749:: CS1 maint: bot: original URL status unknown (
1464:but can also carry 10/100 Mbit/s Ethernet.
1208:Collision detect (half-duplex connections only)
913:MDC and MDIO can be shared among multiple PHYs.
359:Management frame preamble suppression permitted
1526: with: signal description. You can help by
1495:Quad serial gigabit media-independent interface
1487:High serial gigabit media independent interface
751:"RMII" redirects here. Not to be confused with
181:Quad serial gigabit media-independent interface
171:High serial gigabit media-independent interface
1938:
1216:Carrier sense (half-duplex connections only)
1051:trace impedance. National recommends running
992:RX_DV as a supplemental signal in RMII mode.
1629: – 10 Gigabit Attachment Unit Interface
1251:Management interface I/O bidirectional pin.
1119:Clock signal for 10/100 Mbit/s signals
940:The REF_CLK operates at 50 MHz in both
1261:Reduced gigabit media-independent interface
140:Reduced gigabit media-independent interface
1945:
1931:
1456:Serial gigabit media-independent interface
157:Serial gigabit media-independent interface
1918:GMII Timing and Electrical Specification
1717:
1715:
271:is connected to a network. It contains a
1393:(recovered from incoming received data)
1176:(recovered from incoming received data)
1092:
816:Transmit data bit 0 (transmitted first)
452:Transmit data bit 0 (transmitted first)
239:Auto-Negotiation Next Page Transmit (#7)
31:
1671:
1669:
1667:
1665:
1621:Small form-factor pluggable transceiver
1222:
805:Continuous 50 MHz reference clock
14:
2368:
1712:
1507:10 gigabit media-independent interface
533:-capable PHY to enter low power mode.
524:More recently, raising transmit error
419:
260:MMD Access Address Data Register (#14)
191:10-gigabit media-independent interface
27:Type of computer networking connection
1926:
1153:
1082:(MAC) device and the physical layer (
882:Receive error (optional on switches)
678:
2348:
1662:
1550:designed for connecting full duplex
1510:
1028:tolerant. Newer devices may support
849:Receive data bit 0 (received first)
569:Receive data bit 0 (received first)
351:Capable of unidirectional operation
149:Serial media-independent interface (
1902:"CEVA implementation documentation"
1471:by its low-power and low pin-count
1200:Signifies data received has errors
1074:Gigabit media-independent interface
747:Reduced media-independent interface
536:
230:Auto-Negotiation Advertisement (#4)
130:Gigabit media-independent interface
120:Reduced media-independent interface
24:
18:Reduced media independent interface
2008:200, 400, 800 and 1600 Gbit/s
1501:low-voltage differential signaling
730:. As with I²C, the interface is a
248:MASTER-SLAVE Status Register (#10)
245:MASTER-SLAVE Control Register (#9)
25:
2397:
1859:
1192:Signifies data received is valid
257:MMD Access Control Register (#13)
98:Network data on the interface is
2347:
2336:
2335:
1514:
1039:The RMII signals are treated as
995:
959:
275:with the following information:
1846:
1012:logic. Input high threshold is
236:Auto-Negotiation Expansion (#6)
212:
1852:IEEE 802.3 clauses 46 & 47
1829:
1812:
1788:
1757:
1726:
1701:
1679:. IEEE 802.3. 31 August 2018.
1645:
737:
13:
1:
1638:
413:Extended MII registers exist
221:Basic Mode Configuration (#0)
68:. The MII is standardized by
1801:. 2000-12-10. Archived from
1685:10.1109/IEEESTD.2018.8457469
1070:on length to minimize skew.
685:Management Data Input/Output
203:Management Data Input/Output
95:Type B carried MII signals.
7:
1610:List of interface bit rates
1604:Gigabit interface converter
1573:
1426:Management interface clock
1313:
1310:
1307:
1302:
1299:
1296:
1291:
1288:
1285:
1241:Management interface clock
926:clock where MII requires a
386:Capable of Autonegotiation
180:
170:
46:media-independent interface
10:
2402:
1677:IEEE Standard for Ethernet
1615:Medium-dependent interface
1266:Supported Ethernet speeds
781:The COL signal is removed.
750:
682:
507:Transmit error (optional)
251:PSE Control register (#11)
190:
156:
139:
2331:
2285:
2243:
2187:
2116:
2078:
2057:
2016:
1965:
1580:Attachment Unit Interface
1439:Management interface I/O
254:PSE Status register (#12)
129:
119:
2258:SFP/SFP+/QSFP/QSFP+/OSFP
1066:long and matched within
1367:Data to be transmitted
1127:Data to be transmitted
904:Management data clock.
227:PHY Identifier (#2, #3)
108:cyclic redundancy check
2003:40 and 100 Gbit/s
717:Management data clock
41:
1998:25 and 50 Gbit/s
1988:2.5 and 5 Gbit/s
1556:printed circuit board
1080:medium access control
62:medium access control
35:
827:Transmit data bit 1
485:Transmit data bit 3
474:Transmit data bit 2
463:Transmit data bit 1
1552:10 Gigabit Ethernet
1338:
1267:
1135:Transmitter enable
1093:Transmitter signals
860:Receive data bit 1
787:
763:with built-in MAC,
613:Receive data valid
602:Receive data bit 3
591:Receive data bit 2
580:Receive data bit 1
420:Transmitter signals
91:. On older PCs the
40:Creator workstation
36:MII connector on a
1958:local area network
1336:
1330:Source-synchronous
1265:
1223:Management signals
1060:series termination
1045:transmission lines
785:
679:Management signals
343:) register exists
42:
2363:
2362:
2215:Energy Efficiency
2070:Ethernet Alliance
1722:AN-1469 datasheet
1708:AN-1405 schematic
1694:978-1-5044-5090-4
1544:
1543:
1446:
1445:
1318:
1317:
1281:Bits/clock cycle
1255:
1254:
1220:
1219:
1147:
1146:
911:
910:
724:
723:
653:
652:
646:Collision detect
514:
513:
417:
416:
394:Link established
339:Extended status (
331:full/half duplex
319:full/half duplex
307:full/half duplex
74:media independent
64:(MAC) block to a
16:(Redirected from
2393:
2351:
2350:
2339:
2338:
1947:
1940:
1933:
1924:
1923:
1909:
1904:. Archived from
1897:
1895:
1889:, archived from
1888:
1853:
1850:
1844:
1843:
1841:
1833:
1827:
1826:
1824:
1816:
1810:
1809:
1807:
1800:
1792:
1786:
1785:
1783:
1782:
1776:
1770:. Archived from
1769:
1761:
1755:
1754:
1748:
1740:
1738:
1730:
1724:
1719:
1710:
1705:
1699:
1698:
1673:
1660:
1659:
1657:
1649:
1539:
1536:
1518:
1511:
1462:Gigabit Ethernet
1339:
1335:
1271:[Mbit/s]
1268:
1264:
1227:
1226:
1158:
1157:
1154:Receiver signals
1097:
1096:
1069:
1065:
1058:
1054:
1050:
1035:
1031:
1027:
1023:
1019:
1015:
1011:
1007:
955:
951:
947:
943:
929:
925:
922:RMII requires a
893:Management data
788:
784:
761:microcontrollers
706:Management data
689:
688:
541:
540:
537:Receiver signals
496:Transmit enable
424:
423:
341:Gigabit Ethernet
278:
277:
224:Status Word (#1)
59:
38:Sun Ultra 1
21:
2401:
2400:
2396:
2395:
2394:
2392:
2391:
2390:
2366:
2365:
2364:
2359:
2327:
2281:
2239:
2183:
2112:
2074:
2053:
2029:Autonegotiation
2012:
1978:100 Mbit/s
1961:
1951:
1900:
1893:
1886:
1880:
1862:
1857:
1856:
1851:
1847:
1839:
1835:
1834:
1830:
1822:
1818:
1817:
1813:
1805:
1798:
1794:
1793:
1789:
1780:
1778:
1774:
1767:
1763:
1762:
1758:
1742:
1741:
1736:
1732:
1731:
1727:
1720:
1713:
1706:
1702:
1695:
1675:
1674:
1663:
1655:
1651:
1650:
1646:
1641:
1633:XFP transceiver
1594:data link layer
1576:
1540:
1534:
1531:
1524:needs expansion
1509:
1497:
1489:
1458:
1263:
1225:
1156:
1095:
1076:
1067:
1063:
1056:
1052:
1048:
1033:
1029:
1025:
1021:
1017:
1013:
1009:
1005:
998:
962:
953:
949:
945:
941:
927:
923:
756:
749:
740:
687:
681:
539:
441:Transmit clock
422:
368:Autonegotiation
215:
207:autonegotiation
102:using the IEEE
57:
28:
23:
22:
15:
12:
11:
5:
2399:
2389:
2388:
2383:
2381:Computer buses
2378:
2361:
2360:
2358:
2357:
2345:
2332:
2329:
2328:
2326:
2325:
2320:
2315:
2310:
2305:
2300:
2295:
2289:
2287:
2283:
2282:
2280:
2279:
2274:
2269:
2260:
2255:
2249:
2247:
2241:
2240:
2238:
2237:
2232:
2227:
2222:
2217:
2212:
2207:
2202:
2197:
2191:
2189:
2185:
2184:
2182:
2181:
2176:
2171:
2166:
2161:
2156:
2151:
2146:
2141:
2136:
2131:
2126:
2120:
2118:
2114:
2113:
2111:
2110:
2109:
2108:
2098:
2093:
2088:
2082:
2080:
2076:
2075:
2073:
2072:
2067:
2061:
2059:
2055:
2054:
2052:
2051:
2046:
2041:
2036:
2031:
2026:
2024:Physical layer
2020:
2018:
2014:
2013:
2011:
2010:
2005:
2000:
1995:
1993:10 Gbit/s
1990:
1985:
1980:
1975:
1973:10 Mbit/s
1969:
1967:
1963:
1962:
1950:
1949:
1942:
1935:
1927:
1921:
1920:
1915:
1910:
1908:on 2006-12-11.
1898:
1878:
1873:
1868:
1861:
1860:External links
1858:
1855:
1854:
1845:
1828:
1811:
1808:on 2016-03-03.
1787:
1756:
1725:
1711:
1700:
1693:
1661:
1643:
1642:
1640:
1637:
1636:
1635:
1630:
1624:
1618:
1612:
1607:
1601:
1598:physical layer
1583:
1575:
1572:
1542:
1541:
1521:
1519:
1508:
1505:
1496:
1493:
1488:
1485:
1481:clock recovery
1457:
1454:
1444:
1443:
1442:Bidirectional
1440:
1437:
1431:
1430:
1427:
1424:
1420:
1419:
1416:
1413:
1409:
1408:
1405:
1404:Received data
1402:
1398:
1397:
1394:
1387:
1383:
1382:
1379:
1376:
1372:
1371:
1368:
1365:
1361:
1360:
1357:
1354:
1350:
1349:
1346:
1343:
1337:RGMII signals
1316:
1315:
1312:
1309:
1305:
1304:
1301:
1298:
1294:
1293:
1290:
1287:
1283:
1282:
1279:
1272:
1262:
1259:
1253:
1252:
1249:
1243:
1242:
1239:
1235:
1234:
1231:
1224:
1221:
1218:
1217:
1214:
1210:
1209:
1206:
1202:
1201:
1198:
1194:
1193:
1190:
1186:
1185:
1184:Received data
1182:
1178:
1177:
1170:
1166:
1165:
1162:
1155:
1152:
1145:
1144:
1141:
1137:
1136:
1133:
1129:
1128:
1125:
1121:
1120:
1117:
1113:
1112:
1109:
1105:
1104:
1101:
1094:
1091:
1075:
1072:
1041:lumped signals
997:
994:
961:
958:
909:
908:
905:
902:
898:
897:
896:Bidirectional
894:
891:
887:
886:
883:
880:
876:
875:
872:
869:
865:
864:
861:
858:
854:
853:
850:
847:
843:
842:
839:
836:
832:
831:
828:
825:
821:
820:
817:
814:
810:
809:
806:
803:
799:
798:
795:
792:
783:
782:
779:
776:
773:
748:
745:
739:
736:
722:
721:
718:
715:
711:
710:
709:Bidirectional
707:
704:
700:
699:
696:
693:
683:Main article:
680:
677:
651:
650:
647:
644:
640:
639:
636:
635:Carrier sense
633:
629:
628:
625:
624:Receive error
622:
618:
617:
614:
611:
607:
606:
603:
600:
596:
595:
592:
589:
585:
584:
581:
578:
574:
573:
570:
567:
563:
562:
559:
558:Receive clock
556:
552:
551:
548:
545:
538:
535:
512:
511:
508:
505:
501:
500:
497:
494:
490:
489:
486:
483:
479:
478:
475:
472:
468:
467:
464:
461:
457:
456:
453:
450:
446:
445:
442:
439:
435:
434:
431:
428:
421:
418:
415:
414:
411:
407:
406:
400:
396:
395:
392:
388:
387:
384:
380:
379:
376:
372:
371:
365:
361:
360:
357:
353:
352:
349:
345:
344:
337:
333:
332:
325:
321:
320:
313:
309:
308:
301:
297:
296:
290:
286:
285:
282:
262:
261:
258:
255:
252:
249:
246:
243:
240:
237:
234:
231:
228:
225:
222:
214:
211:
199:
198:
188:
178:
168:
154:
147:
137:
127:
26:
9:
6:
4:
3:
2:
2398:
2387:
2384:
2382:
2379:
2377:
2374:
2373:
2371:
2356:
2355:
2346:
2344:
2343:
2334:
2333:
2330:
2324:
2321:
2319:
2316:
2314:
2311:
2309:
2306:
2304:
2301:
2299:
2296:
2294:
2291:
2290:
2288:
2284:
2278:
2275:
2273:
2270:
2268:
2264:
2261:
2259:
2256:
2254:
2251:
2250:
2248:
2246:
2242:
2236:
2233:
2231:
2228:
2226:
2223:
2221:
2218:
2216:
2213:
2211:
2208:
2206:
2203:
2201:
2198:
2196:
2193:
2192:
2190:
2186:
2180:
2177:
2175:
2172:
2170:
2167:
2165:
2162:
2160:
2157:
2155:
2152:
2150:
2147:
2145:
2142:
2140:
2137:
2135:
2132:
2130:
2127:
2125:
2122:
2121:
2119:
2115:
2107:
2104:
2103:
2102:
2099:
2097:
2094:
2092:
2089:
2087:
2084:
2083:
2081:
2077:
2071:
2068:
2066:
2063:
2062:
2060:
2058:Organizations
2056:
2050:
2047:
2045:
2042:
2040:
2037:
2035:
2032:
2030:
2027:
2025:
2022:
2021:
2019:
2015:
2009:
2006:
2004:
2001:
1999:
1996:
1994:
1991:
1989:
1986:
1984:
1983:1 Gbit/s
1981:
1979:
1976:
1974:
1971:
1970:
1968:
1964:
1959:
1955:
1948:
1943:
1941:
1936:
1934:
1929:
1928:
1925:
1919:
1916:
1914:
1911:
1907:
1903:
1899:
1896:on 2015-07-14
1892:
1885:
1884:
1879:
1877:
1874:
1872:
1869:
1867:
1864:
1863:
1849:
1842:. 1995-08-01.
1838:
1832:
1825:. 2006-06-01.
1821:
1815:
1804:
1797:
1791:
1777:on 2014-04-13
1773:
1766:
1765:"XWAY PHY11G"
1760:
1752:
1746:
1735:
1729:
1723:
1718:
1716:
1709:
1704:
1696:
1690:
1686:
1682:
1678:
1672:
1670:
1668:
1666:
1654:
1648:
1644:
1634:
1631:
1628:
1625:
1622:
1619:
1616:
1613:
1611:
1608:
1605:
1602:
1599:
1595:
1591:
1587:
1584:
1581:
1578:
1577:
1571:
1569:
1565:
1561:
1557:
1553:
1549:
1538:
1529:
1525:
1522:This section
1520:
1517:
1513:
1512:
1504:
1502:
1492:
1484:
1482:
1478:
1474:
1470:
1465:
1463:
1453:
1451:
1441:
1438:
1436:
1433:
1432:
1428:
1425:
1422:
1421:
1417:
1414:
1411:
1410:
1406:
1403:
1400:
1399:
1395:
1392:
1388:
1385:
1384:
1380:
1377:
1374:
1373:
1369:
1366:
1363:
1362:
1358:
1356:Clock signal
1355:
1352:
1351:
1347:
1344:
1341:
1340:
1334:
1331:
1326:
1322:
1306:
1295:
1284:
1280:
1277:
1273:
1270:
1269:
1258:
1250:
1248:
1245:
1244:
1240:
1237:
1236:
1232:
1229:
1228:
1215:
1212:
1211:
1207:
1204:
1203:
1199:
1196:
1195:
1191:
1188:
1187:
1183:
1180:
1179:
1175:
1171:
1168:
1167:
1163:
1160:
1159:
1151:
1142:
1139:
1138:
1134:
1131:
1130:
1126:
1123:
1122:
1118:
1115:
1114:
1110:
1107:
1106:
1102:
1099:
1098:
1090:
1087:
1085:
1081:
1071:
1061:
1046:
1042:
1037:
1004:are used for
1003:
996:Signal levels
993:
989:
987:
983:
979:
975:
971:
966:
957:
938:
936:
935:double-pumped
933:
920:
917:
914:
906:
903:
900:
899:
895:
892:
889:
888:
884:
881:
878:
877:
873:
870:
867:
866:
862:
859:
856:
855:
851:
848:
845:
844:
840:
837:
834:
833:
829:
826:
823:
822:
818:
815:
812:
811:
807:
804:
801:
800:
796:
793:
790:
789:
780:
777:
774:
770:
769:
768:
766:
762:
754:
744:
735:
733:
732:multidrop bus
729:
719:
716:
713:
712:
708:
705:
702:
701:
697:
694:
691:
690:
686:
676:
673:
669:
667:
666:false carrier
661:
657:
648:
645:
642:
641:
637:
634:
631:
630:
626:
623:
620:
619:
615:
612:
609:
608:
604:
601:
598:
597:
593:
590:
587:
586:
582:
579:
576:
575:
571:
568:
565:
564:
560:
557:
554:
553:
549:
546:
543:
542:
534:
532:
527:
522:
518:
509:
506:
503:
502:
498:
495:
492:
491:
487:
484:
481:
480:
476:
473:
470:
469:
465:
462:
459:
458:
454:
451:
448:
447:
443:
440:
437:
436:
432:
429:
426:
425:
412:
409:
408:
404:
401:
398:
397:
393:
390:
389:
385:
382:
381:
378:Remote fault
377:
374:
373:
369:
366:
363:
362:
358:
355:
354:
350:
347:
346:
342:
338:
335:
334:
330:
326:
323:
322:
318:
314:
311:
310:
306:
302:
299:
298:
295:
291:
288:
287:
283:
280:
279:
276:
274:
270:
265:
259:
256:
253:
250:
247:
244:
241:
238:
235:
232:
229:
226:
223:
220:
219:
218:
210:
208:
204:
196:
192:
189:
186:
182:
179:
176:
172:
169:
166:
162:
158:
155:
152:
148:
145:
141:
138:
135:
131:
128:
125:
121:
118:
117:
116:
113:
109:
105:
101:
96:
94:
93:CNR connector
90:
85:
83:
79:
75:
71:
67:
63:
55:
54:Fast Ethernet
51:
47:
39:
34:
30:
19:
2386:Serial buses
2352:
2340:
2307:
2245:Transceivers
2188:Applications
2091:Twisted pair
2039:Flow control
1960:technologies
1906:the original
1891:the original
1882:
1848:
1831:
1814:
1803:the original
1790:
1779:. Retrieved
1772:the original
1759:
1728:
1703:
1676:
1647:
1566:(312.5
1545:
1532:
1528:adding to it
1523:
1498:
1490:
1466:
1459:
1447:
1391:clock signal
1345:Description
1342:Signal name
1327:
1323:
1319:
1256:
1233:Description
1230:Signal name
1174:clock signal
1164:Description
1161:Signal name
1148:
1103:Description
1100:Signal name
1088:
1077:
1055:traces with
1043:rather than
1038:
1002:logic levels
999:
990:
978:lost carrier
977:
973:
967:
963:
939:
931:
921:
918:
915:
912:
794:Description
791:Signal name
757:
741:
725:
695:Description
692:Signal name
674:
670:
668:indication.
665:
662:
658:
654:
547:Description
544:Signal name
525:
523:
519:
515:
430:Description
427:Signal name
269:Ethernet NIC
266:
263:
216:
213:Standard MII
200:
194:
184:
174:
164:
160:
150:
143:
133:
123:
97:
86:
78:twisted pair
73:
49:
45:
43:
29:
2235:Synchronous
2210:Data center
1429:MAC to PHY
1418:PHY to MAC
1407:PHY to MAC
1396:PHY to MAC
1381:MAC to PHY
1370:MAC to PHY
1359:MAC to PHY
1016:and low is
960:Limitations
907:MAC to PHY
885:PHY to MAC
874:PHY to MAC
863:PHY to MAC
852:PHY to MAC
841:MAC to PHY
830:MAC to PHY
819:MAC to PHY
738:Limitations
720:MAC to PHY
649:PHY to MAC
638:PHY to MAC
627:PHY to MAC
616:PHY to MAC
605:PHY to MAC
594:PHY to MAC
583:PHY to MAC
572:PHY to MAC
561:PHY to MAC
510:MAC to PHY
499:MAC to PHY
488:MAC to PHY
477:MAC to PHY
466:MAC to PHY
455:MAC to PHY
444:PHY to MAC
327:Capable of
315:Capable of
303:Capable of
292:Capable of
161:serial GMII
82:fiber optic
70:IEEE 802.3u
2370:Categories
2286:Interfaces
2220:Industrial
2200:Automotive
2179:Long Reach
2101:First mile
2065:IEEE 802.3
1956:family of
1781:2014-04-11
1639:References
1548:IEEE 802.3
1348:Direction
1311:125
974:no carrier
942:100 Mbit/s
797:Direction
698:Direction
550:Direction
433:Direction
329:100BASE-T2
305:100BASE-TX
294:100BASE-T4
281:Bit value
58:100 Mbit/s
2174:LattisNet
2169:100BaseVG
2144:10BASE-FL
2139:10BASE-FB
2134:10BROAD36
2034:EtherType
1535:July 2023
1389:Received
1300:25
1172:Received
954:10 Mbit/s
950:10 Mbit/s
946:10 Mbit/s
944:mode and
405:detected
370:complete
273:bit field
2376:Ethernet
2342:Category
2117:Historic
2106:10G-EPON
1954:Ethernet
1745:cite web
1596:and the
1574:See also
802:REF_CLK
317:10BASE-T
284:Meaning
104:Ethernet
66:PHY chip
2354:Commons
2205:Carrier
2154:10BASE2
2149:10BASE5
2129:StarLAN
2124:CSMA/CD
2096:Coaxial
2017:General
1475:-coded
1412:RX_CTL
1375:TX_CTL
1108:GTXCLK
1036:logic.
986:10BASE5
982:10BASE2
868:CRS_DV
772:switch.
555:RX_CLK
526:outside
438:TX_CLK
112:nibbles
56:(i.e.,
2263:XENPAK
2049:Jumbos
2044:Frames
1966:Speeds
1691:
1606:(GBIC)
1477:SerDes
1473:8b/10b
1169:RXCLK
1116:TXCLK
1068:0.05 m
1064:0.15 m
956:mode.
928:25 MHz
924:50 MHz
879:RX_ER
835:TX_EN
621:RX_ER
610:RX_DV
504:TX_ER
493:TX_EN
410:0x0001
403:Jabber
399:0x0002
391:0x0004
383:0x0008
375:0x0010
364:0x0020
356:0x0040
348:0x0080
336:0x0100
324:0x0600
312:0x1800
300:0x6000
289:0x8000
185:QSGMII
175:HSGMII
100:framed
2318:XGMII
2230:Power
2225:Metro
2195:Audio
2164:FOIRL
2086:Fiber
2079:Media
1894:(PDF)
1887:(PDF)
1840:(PDF)
1823:(PDF)
1806:(PDF)
1799:(PDF)
1775:(PDF)
1768:(PDF)
1737:(PDF)
1656:(PDF)
1623:(SFP)
1617:(MDI)
1590:ITU-T
1588:, an
1582:(AUI)
1308:1000
1278:]
1274:[
1197:RXER
1189:RXDV
1140:TXER
1132:TXEN
1034:1.8 V
1030:2.5 V
1018:0.8 V
1014:2.0 V
1010:3.3 V
890:MDIO
857:RXD1
846:RXD0
824:TXD1
813:TXD0
765:FPGAs
703:MDIO
599:RXD3
588:RXD2
577:RXD1
566:RXD0
482:TXD3
471:TXD2
460:TXD1
449:TXD0
195:XGMII
165:SGMII
144:RGMII
2323:XAUI
2313:GMII
2253:GBIC
1751:link
1689:ISBN
1627:XAUI
1586:G.hn
1568:MT/s
1560:XAUI
1469:GMII
1450:HSTL
1435:MDIO
1423:MDC
1401:RXD
1386:RXC
1364:TXD
1353:TXC
1297:100
1289:2.5
1247:MDIO
1238:MDC
1205:COL
1181:RXD
1124:TXD
1057:33 Ω
1053:50 Ω
1049:68 Ω
1032:and
1000:TTL
976:and
901:MDC
714:MDC
643:COL
632:CRS
201:The
151:SMII
134:GMII
124:RMII
44:The
2308:MII
2303:MDI
2298:EAD
2293:AUI
2277:CFP
2272:XFP
2159:MAU
1681:doi
1570:).
1564:DDR
1530:.
1286:10
1276:MHz
1213:CS
1084:PHY
1026:5 V
1022:5 V
1008:or
1006:5 V
984:or
970:CRC
937:).
932:not
753:RM2
728:I²C
531:EEE
89:PCB
50:MII
2372::
2267:X2
1747:}}
1743:{{
1714:^
1687:.
1664:^
1452:.
1314:8
1303:4
1292:4
988:.
163:,
80:,
60:)
2265:/
1946:e
1939:t
1932:v
1784:.
1753:)
1697:.
1683::
1658:.
1600:.
1537:)
1533:(
755:.
197:)
193:(
187:)
183:(
177:)
173:(
167:)
159:(
153:)
146:)
142:(
136:)
132:(
126:)
122:(
48:(
20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
_connector_on_sun_ultra_1.jpg)