25:
471:
1398:– Includes eight e500mc cores, each with 32/32kB instruction/data L1 caches and a 128 kB L2 cache. The chip has dual 1 MB L3 caches, each connected to a 64-bit DDR2/DDR3 memory controller. The chip contains a security and encryption module, capable of packet parsing and classification, and acceleration of encryption and
1316:
The P3 family processors share the same physical package with, and are also software backwards compatible with, P4 and P5. The P3 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions,
642:
LS1 means LS1XXX series (e.g., LS1021A, etc.); LS2 means LS2XXX series. LS2 means a higher performance level than LS1, and it does not indicate a second generation. The middle two digits of the product name are core count; the last digit distinguishes models, with, in most but not all cases, a higher
1390:
The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.
1320:
The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.
1522:
processing units except the lowest end T1 family that uses the older e5500 core. Products will range from single core versions up to parts with 12 cores or more with frequencies ranging all the way up to 2.5 GHz. The processes will be sectioned into five classes according to performance and
1498:
SoC processors targeting wireless infrastructure applications. The PSC913x family chips uses an e500 core based CPU and StarCore SC3850 DSPs will be available in 2011, and is manufactured on a 45 nm process, with e6500 and CS3900 core based 28 nm parts available in 2012 called P4xxx.
1626:
because so many cores require a different system design. In order to restore simplicity and still get the highest level of performance, the telecommunication systems are based on a segregation of the cores. Some cores are used for the control plane while some others are used for a re-designed
670:
Freescale
Semiconductor Inc. (acquired by NXP Semiconductors in late 2015) announced a network processor system architecture said to give the flexibility and scalability required by network infrastructure OEMs to handle the market trends of connected devices, massive datasets, tight security,
1402:
pattern matching. The chip can be configured with up to eight
Gigabit and two 10 Gigabit Ethernet controllers, three 5 GHz PCIe ports and two RapidIO interfaces. It also has various other peripheral connectivity such as two USB2 controllers. It is designed to operate below 30 W at
1449:
fabric. The P5 series processors share the same physical package and are also software backwards compatible with P3 and P4. The P5 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular
1570:– Processors with four cores running at speeds of 1.5 to 1.8 GHz. The '81 parts comes in smaller package, slightly different I/O options and therefore fewer I/O pins. The T2081 is pin compatible with the lower end T104x and T102x parts.
2064:
1057:
The QorIQ P Series processors are based on e500 or e5500 cores. The P10xx series, P2010 and P2020 are based on the e500v2 core, P204x, P30xx and P40xx on the e500mc core, and P50xx on the e5500 core. Features include 32/32
1104:
is tailored for gateways, Ethernet switches, wireless LAN access points, and general-purpose control applications. It is the entry level platform, ranging from 400 to 800 MHz devices. It is designed to replace the
638:
with providing ECC for caches and DDR3/4 at 1000 to 1600 MT/s, dual PCI Express
Controllers in x1/x2/x4 operation, SD/MMC, SATA 1/2/3, USB 2/3 with integrated PHY, and virtualized dTSEC Gigabit Ethernet Controllers.
1931:
1851:
2059:
2005:
1195:
is designed for a wide variety of applications in the networking, telecom, military and industrial markets. It will be available in special high quality parts, with junction tolerances from −40 to 125
1419:
for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008.
2266:
1199:, especially suited for demanding out doors environments. It is the mid-level platform, with devices ranging from 800 MHz up to 1.2 GHz. It is designed to replace the
611:(like compression) may be implemented in software or hardware, depending on the specific chip, but transparent to application programmers. LS-1 and LS-2 are announced to use
540:
cores and came in five different product platforms, P1, P2, P3, P4, and P5, segmented by performance and functionality. The platform keeps software compatibility with older
1367:
cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated
1293:
cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated
1383:, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet,
1309:, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet,
1949:
2044:
1338:– Quad 1.5 GHz cores, 128 kB L2 cache per core, single 1.3 GHz 64-bit DDR3 controller. Manufactured on a 45 nm process operating in a 12 W envelope.
457:
2009:
2259:
1785:
1469:– Dual e5500 2.2 GHz cores, dual 1 MB L3 caches, dual 1.333 lGHz DDR3 controllers, manufactured on a 45 nm process and operating in a 30W envelope.
1622:. For instance, when 4 or 8 cores are used, such as the P4080, in order to achieve millions of Packet Processing per seconds, the system does not scale with
1463:– Single e5500 2.2 GHz core, 1 MB L3 cache, single 1.333 lGHz DDR3 controller, manufactured on a 45 nm process and operating in a 30W envelope.
2252:
1456:
Applications range from high end networking control plane infrastructure, high end storage networking and complex military and industrial devices.
599:
agnostic
Layerscape architecture. They are available since 2013 and target low and mid range networking and wireless infrastructure applications.
1579:
The T1 family uses the e5500 64-bit single threaded core at 1.2 to 1.5 GHz with 256 kB L2 cache per core and 256kB shared CoreNet L3 cache.
634:
The initial LS-1 series does not include any accelerated packet processing layer, focusing typical power consumption of less than 3W using two
565:
2091:
1422:
Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so
551:
The QorIQ brand and the P1, P2 and P4 product families were announced in June 2008. Details of P3 and P5 products were announced in 2010.
2029:
1372:
1298:
450:
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core scaling up to 2.5 GHz and allowing numerous auxiliary application processing units as well as multi core operation via the
1745:
1957:
443:
2065:
MontaVista
Provides First No-Cost Evaluation of Commercial Linux for Freescale QorIQ P4080 Multicore Processor – Money.AOL.com
1932:"Freescale Introduces Industry's First Multimode Wireless Base Station Processor Family That Scales from Small to Large Cells"
405:
1720:
1618:
The QorIQ products bring some new challenges in order to design some control planes of telecommunication systems and their
608:
2655:
1403:
1.5 GHz. The processor is manufactured on a 45 nm SOI process and begun sampling to customers in August 2009.
415:
607:
The
Layerscape (LS) architecture is the latest evolution of the QorIQ family, in that features previously provided by
1641:
to provide software developers with a high-performance commercial packet processing solution for the QorIQ platform.
1544:– A feature reduced version of the T4240 with only eight cores, and less I/O options and just two memory controllers.
1538:– The first product announced and incorporates twelve cores, three memory controllers and various other accelerators.
390:
1550:– A feature reduced version of the T4240 with only four cores, and less I/O options and just two memory controllers.
2822:
2084:
2030:
6WIND Software
Provides 10x the Performance with Lower Power Consumption for Systems Based on Freescale QorIQ P4080
558:
2288:
1768:
D. Mistry, P. Modi, K. Deokule, A. Patel, H. Patki and O. Abuzaghleh, "Network traffic measurement and analysis,"
2121:
1207:
platforms. The chips include, among other integrated functionality, a 512 kB L2 cache, a security engine, three
2817:
1481:– Quad e5500 2.4 GHz cores, 1.6 GHz DDR3/3L. Sampling since March 2012; production expected in 4Q12.
1475:– Dual e5500 2.4 GHz cores, 1.6 GHz DDR3/3L. Sampling since March 2012; production expected in 4Q12.
1255:
interfaces. The chips are packaged in 689-pin packages which are pin compatible with the P1 family processors.
1081:
layer is present in products featuring the e500mc or the e5500. The dual and multi-core devices supports both
1157:
interfaces. The chip is packaged in 689-pin packages which are pin compatible with the P2 family processors.
643:
digit meaning greater performance. “A” at the end indicates the Arm processor. LX designates the 16 nm
658:
and network peripheral interfaces. These features are frequently required for networking, telecom/datacom,
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2244:
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1868:
1993:
1982:
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1086:
410:
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Introduced in June 2010, samples will be available late 2010 and full production is expected in 2011.
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1827:
1803:
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144:
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features, named T1 through T5, and will be manufactured in a 28 nm process beginning in 2012.
1495:
2628:
2202:
2054:
2537:
1950:"Freescale Drives Embedded Multicore Innovation with New QorIQ Advanced Multiprocessing Series"
58:
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1224:
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620:
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2423:
2314:
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651:
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The LS1 family is built on the
Layerscape architecture is a programmable data-plane engine
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8:
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38:
Please help update this article to reflect recent events or newly available information.
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2100:
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572:. These are using the e6500 core with AltiVec and are expected to be shipping in 2013.
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2060:
QorIQ 45-nm communications MPUs feature dual cores, low power – ElectronicProducts.com
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1204:
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1363:. The P4 family offers an extreme multi-core platform, with support for up to eight
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1416:
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To help software developers and system designers get started with the QorIQ P4080,
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654:. Both LS1 and LS2 families of processors offer the advanced, high-performance
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and was available in the end of 2008 (P1 and P2), mid-2009 (P4) and 2010 (P5).
521:
1994:
T2080: QorIQ T Series T2080/T2081 Eight
Virtual Core Communications Processors
1983:
T4240: QorIQ T Series T4240/T4160 24/16 Virtual Core
Communications Processors
568:
process and is pushing a very aggressive power envelope target, capping at 30
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1770:
2016 IEEE Long Island Systems, Applications and Technology Conference (LISAT)
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1828:"P2 Series Single- and dual-core communications processors – Freescale.com"
1804:"P1 Series Single- and Dual-Core Communications Processors – Freescale.com"
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real-time service and increasingly unpredictable network traffic patterns.
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1289:. The P3 family offers a multi-core platform, with support for up to four
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1216:
1122:
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533:
470:
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235:
1914:"6WIND - Virtualized Networking Software on Cloud Native Architecture"
1182:, four SerDes lanes, three Gbit Ethernet controllers and a TDM engine.
544:
products such as the PowerQUICC platform. In 2012 Freescale announced
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2126:
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1953:
1634:
1423:
1412:
1408:
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host controller and high speed interfaces which can be configured as
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400:
66:
2767:
2233:
1598:– Dual-core, four Gbit Ethernet ports and an 8 port Ethernet switch
1586:– Quad-core, four Gbit Ethernet ports and an 8 port Ethernet switch
1368:
1294:
1179:
1165:
1113:
platforms. The chips include among other integrated functionality,
1063:
1059:
655:
289:
1426:
and 6WIND ported 6WIND's packet processing software to the P4080.
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QorIQ LS-1 and LS-2 families are ARM based processors using the
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platform, and initial products were built around one or more
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492:
2787:
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1519:
1376:
1302:
1244:
1220:
1168:, four SerDes lanes, three Gbit Ethernet controllers and a
1150:
1126:
569:
495:
363:
1604:– Dual-core, five Gbit Ethernet ports, no Ethernet switch.
1592:– Quad-core, five Gbit Ethernet ports, no Ethernet switch.
2436:
1913:
501:
2055:
Migrating PowerQUICC® III Processors to QorIQ™ Platforms
1559:
The T2 family uses the e6500 64-bit dual threaded core.
1531:
The T4 family uses the e6500 64-bit dual threaded core.
1351:
is a high performance networking platform, designed for
1511:, processors are all based on the multithreaded 64-bit
1450:
expressions, RAID, security, cryptography and RapidIO.
1281:
is a mid performance networking platform, designed for
1268:– Includes two 1.2 GHz cores, with shared L2 cache
2276:
Motorola-Freescale-NXP processors and microcontrollers
1721:"6 network and security trends you can expect in 2017"
1178:– includes two 800 MHz e500 cores, 256 kB shared
1092:, and can run multiple operating systems in parallel.
1869:"P4 Series P4080 multicore processor – Freescale.com"
498:
489:
1696:"Nov 2012: Layercape – New Embedded Family Solution"
1371:, memory controllers, multiple I/O-devices such as
1073:is present on some cores (not all) and support for
486:
1297:, memory controller, multiple I/O-devices such as
674:
554:QorIQ P Series processors were manufactured on a
2804:
1490:In February 2011 Freescale introduced the QorIQ
1893:"Virtutech page about P4080 simulation support"
1852:"NXP® Semiconductors Official Site | Home"
1494:platform which is a series of combined CPU and
1164:– Includes one 800 MHz e500 core, 256 kB
2260:
2085:
474:P4080 QorIQ processor Freescale Semiconductor
451:
2050:EE Times, NXP Processor Powers IoT, Networks
1614:Networking, IT and telecommunication systems
1679:
1677:
1675:
2267:
2253:
2092:
2078:
1317:RAID, security, cryptography and RapidIO.
548:-based QorIQ offerings beginning in 2013.
458:
444:
1121:controllers, a security engine, a 32-bit
1978:
1976:
1974:
1684:Freescale adopts ARM cores in QorIQ line
1672:
1066:, 36-bit physical memory addressing , a
532:). It is the evolutionary step from the
469:
1243:lanes which can be configured as three
665:
662:, military and aerospace applications.
2805:
2099:
1780:
1778:
1637:has partnered with networking company
2248:
2073:
1971:
74:NXP (formerly Freescale and Motorola)
2654:
1906:
1507:The QorIQ Advanced Multiprocessing,
18:
1775:
13:
1743:
14:
2834:
2038:
1820:
1796:
1772:, Farmingdale, NY, 2016, pp. 1–7.
1762:
1438:is based on the high performance
2045:NXP Semiconductors QorIQ website
1718:
1608:
1262:– Includes one 1.2 GHz core
482:
23:
2122:Communications Processor Module
2023:
1998:
1987:
1942:
1924:
1885:
1861:
1746:"The Top 8 IoT Trends For 2018"
1239:host controller and high speed
2287:
1844:
1737:
1712:
1688:
1387:, RapidIO or PCIe interfaces.
1313:, RapidIO or PCIe interfaces.
1172:for legacy phone applications.
675:Layerscape product family list
1:
1666:
1502:
602:
564:QorIQ T Series is based on a
1956:. 2011-06-21. Archived from
7:
1644:
1485:
1227:support, dual four-channel
1133:support, dual four-channel
1052:
10:
2839:
2760:
2739:
2723:
2664:
2653:
2649:
2627:
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2536:
2509:
2484:
2432:
2369:
2313:
2297:
2286:
2282:
2221:
2195:
2107:
693:
32:This article needs to be
2006:"regular software stack"
81:PowerPC e series (2006)
2823:PowerPC microprocessors
2538:Memory management units
2298:Industrial control unit
2203:Freescale Semiconductor
1223:memory controller with
1129:memory controller with
660:wireless infrastructure
652:networking architecture
1631:based on a Fast Path.
1624:regular software stack
520:–based communications
475:
214:PowerPC series (1992)
2818:Power microprocessors
1574:
1554:
1526:
1429:
1355:and enterprise level
1342:
1272:
1215:controller, a 64-bit
1186:
1095:
1035:24 lanes 25 GHz
473:
1938:. February 14, 2011.
1936:www.businesswire.com
1790:www.businesswire.com
1026:16 x ARM Cortex-A72
1006:4 lanes 10 GHz
977:8 lanes 10 GHz
948:4 lanes 10 GHz
919:4 lanes 10 GHz
890:4 lanes 10 GHz
666:Initial announcement
381:OpenPOWER Foundation
16:Microprocessor range
1385:10 Gigabit Ethernet
1353:backbone networking
1311:10 Gigabit Ethernet
1251:interfaces and two
1071:floating point unit
997:8 x ARM Cortex-A53
968:4 x ARM Cortex-A72
939:2 x ARM Cortex-A53
910:4 x ARM Cortex-A53
881:2 x ARM Cortex-A72
861:3 lanes 5 GHz
803:4 lanes 6 GHz
774:4 lanes 6 GHz
745:3 lanes 6 GHz
736:1 x ARM Cortex-A53
559:fabrication process
2813:NXP Semiconductors
2101:NXP Semiconductors
852:2 x ARM Cortex-A9
832:1 lane 5 GHz
823:2 x ARM Cortex-A7
794:2 x ARM Cortex-A7
765:2 x ARM Cortex-A7
526:NXP Semiconductors
476:
434:historic in italic
262:RAD series (1997)
118:Qor series (2008)
2800:
2799:
2796:
2795:
2645:
2644:
2242:
2241:
1201:PowerQUICC II Pro
1117:controllers, two
1107:PowerQUICC II Pro
1062:data/instruction
1050:
1049:
468:
467:
430:Cancelled in gray
53:
52:
2830:
2657:Microcontrollers
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2650:
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2017:
2008:. Archived from
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1744:Newman, Daniel.
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1700:
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1515:with integrated
1417:virtual platform
1247:interfaces, two
1209:Gigabit Ethernet
1115:Gigabit Ethernet
1068:double precision
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2434:Embedded system
2428:
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2213:VLSI Technology
2191:
2172:Signetics 8X300
2103:
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2041:
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2024:
2015:
2013:
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1345:
1275:
1231:controllers, a
1211:controllers, a
1189:
1137:controllers, a
1098:
1090:multiprocessing
1055:
719:Integrated SEC
677:
668:
605:
595:cores upon the
522:microprocessors
485:
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429:
341:
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69:architectures
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35:
30:
21:
20:
2783:PowerPC 5000
2656:
2613:
2514:coprocessors
2371:68000 family
2334:Hitachi 6309
2289:
2196:Acquisitions
2161:
2117:555 timer IC
2025:
2014:. Retrieved
2010:the original
2000:
1989:
1962:. Retrieved
1958:the original
1944:
1935:
1926:
1917:
1908:
1896:. Retrieved
1887:
1875:. Retrieved
1863:
1846:
1834:. Retrieved
1822:
1810:. Retrieved
1798:
1789:
1769:
1764:
1753:. Retrieved
1749:
1739:
1728:. Retrieved
1724:
1714:
1702:. Retrieved
1690:
1656:PowerPC e500
1633:
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1601:
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1415:to create a
1411:worked with
1406:
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1346:
1335:
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1319:
1315:
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669:
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647:generation.
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550:
478:
477:
433:
386:AIM alliance
362:
322:
315:
308:
301:IBM/Nintendo
288:
265:
241:
234:
217:
178:
171:
164:
157:
150:
121:
41:
33:
2315:6800 family
2152:NXP ARM S32
1032:6x Gen 4.0
1003:3 x Gen3.0
974:3 x Gen3.0
945:1 x Gen3.0
916:3 x Gen2.0
887:2 x Gen2.0
858:2 x Gen2.0
829:1 x Gen2.0
800:2 x Gen2.0
771:2 x Gen2.0
742:1 x Gen2.0
516:-based and
2807:Categories
2778:PowerQUICC
2609:PowerQUICC
2424:DragonBall
2332:see also:
2290:Processors
2157:PowerQUICC
2016:2009-10-23
1964:2011-07-12
1755:2018-04-23
1730:2018-04-23
1667:References
1651:PowerQUICC
1629:data plane
1620:data plane
1513:e6500 core
1509:AMP Series
1503:AMP Series
1170:TDM engine
1087:asymmetric
1079:hypervisor
1077:through a
707:Frequency
603:Layerscape
534:PowerQUICC
528:(formerly
348:PWRficient
2724:16/32-bit
2671:6801/6803
2619:PPC e6500
2604:PPC e5500
2439:-variants
2222:Spin-offs
2208:Signetics
2127:GreenChip
2032:6wind.com
1954:Freescale
1898:24 August
1877:24 August
1836:24 August
1812:24 August
1704:24 August
1635:Freescale
1436:P5 series
1424:Freescale
1413:Virtutech
1409:Freescale
1369:L3 caches
1357:switching
1349:P4 series
1295:L3 caches
1283:switching
1279:P3 series
1193:P2 series
1102:P1 series
1083:symmetric
1044:100 Gbps
636:Cortex A7
613:Cortex A7
581:Cortex A9
577:Cortex A7
530:Freescale
518:Power ISA
401:Power.org
396:Blue Gene
67:Power ISA
2747:DSP568xx
2595:PPC 74xx
2590:PPC e500
2571:PPC e200
2419:ColdFire
2234:Nexperia
2182:Nexperia
2177:TriMedia
2109:Products
1645:See also
1492:Qonverge
1486:Qonverge
1180:L2 cache
1166:L2 cache
1064:L1 cache
1053:P Series
1023:LX2160A
994:LS1088A
965:LS1046A
907:LS1043A
878:LS1028A
849:LS1024A
820:LS1022A
791:LS1021A
762:LS1020A
733:LS1012A
725:DCE/PME
695:Security
656:datapath
324:Espresso
317:Broadway
2585:PPC 7xx
2576:PPC 6xx
2562:PowerPC
2499:MC88110
2494:MC88100
2476:68LC060
2471:68EC060
2466:68LC040
2461:68EC040
2456:68EC030
2451:68EC020
2446:68EC000
2229:Ampleon
2147:NXP LPC
1517:AltiVec
1447:CoreNet
1381:USB 2.0
1361:routing
1307:USB 2.0
1287:routing
1249:RapidIO
1213:USB 2.0
1149:lanes,
1119:USB 2.0
936:LA1575
721:Engine
713:SerDES
701:Device
631:cores.
542:PowerPC
421:AltiVec
278:RAD5500
267:RAD6000
251:(2010)
206:Power10
127:Qorivva
63:PowerPC
34:updated
2773:MPC5xx
2768:M·CORE
2761:32-bit
2740:24-bit
2715:68HC16
2710:68HC12
2705:68HC11
2688:68HC08
2683:68HC05
2564:family
2516:(FPUs)
2361:68HC16
2356:68HC12
2351:68HC11
2346:68HC08
2341:68HC05
2142:Ne-XVP
2137:MIFARE
1786:"News"
1750:Forbes
1440:64-bit
1400:regexp
1365:e500mc
1291:e500mc
1241:SerDes
1147:SerDes
704:Cores
645:FinFET
538:e500mc
294:(1996)
292:series
273:RAD750
201:POWER9
196:POWER8
191:POWER7
186:POWER6
180:POWER5
173:POWER4
166:POWER3
159:POWER2
152:POWER1
65:, and
2731:683xx
2665:8-bit
2614:QorIQ
2552:68851
2547:68451
2540:(MMU)
2528:68882
2523:68881
2486:88000
2414:68060
2409:68040
2404:68030
2399:68020
2394:68012
2389:68010
2384:68008
2379:68000
2305:14500
2162:QorIQ
1918:6WIND
1872:(PDF)
1855:(PDF)
1831:(PDF)
1807:(PDF)
1699:(PDF)
1639:6WIND
1602:T1022
1596:T1020
1590:T1042
1584:T1040
1568:T2081
1564:T2080
1548:T4080
1542:T4160
1536:T4240
1479:P5040
1473:P5021
1467:P5020
1461:P5010
1443:e5500
1396:P4080
1373:DUART
1336:P3041
1331:P2041
1326:P2040
1299:DUART
1266:P2020
1260:P2010
1253:SGMII
1176:P1020
1162:P1011
1155:SGMII
716:SATA
710:PCIe
591:and
566:28 nm
556:45 nm
524:from
479:QorIQ
358:Xenon
342:Titan
333:Other
310:Gekko
145:Power
122:QorIQ
110:e6500
105:e5500
59:POWER
2788:i.MX
2698:RS08
2679:6804
2675:6802
2637:i.MX
2599:e600
2580:e300
2328:6809
2323:6800
2132:i.MX
1900:2023
1879:2023
1838:2023
1814:2023
1706:2023
1566:and
1520:SIMD
1434:The
1379:and
1377:GPIO
1359:and
1347:The
1305:and
1303:GPIO
1285:and
1277:The
1245:PCIe
1221:DDR3
1219:and
1217:DDR2
1203:and
1191:The
1153:and
1151:PCIe
1127:DDR3
1125:and
1123:DDR2
1109:and
1100:The
1085:and
1041:Yes
1038:Yes
1018:Yes
1012:Yes
1009:Yes
983:Yes
980:Yes
954:Yes
951:Yes
931:Yes
925:Yes
922:Yes
896:Yes
893:Yes
870:Yes
867:Yes
864:Yes
838:Yes
815:Yes
809:Yes
806:Yes
786:Yes
780:Yes
777:Yes
751:Yes
748:Yes
627:and
609:DPAA
416:CHRP
411:PReP
406:PAPR
391:RISC
364:X704
353:Cell
290:RS64
236:74xx
100:e600
95:e500
90:e300
85:e200
2693:S08
2629:ARM
2437:68k
1496:DSP
1237:MMC
1229:DMA
1225:ECC
1143:MMC
1135:DMA
1131:ECC
835:No
629:A72
625:A53
621:A15
597:ISA
593:A72
589:A53
585:A15
546:ARM
514:ARM
493:ɔːr
257:A2O
254:A2I
243:970
230:7xx
225:4xx
219:6xx
137:IBM
2809::
1973:^
1952:.
1934:.
1916:.
1788:.
1777:^
1748:.
1723:.
1674:^
1575:T1
1555:T2
1527:T4
1430:P5
1375:,
1343:P4
1301:,
1273:P3
1233:SD
1197:°C
1187:P2
1139:SD
1096:P1
1060:kB
1015:-
989:-
986:-
960:-
957:-
928:-
902:-
899:-
873:-
844:-
841:-
812:-
783:-
757:-
754:-
623:,
619:,
617:A9
615:,
587:,
583:,
579:,
505:uː
496:aɪ
432:,
249:A2
61:,
2597:/
2578:/
2268:e
2261:t
2254:v
2093:e
2086:t
2079:v
2019:.
1967:.
1920:.
1902:.
1881:.
1857:.
1840:.
1816:.
1792:.
1758:.
1733:.
1708:.
1235:/
1141:/
570:W
508:/
502:j
499:k
490:k
487:ˈ
484:/
459:e
452:t
445:v
46:)
42:(
36:.
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