437:(MDMX) extension, MIPS V was designed to improve the performance of 3D graphics transformations. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from Silicon Graphics. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications. MIPS V implementations were never introduced. On May 12, 1997, Silicon Graphics announced the H1 ("Beast") and H2 ("Capitan") microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999. The H1 and H2 projects were later combined and eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 (1999) was based on MIPS V and retains all of its features as an optional Coprocessor 1 (FPU) feature called Paired-Single.
761:. Jumps have two versions: absolute and register-indirect. Absolute jumps ("Jump" and "Jump and Link") compute the address to which control is transferred by shifting the 26-bit instr_index left by two bits and concatenating the 28-bit result with the four high-order bits of the address of the instruction in the branch delay slot. Register-indirect jumps transfer control to the instruction at the address sourced from a GPR (rs). The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. Branch and jump instructions that link (except for "Jump and Link Register") save the return address to GPR 31. The "Jump and Link Register" instruction permits the return address to be saved to any writable GPR.
750:
instructions. For multiplication, the high- and low-order halves of the 64-bit product is written to HI and LO (respectively). For division, the quotient is written to LO and the remainder to HI. To access the results, a pair of instructions (Move from HI and Move from LO) is provided to copy the contents of HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. Another pair of instructions (Move to HI or Move to LO) copies the contents of a GPR to HI and LO. These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO.
2195:, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K, 34K, 74K, 1004K, 1074K, M14K, microAptiv, interAptiv, proAptiv 32-bit cores and the MIPS 64-bit 5K range of cores. These models are created and maintained by Imperas and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free for non-commercial usage, and are easy to use. OVPsim is developed and maintained by
1193:) manager block. This enables two prioritization mechanisms that determine the flow of information across the bus. The first mechanism allows the user to prioritize one thread over another. The second mechanism is used to allocate a specified ratio of the cycles to specific threads over time. The combined use of both mechanisms allows effective allocation of bandwidth to the set of threads, and better control of latencies. In real-time systems, system-level determinism is very critical, and the QoS block facilitates improvement of the predictability of a system. Hardware designers of advanced systems may replace the standard QoS block provided by MIPS Technologies with one that is specifically tuned for their application.
1079:(among others); and implemented as an extension to the MIPS I, II, an III architectures. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture. It is supported by hardware and software development tools from MIPS Technologies and other providers. MIPS16e is an improved version of MIPS16 first supported by MIPS32 and MIPS64 Release 1. MIPS16e2 is an improved version of MIPS16 that is supported by MIPS32 and MIPS64 (up to Release 5). Release 6 replaced it with microMIPS.
720:
instructions source the base from the contents of a GPR (rs) and write the result to another GPR (rt). Store instructions source the base from the contents of a GPR (rs) and the store data from another GPR (rt). All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. To support efficient unaligned memory accesses, there are load/store word instructions suffixed by "left" or "right". All load instructions are followed by a
854:
the requirement for instructions to use even-numbered register only was removed. This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit (FPU) in a MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility. The only new floating-point instructions added were those to copy doublewords between the CPU and FPU convert single- and double-precision floating-point numbers into doubleword integers and vice versa.
994:
used 32-bit instructions that are encoded as 16-bit instructions. This allows programs to intermix 16- and 32-bit instructions without having to switch modes. microMIPS was introduced alongside of MIPS32/64 Release 3, and each subsequent release of MIPS32/64 has a corresponding microMIPS32/64 version. A processor may implement microMIPS32/64 or both microMIPS32/64 and its corresponding MIPS32/64 subset. Starting with MIPS32/64 Release 6, support for MIPS16e ended, and microMIPS is the only form of code compression in MIPS.
757:. Unless the branch delay slot is filled by an instruction performing useful work, an nop is substituted. MIPS I branch instructions compare the contents of a GPR (rs) against zero or another GPR (rt) as signed integers and branch if the specified condition is true. Control is transferred to the address computed by shifting the 16-bit offset left by two bits, sign-extending the 18-bit result, and adding the 32-bit sign-extended result to the sum of the program counter (instruction address) and 8
2009:
520:
285:
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422:(1998). The R10000, fabricated and sold by NEC Electronics and Toshiba, and its derivatives were used by NEC, Pyramid Technology, Silicon Graphics, and Tandem Computers (among others) in workstations, servers, and supercomputers. The R5000 and R7000 found use in high-end embedded systems, personal computers, and low-end workstations and servers. A derivative of the R5000 from Toshiba, the R5900, was used in Sony Computer Entertainment's
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additional logic to implement in MIPS processor cores. Revision 2 of the ASE was introduced in the second half of 2006. This revision adds extra instructions to the original ASE, but is otherwise backwards-compatible with it. Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for a particular relevance to some key algorithm. Its main novel features (vs original MIPS32):
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meet IEEE 754 accuracy requirements (respectively). The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place (it is implementation defined). These instructions serve applications where instruction latency is more important than accuracy.
728:
instructions for addition and subtraction have two variants: by default, an exception is signaled if the result overflows; instructions with the "unsigned" suffix do not signal an exception. The overflow check interprets the result as a 32-bit two's complement integer. MIPS I has instructions to perform
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The DSP ASE is an optional extension to the MIPS32/MIPS64 Release 2 and newer instruction sets which can be used to accelerate a large range of "media" computations—particularly audio and video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal
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MIPS I has two instructions for software to signal an exception: System Call and
Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can
993:
The microMIPS32/64 architectures are supersets of the MIPS32 and MIPS64 architectures (respectively) designed to replace the MIPS16e ASE. A disadvantage of MIPS16e is that it requires a mode switch before any of its 16-bit instructions can be processed. microMIPS adds versions of the most-frequently
887:
MIPS V added a new data type, the Paired Single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on
878:
MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings (it is implementation-defined), to exceed or
853:
MIPS III removed the
Coprocessor 3 (CP3) support instructions, and reused its opcodes for the new doubleword instructions. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The floating general registers (FGRs) were extended to 64 bits and
768:
MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions (moves/copies and loads/stores were
440:
When MIPS Technologies was spun-out of
Silicon Graphics in 1998, it refocused on the embedded market. Through MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem, and the architecture definition was changed to define a 32-bit and
1294:
A few attempts have been made to replace O32 with a 32-bit ABI that resembles N32 more. A 1995 conference came up with MIPS EABI, for which the 32-bit version was quite similar. EABI inspired MIPS Technologies to propose a more radical "NUBI" ABI additionally reuse argument registers for the return
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Each multi-threaded MIPS core can support up to two VPEs (Virtual
Processing Elements) which share a single pipeline as well as other hardware resources. However, since each VPE includes a complete copy of the processor state as seen by the software system, each VPE appears as a complete standalone
719:
is supported: base + displacement. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either sign-extended or zero-extended to 32 bits. The load instructions suffixed by "unsigned" perform zero extension; otherwise sign extension is performed. Load
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In
December 2018, Wave Computing, the new owner of the MIPS architecture, announced that MIPS ISA would be open-sourced in a program dubbed the MIPS Open initiative. The program was intended to open up access to the most recent versions of both the 32-bit and 64-bit designs making them available
838:
The R instruction format's inability to specify the full shift distance for 64-bit shifts (its 5-bit shift amount field is too narrow to specify the shift distance for doublewords) required MIPS III to provide three 64-bit versions of each MIPS I shift instruction. The first version is a 64-bit
796:
versions that executed the instruction in the branch delay slot only if the branch is taken. These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot. Doubleword load and store instructions for COP1–3 were added. Consistent with other
634:
Instructions are divided into three types: R (register), I (immediate), and J (jump). Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a
1188:
Linux operating system. For more fine-grained thread processing applications, each VPE is capable of supporting up to nine TCs allocated across two VPEs. The TCs share a common execution unit but each has its own program counter and core register files so that each can handle a thread from the
870:
MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. FP comparison and branch instructions were
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instructions write one or zero to the destination register if the specified relation is true or false. These instructions source their operands from two GPRs or one GPR and a 16-bit immediate (which is sign-extended to 32 bits), and write the result to a third GPR. By default, the operands are
409:
microprocessor chipset (1994). The design of the R8000 began at
Silicon Graphics, Inc. and it was only used in high-end workstations and servers for scientific and technical applications where high performance on large floating-point workloads was important. Later implementations were the MIPS
227:
There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is
800:
The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision
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memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition,
727:
MIPS I has instructions to perform addition and subtraction. These instructions source their operands from two GPRs (rs and rt), and write the result to a third GPR (rd). Alternatively, addition can source one of the operands from a 16-bit immediate (which is sign-extended to 32 bits). The
749:
MIPS I has instructions for signed and unsigned integer multiplication and division. These instructions source their operands from two GPRs and write their results to a pair of 32-bit registers called HI and LO, since they may execute separately from (and concurrently with) the other CPU
745:
MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR (rt), and the result is written to another GPR (rd). The shift distance is obtained from either a GPR (rs) or a 5-bit "shift amount" (the "sa" field).
826:
instructions were added. Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined was
732:
logical AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write the result to a third GPR. The AND, OR, and XOR instructions can alternatively source one of the operands from a 16-bit immediate (which is zero-extended to 32 bits). The Set on
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for use in education. EduMIPS64 is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU.
374:(ARC) standard, which aimed to establish MIPS as the dominant personal computing platform. ARC found little success in personal computers, but the R4000 (and the R4400 derivative) were widely used in workstation and server computers, especially by its largest user,
1259:. The ABI took shape in 1990 and was last updated in 1994. This perceived slowness, along with an antique floating-point model with only 16 registers, has encouraged the proliferation of many other calling conventions. It is only defined for 32-bit MIPS, but
3087:
499:
In March 2021, Wave
Computing announced that the development of the MIPS architecture has ceased. The company has joined the RISC-V foundation and future processor designs will be based on the RISC-V architecture. In spite of this, some licensees such as
862:
MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed
647:-31- format (bits) -0-
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The existing integer multiplication and multiply-accumulate instructions, which deliver results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of
1266:
For 64-bit, the N64 ABI by
Silicon Graphics is most commonly used. The most important improvement is that eight registers are now available for argument passing; it also increases the number of floating-point registers to 32. There is also an
724:. The instruction in the load delay slot cannot use the data loaded by the load instruction. The load delay slot can be filled with an instruction that is not dependent on the load; a nop is substituted if such an instruction cannot be found.
1975:
Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, $ s-registers must be saved to the stack by a procedure that needs to use them, and
867:(base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes).
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2305:
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floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the
Floating Point Control and Status Register.
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Includes atomic bit set/clear instructions which enables bits within an I/O register that are normally used to monitor or control external peripheral functions to be modified without interruption, ensuring the action is performed
365:
microprocessor (1991) was the first MIPS III implementation. It was designed for use in personal, workstation, and server computers. MIPS Computer
Systems aggressively promoted the MIPS architecture and R4000, establishing the
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list. These uses were complemented by embedded applications at first, but during the 1990s, MIPS became a major presence in the embedded processor market, and by the 2000s, most MIPS processors were for these applications.
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interpreted as signed integers. The variants of these instructions that are suffixed with "unsigned" interpret the operands as unsigned integers (even those that source an operand from the sign-extended 16-bit immediate).
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redefined so they could specify which condition bit was written or read (respectively); and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for
3077:
1988:
is changed automatically by any normal function call (ones that use jal), and $ t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).
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register. This is automatically set with the use of the JAL (jump and link) or JALR (jump and link register) instructions. The function prologue of a (non-leaf) MIPS subroutine pushes the return address (in
741:
The Load Immediate Upper instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with the Or Immediate instruction to load a 32-bit immediate into a register.
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available to pass arguments. Space on the stack is reserved in case the callee needs to save its arguments, but the registers are not stored there by the caller. The return value is stored in register
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this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data. It was the first instruction set to exploit floating-point SIMD with existing resources.
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have since joined them. MIPS32/MIPS64 Release 5 was announced on December 6, 2012. According to the Product Marketing Director at MIPS, Release 4 was skipped because the number four is perceived as
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instructions were added. A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given
2265:
The Creator simulator is portable and allows the user to learn various assembly languages of different processors (Creator has examples with an implementation of MIPS32 and RISC-V instructions).
1047:
Supports speculative pre-fetching of the interrupt vector address. Reduces the number of interrupt service cycles by overlapping memory accesses with pipeline flushes and exception prioritization
2790:
1044:
Interrupt Chaining – supports the service of pending interrupts without the need to exit the initial interrupt routine, saving the cycles required to store and restore multiple active interrupts
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a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999. MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V.
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unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))
2217:
WebMIPS is a browser-based MIPS simulator with visual representation of a generic, pipelined processor. This simulator is quite useful for register tracking during step by step execution.
355:
were MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32 was introduced in 1999.
1390:) are reserved for kernel use and should not be used by applications since these registers can be changed at any time by the kernel due to interrupts, context switches or other events.
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was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps.
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the shift amount field's value so that constant shift distances of 32–63 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR.
3552:
2380:
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554:(CP0/1/2/3). In MIPS terminology, CP0 is the System Control Coprocessor (an essential part of the processor that is implementation-defined in MIPS I–V), CP1 is an optional
228:
MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.
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software. The MIPS MT architecture also allows the allocation of processor cycles to threads, and sets the relative thread priorities with an optional Quality of Service (
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privilege level in between the existing kernel and user privilege levels. This feature only affected the implementation-defined System Control Processor (Coprocessor 0).
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subtraction, multiplication, division, and shift operations on them, and to move doubleword between the GPRs and HI/LO registers. For shared-memory multiprocessing, the
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The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries.
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QtMips provides a simple 5-stage pipeline visualization as well as cache principle visualization for basic computer architectures courses. It is available both as a
3899:
900:, and other features from the R4000 and R5000 families of 64-bit processors. The first release of MIPS64 adds a MIPS32 mode to run 32-bit code. The MUL and MADD (
172:
processor has been on the market for more than 20 years and as such cannot be subject to patent claims. Therefore, the R16000 and older processors are fully open.
1104:
instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).
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WepSIM is a browser-based simulator where a subset of MIPS instructions are micro-programmed. This simulator is very useful in order to learn how a CPU works (
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378:. Other uses of the R4000 included high-end embedded systems and supercomputers. MIPS III was eventually implemented by a number of embedded microprocessors.
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and is very fast (hundreds of million of instructions per second), and built to handle multicore homogeneous and heterogeneous architectures and systems.
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version of the original shift instructions, used to specify constant shift distances of 0–31 bits. The second version is similar to the first, but adds 32
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563:
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3155:
1002:
The base MIPS32 and MIPS64 architectures can be supplemented with a number of optional architectural extensions, which are collectively referred to as
558:(FPU) and CP2/3 are optional implementation-defined coprocessors (MIPS III removed CP3 and reused its opcodes for other purposes). For example, in the
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controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs.
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courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as
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In March 2019, one version of the architecture was made available under a royalty-free license, but later that year the program was shut down again.
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software. It is supported by MIPS32 only, since smart cards do not require the capabilities of MIPS64 processors. Few smart cards use SmartMIPS.
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By the late 2010s, MIPS machines were still commonly used in embedded markets, including automotive, wireless router, LTE modems (mainly via
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are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast,
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2813:"Latest Release of MIPS Architecture Includes Virtualization and SIMD Key Functionality for Enabling Next Generation of MIPS-Based Products"
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5387:
1314:) is optional and in practice rarely used except when the stack allocation in a function is determined at runtime, for example, by calling
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On both O32 and N32/N64 the stack grows downwards, but the N32/N64 ABIs require 64-bit alignment for all stack entries. The frame pointer (
1067:, announced on October 21, 1996, alongside its first implementation, the LSI Logic TinyRISC processor. MIPS16 was subsequently licensed by
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3312:"Silicon Graphics Introduces Compact MIPS RISC Microprocessor Code For High Performance at a Low Cost" (Press release). October 21, 1996.
1094:
Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").
3078:"Chinese chipmaker Loongson wins case over rights to MIPS architecture - company's new CPU architecture heavily resembles existing MIPS"
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full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),
7017:
3855:
3681:
615:. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers,
329:
microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985. When MIPS II was introduced,
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2559:
2255:
2196:
623:, are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers.
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419:
268:. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to
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and is accessed by using the mfhw (move from hardware) instruction. At least one vendor is known to store this information in the
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R-type is short for register-type. R-type instructions use three registers as operands: two as sources, and one as a destination.
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386:(1993) and its derivatives was widely used in high-end embedded systems and low-end workstations and servers. MIPS Technologies'
1992:
The userspace calling convention of position-independent code on Linux additionally requires that when a function is called the
1275:. Both run under the 64-bit mode of the CPU. The N32 and N64 ABIs pass the first eight arguments to a function in the registers
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255:
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Enhancements for microcontroller applications. The MCU ASE (application-specific extension) has been developed to extend the
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Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).
239:
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projects. These emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them.
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904:) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were
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Automated Interrupt Epilogue – restores the system state previously stored in the stack for returning from the interrupt.
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register must contain the address of that function. This convention dates back to the System V ABI supplement for MIPS.
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Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (August 2, 2022).
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microprocessor (1989) was the first MIPS II implementation. Designed for servers, the R6000 was fabricated and sold by
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Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (May 29, 2024).
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247:
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instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
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Software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware
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Automated Interrupt Prologue – adds hardware to save and update system status before the interrupt handling routine
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MIPS II removed the load delay slot and added several sets of instructions. For shared-memory multiprocessing, the
390:(1994), was designed for embedded systems, laptop, and personal computers. A derivative, the R4300i, fabricated by
213:
94:
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In the mid- to late-1990s, it was estimated that one in three RISC microprocessors produced was a MIPS processor.
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3417:
3180:
1283:; subsequent arguments are passed on the stack. The return value (or a pointer to it) is stored in the registers
1166:
Emerging data mining, feature extraction, image and video processing, and human-computer interaction applications
943:
instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
2910:
2885:"Wave Computing® Launches the MIPS Open Initiative To Accelerate Innovation for the Renowned MIPS® Architecture"
6561:
6280:
5715:
4176:
4004:
3526:
2246:
Commercial simulators are available especially for the embedded use of MIPS processors, for example Wind River
2087:. Originally, MIPS was designed for general-purpose computing. During the 1980s and 1990s, MIPS processors for
367:
3582:
1006:(ASEs). These ASEs provide features that improve the efficiency and performance of certain workloads, such as
6735:
6583:
6556:
6417:
6031:
5992:
5849:
4308:
3499:
2100:
1924:
1633:
958:
instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.
348:
4257:
4076:
3148:
2210:
MARS is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's
978:
integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
7172:
6934:
6410:
6371:
6026:
6021:
5955:
5767:
4345:
2967:
2762:"Silicon Graphics Previews New High-Performance MIPS Microprocessor Roadmap" (Press release). May 12, 1997.
2728:
2331:
1363:
For multi-threaded code, the thread local storage pointer is typically stored in special hardware register
1240:
1029:
Supports up to 256 interrupts in EIC (External Interrupt Controller) mode and eight hardware interrupt pins
466:
217:
493:
without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents.
6799:
6496:
6194:
5891:
5373:
3677:
442:
5365:
2820:
2020:
531:
296:
7611:
7596:
7449:
7096:
6513:
6004:
5972:
5742:
5730:
5710:
4192:
2884:
3710:
3348:
2202:
There is a freely available MIPS32 simulator (earlier versions simulated only the R2000/R3000) called
715:
MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Only one
7540:
7503:
7493:
5881:
3762:
3736:
2783:"MIPS Technologies, Inc. Enhances Architecture to Support Growing Need for IP Re-Use and Integration"
1185:
1007:
905:
121:
797:
memory access instructions, these loads and stores required the doubleword to be naturally aligned.
7555:
6962:
6898:
6875:
6725:
6687:
6523:
6473:
6468:
5945:
5839:
5747:
4700:
4560:
2703:"Silicon Graphics Introduces Enhanced MIPS Architecture to Lead the Interactive Digital Revolution"
2642:
2581:
2525:
184:
45:
17:
3468:
3378:
2612:
1160:
Accelerates compute-intensive applications in conjunction with leveraging generic compiler support
772:
Single precision is denoted by the .s suffix, while double precision is denoted by the .d suffix.
7508:
7291:
7185:
7149:
7066:
7050:
6892:
6681:
6640:
6628:
6491:
6405:
6326:
6091:
5752:
5695:
5450:
3637:
1260:
588:
580:
371:
251:
952:
multiply and divide instructions redefined so that they use a single register for their result).
949:
bit-reversal and byte-alignment instructions (previously only available with the DSP extension).
7314:
7286:
7196:
7161:
6910:
6904:
6886:
6620:
6614:
6518:
6422:
6313:
6252:
6114:
5757:
5624:
5186:
3218:
2844:
2710:
2706:
1123:
Efficient vector parallel arithmetic operations on integer, fixed-point and floating-point data
1072:
326:
946:
PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
7488:
7397:
7143:
6855:
6673:
6432:
6400:
6358:
6270:
6071:
5886:
5876:
5866:
5856:
5826:
5809:
5674:
5349:
5342:
5024:
4811:
4437:
2736:
2146:
2104:
1200:
559:
482:
399:
379:
358:
340:
322:
261:
89:
2191:
Open Virtual Platforms (OVP) includes the freely available for non-commercial use simulator
1216:
Multimedia application accelerations that were common in the 1990s on RISC and CISC systems.
7518:
7454:
7040:
6762:
6652:
6599:
6131:
5844:
5700:
5682:
5571:
5455:
5036:
4982:
4929:
4864:
4557:
3707:"OVP: Fast Simulation, Free Open Source Models. Virtual Platforms for software development"
3670:
2336:
2177:
2154:
897:
810:
454:
2551:
1107:
SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.
351:, but was a commercial failure. During the mid-1990s, many new 32-bit MIPS processors for
8:
7565:
7550:
7370:
7221:
7203:
7167:
7155:
6809:
6756:
6533:
6449:
6331:
6186:
6081:
5940:
5489:
4952:
3924:
3327:(2nd ed.). San Francisco, California: Morgan Kaufmann Publishers. pp. 425–427.
2080:
1120:
32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements
635:
16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.
555:
2469:
2058:
Please help update this article to reflect recent events or newly available information.
940:
index jump instructions with no delay slot designed to support large absolute addresses.
402:, were among the highest volume users of MIPS architecture processors in the mid-1990s.
7422:
7414:
7266:
7241:
7045:
6920:
6444:
6385:
6265:
5997:
5725:
5515:
4051:
3118:
2859:"Wave Computing Extends AI Lead by Targeting Edge of Cloud Through Acquisition of MIPS"
2135:
2112:
2096:
2084:
1190:
872:
177:
2491:
7375:
7342:
7258:
7190:
7091:
7081:
7071:
7002:
6997:
6992:
6915:
6844:
6750:
6710:
6343:
6293:
6243:
6219:
6041:
6036:
5918:
5834:
5144:
5121:
4668:
4595:
4518:
4453:
4377:
4234:
4215:
4196:
4162:
4055:
4041:
4025:
3975:
3955:
3849:
3397:
3328:
3189:
3122:
3082:
2816:
2441:
2370:
2088:
1064:
754:
729:
316:
221:
41:
4032:. 2021 XLVII Latin American Computing Conference (CLEI) (in Spanish). pp. 1–9.
3784:
3671:"A FPGA Implementation of a MIPS RISC Processor for Computer Architecture Education"
2994:"Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning"
7545:
7478:
7464:
7319:
7226:
7180:
6987:
6982:
6977:
6972:
6967:
6957:
6827:
6794:
6705:
6700:
6609:
6461:
6456:
6439:
6427:
6366:
5930:
5908:
5794:
5772:
5690:
5600:
4838:
4721:
4645:
4180:
4037:
4033:
3965:
3958:"CREATOR: An Educational Integrated Development Environment for RISC-V Programming"
3638:"System V Application Binary Interface MIPS RISC Processor Supplement, 3rd Edition"
3578:
3114:
2128:
2124:
1964:
1673:
1138:
Complete set of vector-level compare and branch instructions with no condition flag
375:
1271:
version called N32, which uses 32-bit pointers for smaller code, analogous to the
126:
Compare and branch, with a 1 instruction delay after the branching condition check
7459:
7444:
7392:
7296:
7271:
7108:
7101:
6952:
6947:
6942:
6881:
6789:
6779:
6501:
6336:
6288:
6051:
5935:
5903:
5804:
5799:
5720:
5445:
4959:
4540:
4295:
4283:
4270:
4261:
4185:
4027:
3814:
2937:
2341:
2309:
2298:
2287:
2276:
2221:
2076:
1224:
Additional instructions for improving the performance of 3D graphics applications
1068:
935:
full set of branch-and-link which compare a register against zero (e.g. BGTZALC).
864:
721:
716:
592:
470:
462:
391:
352:
111:
3970:
3290:
1291:. In both the N32 and N64 ABIs all registers are considered to be 64-bits wide.
1059:
MIPS16 is an Application-Specific Extension for MIPS I through to V designed by
7570:
7404:
7387:
7380:
7276:
7133:
6870:
6784:
6715:
6298:
6260:
6209:
6204:
6199:
5913:
5737:
5610:
5581:
5437:
5045:
2672:
1356:). The O32 ABI is the same except the calling function is required to save the
1236:
The O32 ABI is the most commonly-used ABI, owing to its status as the original
1203:
and MIPS Technologies to improve performance and reduce memory consumption for
423:
236:
194:
104:
4276:
3957:
3453:
2183:). They have mostly faded out of the personal, server, and application space.
1371:
register which is normally reserved for kernel use, but this is not standard.
1295:
value. MIPS EABI is supported by GCC but not LLVM, and neither supports NUBI.
765:
contain operating environment-specific information for the exception handler.
433:
Announced on October 21, 1996, at the Microprocessor Forum 1996 alongside the
250:
instruction set using the 64-bit floating-point registers, MIPS16e which adds
7590:
7365:
7281:
6321:
6303:
6096:
5789:
5469:
5421:
5416:
5059:
5042:
4001:"CREATOR: Simulador didáctico y genérico para la programación en ensamblador"
3979:
2786:
2529:
2158:
2150:
1944:
1653:
1322:
1233:
MIPS has had several calling conventions, especially on the 32-bit platform.
612:
566:(GTE), which accelerates the processing of geometry in 3D computer graphics.
427:
6224:
926:
unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,
7575:
7513:
7329:
7306:
7118:
6839:
5777:
5558:
5465:
4445:
3829:
1321:
For N32 and N64, the return address is typically stored 8 bytes before the
985:
Reorganized the instruction encoding, freeing space for future expansions.
901:
507:
In January 2024, Loongson won a case over rights to use MIPS architecture.
7360:
7324:
7035:
7007:
6865:
6720:
5643:
5576:
5553:
5395:
5030:
4467:
4460:
2139:
2092:
551:
486:
395:
4093:
2008:
896:
The first release of MIPS32, based on MIPS II, added conditional moves,
519:
284:
7246:
7236:
7231:
7213:
7113:
7086:
6348:
6181:
6151:
5871:
5595:
5591:
5528:
5316:
5306:
5296:
4300:
1204:
1145:
638:
The following are the three formats used for the core instruction set:
603:
MIPS I has thirty-two 32-bit general-purpose registers (GPR). Register
131:
5321:
5311:
5301:
5291:
3615:
3349:"Using the GNU Compiler Collection (GCC): MIPS DSP Built-in Functions"
169:
7337:
7334:
7076:
6146:
6124:
5586:
5548:
5532:
5484:
2250:(MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000, Broadcom/Netlogic ec4400,
1157:
Pre-defined scalable extensions for chips with more gates/transistors
1060:
1018:
265:
136:
5614:
5244:
4000:
7352:
6171:
5632:
5479:
5460:
5440:
5256:
5232:
5219:
5092:
5076:
4885:
4851:
4740:
4658:
4138:
2839:
2173:
2116:
1237:
501:
478:
3869:
3503:
504:
continue with new extension of MIPS-compatible ISAs on their own.
6161:
6119:
5628:
5619:
5520:
5411:
5268:
5201:
4906:
4577:
4254:
4187:
Computer Organization and Design: The Hardware/Software Interface
2157:
used MIPS processors. MIPS processors also used to be popular in
1272:
1219:
1199:
SmartMIPS is an Application-Specific Extension (ASE) designed by
1135:
Conversions between integer, floating-point, and fixed-point data
1076:
458:
457:) each obtained licenses for MIPS64 as soon as it was announced.
446:
232:
158:
4029:
A new generic simulator for the teaching of assembly programming
2258:(all MIPS32 and MIPS64 cores), VaST Systems (R3000, R4000), and
6176:
6141:
6106:
5605:
5525:
5505:
5496:
5333:
5286:
4992:
4939:
4795:
4771:
4679:
4142:
4097:
3873:
2259:
2251:
2247:
2236:
2192:
2162:
1243:
for MIPS. It is strictly stack-based, with only four registers
814:
474:
450:
411:
269:
55:
3109:
Harris, David Money; Harris, Sarah L. (2013). "Architecture".
3102:
1298:
For all of O32 and N32/N64, the return address is stored in a
1151:
IEEE Standard for Floating-Point Arithmetic 754-2008 compliant
831:. In MIPS III it sign-extends words to 64 bits. To complement
607:
is hardwired to zero and writes to it are discarded. Register
6634:
6166:
6136:
5566:
5563:
5510:
5281:
5276:
5251:
5239:
5227:
5209:
5191:
4487:
2229:
2225:
1268:
1115:
Instruction set extensions designed to accelerate multimedia.
415:
406:
387:
383:
362:
344:
2161:
during the 1990s, but all such systems have dropped off the
975:
integer overflow trapping instructions with 16-bit immediate
254:
to make programs take up less room, and MIPS MT, which adds
7498:
6646:
6566:
6156:
5500:
5492:
3020:"Wave Computing and MIPS emerge from chapter 11 bankruptcy"
2610:
2240:
2203:
2143:
1210:
434:
405:
The first MIPS IV implementation was the MIPS Technologies
321:
The first version of the MIPS architecture was designed by
243:
154:
3706:
2911:"MIPS Processor ISA To Be Open-Sourced In 2019 - Phoronix"
2052:
Parts of this article (those related to 2010s) need to be
6086:
6076:
3758:
3732:
2321:
2108:
929:
conditional branch on zero/non-zero with a 21-bit offset,
3251:"MIPS® Coherence Protocol Specification, Revision 01.01"
3149:"APPLICATION NOTE MIPS R4000 Synchronization Primitives"
3283:"MIPS – Market-leading RISC CPU IP processor solutions"
1328:
For the N32 and N64 ABIs, a function must preserve the
753:
All MIPS I control flow instructions are followed by a
231:
The MIPS architecture has several optional extensions.
2636:
2634:
3662:
1758:
values for function returns and expression evaluation
1467:
values for function returns and expression evaluation
919:
MIPS32/MIPS64 Release 6 in 2014 added the following:
550:
MIPS is a modular architecture supporting up to four
2777:
2775:
2773:
2771:
2769:
2235:
More advanced free emulators are available from the
2631:
210:
Microprocessor without Interlocked Pipelined Stages
4184:
3870:QtMips - MIPS CPU simulator for education purposes
1154:Element precise floating-point exception signaling
997:
3785:"MARS MIPS simulator - Missouri State University"
2968:"MIPS R6 Architecture Now Available for Open Use"
2766:
2722:
2720:
2613:"ECS 142 (Compilers) References & Tools page"
7588:
3888:Graphical CPU Simulator with Cache Visualization
3811:"WebMIPS - MIPS CPU PIPLINED SIMULATION On Line"
3466:
3047:"Loongson Rips MIPS: Uses Old Code for New CPUs"
5067:
4368:
2239:(formerly known as the mips64emul project) and
972:instructions (deprecated in previous releases).
3936:National and Kapodistrian University of Athens
2717:
2431:
2429:
2427:
2425:
2423:
2421:
2419:
2417:
2262:(the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).
2099:computers were used by many companies such as
1685:Registers for N32 and N64 calling conventions
1035:Pre-fetching of the interrupt exception vector
398:game console. The Nintendo 64, along with the
220:(ISA) developed by MIPS Computer Systems, now
5659:
5381:
4316:
3444:
3442:
3143:
3141:
1177:Hardware supported virtualization technology.
1141:Vector (1D) and array (2D) shuffle operations
923:a new family of branches with no delay slot:
595:, all instructions operate on the registers.
3524:
3108:
813:extension of MIPS II that added support for
6664:Computer performance by orders of magnitude
3543:
2414:
2403:
2401:
2224:and as a downloadable program for Windows,
1263:has created a 64-bit variation called O64.
246:(MaDMaX) which is a more extensive integer
5673:
5666:
5652:
5388:
5374:
4323:
4309:
3923:
3439:
3371:"Instruction Set Architecture - LinuxMIPS"
3138:
3969:
3075:
2729:"Digital, MIPS Add Multimedia Extensions"
2359:
2176:), and microcontrollers (for example the
1360:register instead of the called function.
1287:; a second return value may be stored in
1255:; a second return value may be stored in
1129:Rounding and saturation options available
908:. For the purpose of cache control, both
835:, a version that zero-extends was added.
4330:
4289:MIPS Instructions - MIPS Instruction Set
4083:from the original on September 29, 2021.
3558:from the original on September 30, 2020.
3418:"MIPS32 Instruction Set Quick Reference"
3391:
3385:
3322:
3111:Digital Design and Computer Architecture
2435:
2398:
1132:Full precision multiply and multiply-add
962:Removed infrequently used instructions:
337:to distinguish it from the new version.
4007:from the original on September 29, 2021
3076:Connatser, Matthew (January 19, 2024).
2935:
2835:"MIPS skips Release 4 amid bidding war"
2726:
2411:(Revision 3.2), MIPS Technologies, Inc.
1026:Separate priority and vector generation
14:
7607:Computer-related introductions in 1985
7589:
5017:
3905:from the original on November 19, 2020
3854:: CS1 maint: archived copy as title (
3650:from the original on November 12, 2020
3533:from the original on October 25, 2020.
3263:from the original on September 4, 2018
3231:from the original on December 15, 2023
3199:from the original on November 27, 2022
3161:from the original on December 27, 2023
3044:
2865:from the original on November 25, 2020
2640:
2386:from the original on September 4, 2019
1228:
1144:Typed load and store instructions for
629:
414:(1996) and the Quantum Effect Devices
5647:
5369:
4304:
4157:Farquhar, Erin; Philip Bunce (1994).
3836:from the original on October 10, 2011
3527:"The MIPS Register Usage Conventions"
3427:from the original on January 25, 2022
3090:from the original on January 19, 2024
3057:from the original on January 25, 2022
2793:from the original on December 1, 2018
2727:Gwennap, Linley (November 18, 1996).
2592:from the original on October 26, 2020
2562:from the original on January 16, 2021
2502:from the original on February 2, 2020
1394:Registers for O32 calling convention
1169:High-performance scientific computing
1126:Operations on absolute value operands
1032:Provides 16-bit vector offset address
252:compression to the instruction stream
6635:Floating-point operations per second
4351:List of MIPS architecture processors
3896:Czech Technical University in Prague
3884:
3359:from the original on April 20, 2017.
2936:Yoshida, Junko (December 17, 2018).
2327:List of MIPS architecture processors
2038:
2003:
1082:MIPS Digital Signal Processing (DSP)
514:
279:
3687:from the original on April 15, 2012
3410:
2974:from the original on August 4, 2020
2843:. December 10, 2012. Archived from
2751:from the original on July 20, 2011.
2653:from the original on March 21, 2021
2619:from the original on March 21, 2011
2440:. Morgan Kaufmann Publishers, Inc.
710:
24:
4150:
4120:from the original on July 25, 2022
3739:from the original on June 14, 2012
3467:Eric Christopher (June 11, 2003).
3119:10.1016/b978-0-12-394424-5.00006-9
3000:from the original on March 7, 2021
2917:from the original on March 6, 2021
2891:from the original on July 28, 2021
2819:. December 6, 2012. Archived from
25:
7623:
4267:MIPS Architecture history diagram
4248:
4077:"CREATOR Web with MIPS32 example"
3713:from the original on June 8, 2012
3668:
3045:Shilov, Anton (August 25, 2021).
3026:from the original on May 13, 2021
2948:from the original on July 5, 2022
2683:from the original on May 17, 2023
2643:"Wait, What? MIPS Becomes RISC-V"
2611:University of California, Davis.
2407:Price, Charles (September 1995).
7561:Semiconductor device fabrication
5397:Reduced instruction set computer
3791:from the original on May 2, 2012
3765:from the original on May 7, 2012
3480:from the original on May 7, 2020
3022:(Press release). March 1, 2021.
2709:October 21, 1996. Archived from
2363:Computer Organization and Design
2212:Computer Organization and Design
2043:
2007:
1968:
1890:
1716:
1677:
1599:
1425:
891:
518:
370:(ACE) consortium to advance its
283:
214:reduced instruction set computer
7536:History of general-purpose CPUs
5763:Nondeterministic Turing machine
4391:LS3A4000/LS3A4000-I(LS3A4000-i)
4388:LS3A3000/LS3A3000-I(LS3A3000-i)
4382:LS3A1000/LS3A1000-I(LS3A1000-i)
4132:
4102:
4087:
4069:
4019:
3993:
3949:
3917:
3878:
3863:
3803:
3777:
3751:
3725:
3699:
3630:
3600:
3562:
3537:
3518:
3492:
3460:
3363:
3341:
3316:
3305:
3275:
3243:
3211:
3173:
3069:
3038:
3012:
2986:
2960:
2929:
2903:
2877:
2851:
2827:
2805:
2755:
2695:
2665:
1336:registers, the global pointer (
1325:although this may be optional.
1004:application-specific extensions
998:Application-specific extensions
562:video game console, CP2 is the
5716:Deterministic finite automaton
4233:. Morgan Kaufmann Publishers.
4214:. Morgan Kaufmann Publishers.
4161:. Morgan Kaufmann Publishers.
4110:"WepSIM with a MIPS32 example"
4038:10.1109/CLEI53233.2021.9640144
3113:. Elsevier. pp. 294–369.
2647:Electronic Engineering Journal
2604:
2574:
2544:
2514:
2484:
2454:
2353:
585:register-register architecture
564:Geometry Transformation Engine
368:Advanced Computing Environment
242:dedicated to common 3D tasks,
224:, based in the United States.
13:
1:
6507:Simultaneous and heterogenous
4003:(in Spanish). July 23, 2021.
3787:. Courses.missouristate.edu.
2641:Turley, Jim (March 8, 2021).
2369:. Elsevier. pp. 4.16–4.
2347:
2186:
2101:Digital Equipment Corporation
824:Store Conditional Double Word
435:MIPS Digital Media Extensions
349:Bipolar Integrated Technology
218:instruction set architectures
7191:Integrated memory controller
7173:Translation lookaside buffer
6372:Memory dependence prediction
5815:Random-access stored program
5768:Probabilistic Turing machine
4346:MIPS architecture processors
2332:MIPS architecture processors
2075:MIPS processors are used in
1211:MIPS Digital Media eXtension
1112:MIPS SIMD architecture (MSA)
988:
916:instructions were prepared.
694:
675:
650:
598:
27:Instruction set architecture
7:
6647:Synaptic updates per second
3971:10.1109/ACCESS.2024.3406935
3678:New Mexico State University
2315:
804:
569:
471:Raza Microelectronics, Inc.
68:; 39 years ago
10:
7628:
7051:Heterogeneous architecture
5973:Orthogonal instruction set
5743:Alternating Turing machine
5731:Quantum cellular automaton
4273: (archived 2013-05-30)
4229:Sweetman, Dominic (2007).
4210:Sweetman, Dominic (1999).
4193:Morgan Kaufmann Publishers
4159:MIPS Programmer's Handbook
3735:. Imperas. March 3, 2008.
3392:Sweetman, Dominic (2007).
3323:Sweetman, Dominic (2007).
2436:Sweetman, Dominic (1999).
906:cache control instructions
857:
775:
314:
275:
84:MIPS32/64 Release 6 (2014)
7541:Microprocessor chronology
7528:
7504:Dynamic frequency scaling
7477:
7413:
7351:
7305:
7257:
7212:
7132:
7059:
7028:
6933:
6854:
6818:
6772:
6672:
6659:Cache performance metrics
6598:
6532:
6482:
6393:
6384:
6357:
6312:
6279:
6251:
6242:
6062:
5965:
5954:
5825:
5681:
5541:
5430:
5404:
5332:
5267:
5218:
5200:
5177:
5168:
5135:
5112:
5105:
5058:
5010:
4973:
4920:
4899:
4878:
4831:
4788:
4714:
4693:
4638:
4631:
4586:
4569:
4550:
4539:
4509:
4428:
4419:
4359:
4336:
4231:See MIPS Run, 2nd edition
3929:"The basics of QtMips-v3"
3546:"MIPS Calling Convention"
3469:"mips eabi documentation"
3394:See MIPS Run, 2nd edition
3219:"MIPS instruction set R5"
3188:(Revision 3.2 ed.).
2360:Patterson, David (2014).
1352:) and the frame pointer (
1008:digital signal processing
882:
782:Synchronize Shared Memory
703:
690:
646:
574:
510:
235:which is a simple set of
193:
183:
176:
164:
150:
142:
130:
120:
110:
100:
88:
80:
62:
51:
37:
7556:Hardware security module
6899:Digital signal processor
6876:Graphics processing unit
6688:Graphics processing unit
4479:Velocity Micro T301 Cruz
4476:Velocity Micro T103 Cruz
3571:MIPSpro N32 ABI Handbook
2526:Imagination Technologies
2297:August 20, 2022, at the
489:in many Asian cultures.
46:Imagination Technologies
7602:Advanced RISC Computing
7509:Dynamic voltage scaling
7292:Memory address register
7186:Branch target predictor
7150:Address generation unit
6893:Physics processing unit
6682:Central processing unit
6641:Transactions per second
6629:Instructions per second
6552:Array processing (SIMT)
5696:Stored-program computer
3827:(online demonstration)
3182:MIPS IV Instruction Set
2938:"MIPS Goes Open Source"
2409:MIPS IV Instruction Set
1999:
820:Load Linked Double Word
589:load/store instructions
581:load/store architecture
372:Advanced RISC Computing
7315:Hardwired control unit
7197:Memory management unit
7162:Memory management unit
6911:Secure cryptoprocessor
6905:Tensor Processing Unit
6887:Vision processing unit
6621:Cycles per instruction
6615:Instructions per cycle
6562:Associative processing
6253:Instruction pipelining
5675:Processor technologies
5077:Loongson-based systems
5027:MIPS R3000A-compatible
4949:Alchemy Semiconductor
4294:April 7, 2022, at the
4282:March 5, 2022, at the
3608:"PIC code – LinuxMIPS"
2707:Silicon Graphics, Inc.
2308:July 26, 2022, at the
2286:July 26, 2022, at the
2275:July 26, 2022, at the
1888:reserved for OS kernel
1699:Callee must preserve?
1618:Yes (except PIC code)
1597:reserved for OS kernel
1408:Callee must preserve?
1344:), the stack pointer (
1148:-independent operation
1073:Philips Semiconductors
966:some conditional moves
790:Store Conditional Word
7398:Sum-addressed decoder
7144:Arithmetic logic unit
6271:Classic RISC pipeline
6225:Epiphany architecture
6072:Motorola 68000 series
4705:88E6318 "Link Street"
4260:May 11, 2022, at the
3618:on September 21, 2018
3525:Karen Miller (2006).
2996:. November 15, 2019.
2887:. December 17, 2018.
2823:on December 13, 2012.
2737:Microprocessor Report
2582:"MIPS Multithreading"
2492:"MIPS64 Architecture"
2462:"MIPS32 Architecture"
2105:MIPS Computer Systems
1201:Gemplus International
898:prefetch instructions
483:Ingenic Semiconductor
380:Quantum Effect Design
359:MIPS Computer Systems
341:MIPS Computer Systems
323:MIPS Computer Systems
262:Computer architecture
7519:Performance per watt
7097:replacement policies
6763:Package on a package
6653:Performance per watt
6557:Pipelined processing
6327:Tomasulo's algorithm
6132:Clipper architecture
5988:Application-specific
5701:Finite-state machine
5399:(RISC) architectures
5037:PlayStation Portable
4558:Microchip Technology
4331:MIPS microprocessors
4277:Online MIPS emulator
3927:(December 6, 2020).
3925:Gizopoulos, Dimitris
3885:KoÄŤĂ, Karel (2018).
3817:on December 31, 2012
3588:on December 17, 2021
3544:Hal Perkins (2006).
3256:. p. 26,25,57.
2673:"The MIPS Processor"
2337:Pipeline (computing)
2178:Microchip Technology
2155:PlayStation Portable
2081:residential gateways
1180:MIPS multi-threading
1098:multiply-accumulate.
811:backwards-compatible
426:, which powered its
7551:Digital electronics
7204:Instruction decoder
7156:Floating-point unit
6810:Soft microprocessor
6757:System in a package
6332:Reservation station
5862:Transport-triggered
4488:Ainol Novo7 Paladin
4385:LS3A2000/LS3A1500-I
4094:CREATOR source code
3456:on August 26, 2018.
3396:. Morgan Kaufmann.
2136:video game consoles
1732:assembler temporary
1686:
1441:assembler temporary
1395:
1229:Calling conventions
1174:MIPS virtualization
873:partial predication
630:Instruction formats
556:floating-point unit
479:Loongson Technology
453:(later acquired by
34:
7423:Integrated circuit
7267:Processor register
6921:Baseband processor
6266:Operand forwarding
5726:Cellular automaton
4177:Patterson, David A
4139:WepSIM source code
3612:www.linux-mips.org
3450:"MIPS ABI History"
3381:on April 20, 2017.
3375:www.linux-mips.org
3192:. September 1995.
2970:. March 28, 2019.
2847:on April 17, 2014.
2532:on January 3, 2014
2113:Pyramid Technology
2019:. You can help by
1784:function arguments
1684:
1493:function arguments
1393:
587:); except for the
530:. You can help by
394:, was used in the
295:. You can help by
32:
7612:MIPS Technologies
7597:MIPS architecture
7584:
7583:
7473:
7472:
7092:Instruction cache
7082:Scratchpad memory
6929:
6928:
6916:Network processor
6845:Network on a chip
6800:Ultra-low-voltage
6751:Multi-chip module
6594:
6593:
6380:
6379:
6367:Branch prediction
6344:Register renaming
6238:
6237:
6220:VISC architecture
6042:Quantum computing
6037:VISC architecture
5919:Secondary storage
5835:Microarchitecture
5795:Register machines
5641:
5640:
5363:
5362:
5359:
5358:
5164:
5163:
5145:Loongson 1 Series
5126:LS1E0300/LS1E1000
5122:Loongson 1 Series
5101:
5100:
5054:
5053:
5006:
5005:
4671:/Infineon/Lantiq
4669:Texas Instruments
4627:
4626:
4596:Loongson 1 Series
4576:ATI/AMD/Broadcom
4544:(embedded device)
4535:
4534:
4526:LS2K1000/LS2K2000
4519:Loongson 2 Series
4454:Skytone Alpha-400
4415:
4414:
4378:Loongson 3 Series
4341:MIPS architecture
4240:978-0-12-088421-6
4047:978-1-6654-9503-5
3669:Rubio, Victor P.
3643:. pp. 3–12.
3403:978-0-12088-421-6
3334:978-0-12-088421-6
3224:. p. 59-62.
3190:MIPS Technologies
2861:. June 15, 2018.
2817:MIPS Technologies
2815:(Press release).
2785:(Press release).
2705:(Press release).
2472:on March 21, 2020
2376:978-0-12-407726-3
2073:
2072:
2037:
2036:
1973:
1972:
1836:saved temporaries
1682:
1681:
1545:saved temporaries
1065:MIPS Technologies
846:MIPS III added a
755:branch delay slot
708:
707:
583:(also known as a
548:
547:
317:MIPS Technologies
313:
312:
240:SIMD instructions
222:MIPS Technologies
212:) is a family of
203:
202:
42:MIPS Technologies
16:(Redirected from
7619:
7546:Processor design
7438:Power management
7320:Instruction unit
7181:Branch predictor
7130:
7129:
6828:System on a chip
6770:
6769:
6610:Transistor count
6534:Flynn's taxonomy
6391:
6390:
6249:
6248:
6052:Addressing modes
5963:
5962:
5909:Memory hierarchy
5773:Hypercomputation
5691:Abstract machine
5668:
5661:
5654:
5645:
5644:
5390:
5383:
5376:
5367:
5366:
5175:
5174:
5110:
5109:
5065:
5064:
5015:
5014:
4839:Qualcomm Atheros
4722:Qualcomm Atheros
4646:Qualcomm Atheros
4636:
4635:
4548:
4547:
4541:Microcontrollers
4426:
4425:
4366:
4365:
4325:
4318:
4311:
4302:
4301:
4244:
4225:
4206:
4190:
4181:John L. Hennessy
4172:
4145:
4136:
4130:
4129:
4127:
4125:
4106:
4100:
4091:
4085:
4084:
4073:
4067:
4066:
4064:
4062:
4023:
4017:
4016:
4014:
4012:
3997:
3991:
3990:
3988:
3986:
3973:
3953:
3947:
3946:
3944:
3942:
3933:
3921:
3915:
3914:
3912:
3910:
3904:
3893:
3882:
3876:
3867:
3861:
3859:
3853:
3845:
3843:
3841:
3826:
3824:
3822:
3813:. Archived from
3807:
3801:
3800:
3798:
3796:
3781:
3775:
3774:
3772:
3770:
3755:
3749:
3748:
3746:
3744:
3729:
3723:
3722:
3720:
3718:
3709:. Ovpworld.org.
3703:
3697:
3696:
3694:
3692:
3686:
3675:
3666:
3660:
3659:
3657:
3655:
3649:
3642:
3634:
3628:
3627:
3625:
3623:
3614:. Archived from
3604:
3598:
3597:
3595:
3593:
3587:
3581:. Archived from
3579:Silicon Graphics
3576:
3566:
3560:
3559:
3557:
3550:
3541:
3535:
3534:
3522:
3516:
3515:
3513:
3511:
3506:on July 29, 2021
3502:. Archived from
3496:
3490:
3489:
3487:
3485:
3476:(Mailing list).
3464:
3458:
3457:
3452:. Archived from
3446:
3437:
3436:
3434:
3432:
3426:
3414:
3408:
3407:
3389:
3383:
3382:
3377:. Archived from
3367:
3361:
3360:
3345:
3339:
3338:
3320:
3314:
3313:
3309:
3303:
3302:
3300:
3298:
3293:on March 9, 2016
3289:. Archived from
3279:
3273:
3272:
3270:
3268:
3262:
3255:
3247:
3241:
3240:
3238:
3236:
3230:
3223:
3215:
3209:
3208:
3206:
3204:
3198:
3187:
3177:
3171:
3170:
3168:
3166:
3160:
3153:
3145:
3136:
3135:
3106:
3100:
3099:
3097:
3095:
3073:
3067:
3066:
3064:
3062:
3042:
3036:
3035:
3033:
3031:
3016:
3010:
3009:
3007:
3005:
2990:
2984:
2983:
2981:
2979:
2964:
2958:
2957:
2955:
2953:
2933:
2927:
2926:
2924:
2922:
2907:
2901:
2900:
2898:
2896:
2881:
2875:
2874:
2872:
2870:
2855:
2849:
2848:
2831:
2825:
2824:
2809:
2803:
2802:
2800:
2798:
2779:
2764:
2763:
2759:
2753:
2752:
2750:
2733:
2724:
2715:
2714:
2713:on June 6, 1997.
2699:
2693:
2692:
2690:
2688:
2669:
2663:
2662:
2660:
2658:
2638:
2629:
2628:
2626:
2624:
2608:
2602:
2601:
2599:
2597:
2578:
2572:
2571:
2569:
2567:
2548:
2542:
2541:
2539:
2537:
2528:. Archived from
2518:
2512:
2511:
2509:
2507:
2488:
2482:
2481:
2479:
2477:
2468:. Archived from
2458:
2452:
2451:
2433:
2412:
2405:
2396:
2395:
2393:
2391:
2385:
2368:
2357:
2270:microprogramming
2129:Tandem Computers
2125:Silicon Graphics
2077:embedded systems
2068:
2065:
2059:
2047:
2046:
2039:
2032:
2029:
2011:
2004:
1995:
1987:
1983:
1979:
1961:
1956:
1941:
1936:
1921:
1916:
1903:
1898:
1885:
1881:
1876:
1872:
1859:
1855:
1850:
1846:
1833:
1829:
1824:
1820:
1807:
1803:
1798:
1794:
1781:
1777:
1772:
1768:
1755:
1751:
1746:
1742:
1729:
1724:
1711:
1706:
1687:
1683:
1670:
1665:
1650:
1645:
1630:
1625:
1612:
1607:
1594:
1590:
1585:
1581:
1568:
1564:
1559:
1555:
1542:
1538:
1533:
1529:
1516:
1512:
1507:
1503:
1490:
1486:
1481:
1477:
1464:
1460:
1455:
1451:
1438:
1433:
1420:
1415:
1396:
1392:
1389:
1385:
1381:
1377:
1370:
1366:
1359:
1355:
1351:
1347:
1343:
1339:
1335:
1331:
1317:
1313:
1307:) to the stack.
1306:
1301:
1290:
1286:
1282:
1278:
1258:
1254:
1250:
1246:
1184:processor to an
915:
911:
786:Load Linked Word
711:CPU instructions
641:
640:
610:
606:
543:
540:
522:
515:
376:Silicon Graphics
353:embedded systems
308:
305:
287:
280:
76:
74:
69:
35:
31:
21:
7627:
7626:
7622:
7621:
7620:
7618:
7617:
7616:
7587:
7586:
7585:
7580:
7566:Tick–tock model
7524:
7480:
7469:
7409:
7393:Address decoder
7347:
7301:
7297:Program counter
7272:Status register
7253:
7208:
7168:Load–store unit
7135:
7128:
7055:
7024:
6925:
6882:Image processor
6857:
6850:
6820:
6814:
6790:Microcontroller
6780:Embedded system
6768:
6668:
6601:
6590:
6528:
6478:
6376:
6353:
6337:Re-order buffer
6308:
6289:Data dependency
6275:
6234:
6064:
6058:
5957:
5956:Instruction set
5950:
5936:Multiprocessing
5904:Cache hierarchy
5897:Register/memory
5821:
5721:Queue automaton
5677:
5672:
5642:
5637:
5537:
5426:
5400:
5394:
5364:
5355:
5328:
5263:
5214:
5196:
5170:
5160:
5152:LS1F04/LS1F0300
5137:
5131:
5114:
5097:
5069:
5050:
5002:
4975:
4969:
4960:RMI Corporation
4922:
4916:
4895:
4874:
4827:
4822:Fusiv Vx185/183
4816:Fusiv Vx175/173
4784:
4710:
4689:
4623:
4588:
4582:
4565:
4543:
4531:
4511:
4505:
4430:
4421:
4411:
4370:
4361:
4355:
4332:
4329:
4296:Wayback Machine
4284:Wayback Machine
4271:Wayback Machine
4262:Wayback Machine
4255:MIPS Processors
4251:
4241:
4228:
4222:
4209:
4203:
4175:
4169:
4156:
4153:
4151:Further reading
4148:
4137:
4133:
4123:
4121:
4108:
4107:
4103:
4092:
4088:
4075:
4074:
4070:
4060:
4058:
4048:
4024:
4020:
4010:
4008:
3999:
3998:
3994:
3984:
3982:
3954:
3950:
3940:
3938:
3931:
3922:
3918:
3908:
3906:
3902:
3891:
3883:
3879:
3868:
3864:
3847:
3846:
3839:
3837:
3830:"Archived copy"
3828:
3820:
3818:
3809:
3808:
3804:
3794:
3792:
3783:
3782:
3778:
3768:
3766:
3761:. Edumips.org.
3757:
3756:
3752:
3742:
3740:
3731:
3730:
3726:
3716:
3714:
3705:
3704:
3700:
3690:
3688:
3684:
3673:
3667:
3663:
3653:
3651:
3647:
3640:
3636:
3635:
3631:
3621:
3619:
3606:
3605:
3601:
3591:
3589:
3585:
3574:
3568:
3567:
3563:
3555:
3548:
3542:
3538:
3523:
3519:
3509:
3507:
3498:
3497:
3493:
3483:
3481:
3465:
3461:
3448:
3447:
3440:
3430:
3428:
3424:
3416:
3415:
3411:
3404:
3390:
3386:
3369:
3368:
3364:
3347:
3346:
3342:
3335:
3321:
3317:
3311:
3310:
3306:
3296:
3294:
3281:
3280:
3276:
3266:
3264:
3260:
3253:
3249:
3248:
3244:
3234:
3232:
3228:
3221:
3217:
3216:
3212:
3202:
3200:
3196:
3185:
3179:
3178:
3174:
3164:
3162:
3158:
3151:
3147:
3146:
3139:
3129:
3107:
3103:
3093:
3091:
3074:
3070:
3060:
3058:
3043:
3039:
3029:
3027:
3018:
3017:
3013:
3003:
3001:
2992:
2991:
2987:
2977:
2975:
2966:
2965:
2961:
2951:
2949:
2934:
2930:
2920:
2918:
2909:
2908:
2904:
2894:
2892:
2883:
2882:
2878:
2868:
2866:
2857:
2856:
2852:
2833:
2832:
2828:
2811:
2810:
2806:
2796:
2794:
2789:. May 3, 1999.
2781:
2780:
2767:
2761:
2760:
2756:
2748:
2731:
2725:
2718:
2701:
2700:
2696:
2686:
2684:
2671:
2670:
2666:
2656:
2654:
2639:
2632:
2622:
2620:
2609:
2605:
2595:
2593:
2580:
2579:
2575:
2565:
2563:
2550:
2549:
2545:
2535:
2533:
2520:
2519:
2515:
2505:
2503:
2490:
2489:
2485:
2475:
2473:
2460:
2459:
2455:
2448:
2434:
2415:
2406:
2399:
2389:
2387:
2383:
2377:
2366:
2358:
2354:
2350:
2342:Prpl Foundation
2318:
2310:Wayback Machine
2299:Wayback Machine
2288:Wayback Machine
2277:Wayback Machine
2222:web application
2189:
2121:Siemens Nixdorf
2069:
2063:
2060:
2057:
2048:
2044:
2033:
2027:
2024:
2017:needs expansion
2002:
1993:
1985:
1981:
1977:
1959:
1954:
1939:
1934:
1919:
1914:
1901:
1896:
1883:
1879:
1874:
1870:
1857:
1853:
1848:
1844:
1831:
1827:
1822:
1818:
1805:
1801:
1796:
1792:
1779:
1775:
1770:
1766:
1753:
1749:
1744:
1740:
1727:
1722:
1709:
1704:
1668:
1663:
1648:
1643:
1628:
1623:
1610:
1605:
1592:
1588:
1583:
1579:
1566:
1562:
1557:
1553:
1540:
1536:
1531:
1527:
1514:
1510:
1505:
1501:
1488:
1484:
1479:
1475:
1462:
1458:
1453:
1449:
1436:
1431:
1418:
1413:
1387:
1383:
1379:
1375:
1368:
1364:
1357:
1353:
1349:
1345:
1341:
1337:
1333:
1329:
1315:
1311:
1304:
1299:
1288:
1284:
1280:
1276:
1256:
1252:
1248:
1244:
1231:
1069:NEC Electronics
1000:
991:
913:
909:
894:
885:
865:addressing mode
860:
842:
807:
778:
769:not affected).
760:
722:load delay slot
717:addressing mode
713:
691:immediate (16)
632:
608:
604:
601:
591:used to access
577:
572:
544:
538:
535:
528:needs expansion
513:
392:NEC Electronics
319:
309:
303:
300:
293:needs expansion
278:
185:General-purpose
72:
70:
67:
28:
23:
22:
15:
12:
11:
5:
7625:
7615:
7614:
7609:
7604:
7599:
7582:
7581:
7579:
7578:
7573:
7571:Pin grid array
7568:
7563:
7558:
7553:
7548:
7543:
7538:
7532:
7530:
7526:
7525:
7523:
7522:
7516:
7511:
7506:
7501:
7496:
7491:
7485:
7483:
7475:
7474:
7471:
7470:
7468:
7467:
7462:
7457:
7452:
7447:
7442:
7441:
7440:
7435:
7430:
7419:
7417:
7411:
7410:
7408:
7407:
7405:Barrel shifter
7402:
7401:
7400:
7395:
7388:Binary decoder
7385:
7384:
7383:
7373:
7368:
7363:
7357:
7355:
7349:
7348:
7346:
7345:
7340:
7332:
7327:
7322:
7317:
7311:
7309:
7303:
7302:
7300:
7299:
7294:
7289:
7284:
7279:
7277:Stack register
7274:
7269:
7263:
7261:
7255:
7254:
7252:
7251:
7250:
7249:
7244:
7234:
7229:
7224:
7218:
7216:
7210:
7209:
7207:
7206:
7201:
7200:
7199:
7188:
7183:
7178:
7177:
7176:
7170:
7159:
7153:
7147:
7140:
7138:
7127:
7126:
7121:
7116:
7111:
7106:
7105:
7104:
7099:
7094:
7089:
7084:
7079:
7069:
7063:
7061:
7057:
7056:
7054:
7053:
7048:
7043:
7038:
7032:
7030:
7026:
7025:
7023:
7022:
7021:
7020:
7010:
7005:
7000:
6995:
6990:
6985:
6980:
6975:
6970:
6965:
6960:
6955:
6950:
6945:
6939:
6937:
6931:
6930:
6927:
6926:
6924:
6923:
6918:
6913:
6908:
6902:
6896:
6890:
6884:
6879:
6873:
6871:AI accelerator
6868:
6862:
6860:
6852:
6851:
6849:
6848:
6842:
6837:
6834:Multiprocessor
6831:
6824:
6822:
6816:
6815:
6813:
6812:
6807:
6802:
6797:
6792:
6787:
6785:Microprocessor
6782:
6776:
6774:
6773:By application
6767:
6766:
6760:
6754:
6748:
6743:
6738:
6733:
6728:
6723:
6718:
6716:Tile processor
6713:
6708:
6703:
6698:
6697:
6696:
6685:
6678:
6676:
6670:
6669:
6667:
6666:
6661:
6656:
6650:
6644:
6638:
6632:
6626:
6625:
6624:
6612:
6606:
6604:
6596:
6595:
6592:
6591:
6589:
6588:
6587:
6586:
6576:
6571:
6570:
6569:
6564:
6559:
6554:
6544:
6538:
6536:
6530:
6529:
6527:
6526:
6521:
6516:
6511:
6510:
6509:
6504:
6502:Hyperthreading
6494:
6488:
6486:
6484:Multithreading
6480:
6479:
6477:
6476:
6471:
6466:
6465:
6464:
6454:
6453:
6452:
6447:
6437:
6436:
6435:
6430:
6420:
6415:
6414:
6413:
6408:
6397:
6395:
6388:
6382:
6381:
6378:
6377:
6375:
6374:
6369:
6363:
6361:
6355:
6354:
6352:
6351:
6346:
6341:
6340:
6339:
6334:
6324:
6318:
6316:
6310:
6309:
6307:
6306:
6301:
6296:
6291:
6285:
6283:
6277:
6276:
6274:
6273:
6268:
6263:
6261:Pipeline stall
6257:
6255:
6246:
6240:
6239:
6236:
6235:
6233:
6232:
6227:
6222:
6217:
6214:
6213:
6212:
6210:z/Architecture
6207:
6202:
6197:
6189:
6184:
6179:
6174:
6169:
6164:
6159:
6154:
6149:
6144:
6139:
6134:
6129:
6128:
6127:
6122:
6117:
6109:
6104:
6099:
6094:
6089:
6084:
6079:
6074:
6068:
6066:
6060:
6059:
6057:
6056:
6055:
6054:
6044:
6039:
6034:
6029:
6024:
6019:
6014:
6013:
6012:
6002:
6001:
6000:
5990:
5985:
5980:
5975:
5969:
5967:
5960:
5952:
5951:
5949:
5948:
5943:
5938:
5933:
5928:
5923:
5922:
5921:
5916:
5914:Virtual memory
5906:
5901:
5900:
5899:
5894:
5889:
5884:
5874:
5869:
5864:
5859:
5854:
5853:
5852:
5842:
5837:
5831:
5829:
5823:
5822:
5820:
5819:
5818:
5817:
5812:
5807:
5802:
5792:
5787:
5782:
5781:
5780:
5775:
5770:
5765:
5760:
5755:
5750:
5745:
5738:Turing machine
5735:
5734:
5733:
5728:
5723:
5718:
5713:
5708:
5698:
5693:
5687:
5685:
5679:
5678:
5671:
5670:
5663:
5656:
5648:
5639:
5638:
5636:
5635:
5622:
5617:
5611:Motorola 88000
5608:
5603:
5598:
5589:
5584:
5579:
5574:
5569:
5561:
5556:
5551:
5545:
5543:
5539:
5538:
5536:
5535:
5523:
5518:
5513:
5508:
5503:
5487:
5482:
5477:
5472:
5463:
5458:
5453:
5448:
5443:
5438:Analog Devices
5434:
5432:
5428:
5427:
5425:
5424:
5419:
5414:
5408:
5406:
5402:
5401:
5393:
5392:
5385:
5378:
5370:
5361:
5360:
5357:
5356:
5354:
5353:
5346:
5338:
5336:
5330:
5329:
5327:
5326:
5325:
5324:
5319:
5314:
5309:
5304:
5299:
5294:
5284:
5279:
5273:
5271:
5265:
5264:
5262:
5261:
5260:
5259:
5249:
5248:
5247:
5237:
5236:
5235:
5224:
5222:
5216:
5215:
5213:
5212:
5206:
5204:
5198:
5197:
5195:
5194:
5189:
5183:
5181:
5172:
5166:
5165:
5162:
5161:
5159:
5158:
5157:
5156:
5153:
5150:
5141:
5139:
5133:
5132:
5130:
5129:
5128:
5127:
5118:
5116:
5107:
5103:
5102:
5099:
5098:
5096:
5095:
5090:
5089:
5088:
5085:
5082:
5073:
5071:
5062:
5056:
5055:
5052:
5051:
5049:
5048:
5046:Emotion Engine
5040:
5034:
5028:
5021:
5019:
5012:
5008:
5007:
5004:
5003:
5001:
5000:
4999:
4998:
4990:
4989:
4988:
4979:
4977:
4971:
4970:
4968:
4967:
4966:
4965:
4957:
4956:
4955:
4947:
4946:
4945:
4937:
4936:
4935:
4926:
4924:
4918:
4917:
4915:
4914:
4913:
4912:
4903:
4901:
4897:
4896:
4894:
4893:
4892:
4891:
4882:
4880:
4876:
4875:
4873:
4872:
4871:
4870:
4862:
4861:
4860:
4857:
4849:
4848:
4847:
4844:
4835:
4833:
4829:
4828:
4826:
4825:
4824:
4823:
4820:
4817:
4809:
4808:
4807:
4804:
4801:
4792:
4790:
4786:
4785:
4783:
4782:
4781:
4780:
4777:
4769:
4768:
4767:
4764:
4761:
4758:
4755:
4752:
4749:
4746:
4738:
4737:
4736:
4733:
4730:
4727:
4718:
4716:
4712:
4711:
4709:
4708:
4707:
4706:
4697:
4695:
4691:
4690:
4688:
4687:
4686:
4685:
4677:
4676:
4675:
4666:
4665:
4664:
4656:
4655:
4654:
4651:
4642:
4640:
4633:
4629:
4628:
4625:
4624:
4622:
4621:
4620:
4619:
4616:
4613:
4610:
4607:
4604:
4601:
4592:
4590:
4584:
4583:
4581:
4580:
4573:
4571:
4567:
4566:
4564:
4563:
4554:
4552:
4545:
4537:
4536:
4533:
4532:
4530:
4529:
4528:
4527:
4524:
4515:
4513:
4507:
4506:
4504:
4503:
4502:
4501:
4498:
4497:
4496:
4493:
4490:
4482:
4481:
4480:
4477:
4471:
4464:
4457:
4450:
4449:
4448:
4438:Ingenic XBurst
4434:
4432:
4423:
4417:
4416:
4413:
4412:
4410:
4409:
4408:
4407:
4404:
4401:
4398:
4395:
4392:
4389:
4386:
4383:
4374:
4372:
4363:
4357:
4356:
4354:
4353:
4348:
4343:
4337:
4334:
4333:
4328:
4327:
4320:
4313:
4305:
4299:
4298:
4286:
4274:
4264:
4250:
4249:External links
4247:
4246:
4245:
4239:
4226:
4220:
4207:
4201:
4173:
4167:
4152:
4149:
4147:
4146:
4131:
4101:
4086:
4068:
4046:
4018:
3992:
3948:
3916:
3877:
3862:
3802:
3776:
3750:
3724:
3698:
3661:
3629:
3599:
3561:
3536:
3517:
3491:
3459:
3438:
3409:
3402:
3384:
3362:
3340:
3333:
3315:
3304:
3274:
3242:
3210:
3172:
3137:
3127:
3101:
3083:Tom's Hardware
3068:
3051:Tom's Hardware
3037:
3011:
2985:
2959:
2928:
2902:
2876:
2850:
2826:
2804:
2765:
2754:
2716:
2694:
2664:
2630:
2603:
2573:
2543:
2513:
2483:
2453:
2446:
2413:
2397:
2375:
2351:
2349:
2346:
2345:
2344:
2339:
2334:
2329:
2324:
2317:
2314:
2188:
2185:
2159:supercomputers
2134:Historically,
2071:
2070:
2051:
2049:
2042:
2035:
2034:
2014:
2012:
2001:
1998:
1971:
1970:
1967:
1965:return address
1962:
1957:
1951:
1950:
1947:
1942:
1937:
1931:
1930:
1927:
1922:
1917:
1911:
1910:
1907:
1906:global pointer
1904:
1899:
1893:
1892:
1889:
1886:
1877:
1867:
1866:
1863:
1860:
1851:
1841:
1840:
1837:
1834:
1825:
1815:
1814:
1811:
1808:
1799:
1789:
1788:
1785:
1782:
1773:
1763:
1762:
1759:
1756:
1747:
1737:
1736:
1733:
1730:
1725:
1719:
1718:
1715:
1712:
1707:
1701:
1700:
1697:
1694:
1691:
1680:
1679:
1676:
1674:return address
1671:
1666:
1660:
1659:
1656:
1651:
1646:
1640:
1639:
1636:
1631:
1626:
1620:
1619:
1616:
1615:global pointer
1613:
1608:
1602:
1601:
1598:
1595:
1586:
1576:
1575:
1572:
1569:
1560:
1550:
1549:
1546:
1543:
1534:
1524:
1523:
1520:
1517:
1508:
1498:
1497:
1494:
1491:
1482:
1472:
1471:
1468:
1465:
1456:
1446:
1445:
1442:
1439:
1434:
1428:
1427:
1424:
1421:
1416:
1410:
1409:
1406:
1403:
1400:
1230:
1227:
1226:
1225:
1222:
1217:
1214:
1208:
1197:
1194:
1181:
1178:
1175:
1171:
1170:
1167:
1164:
1161:
1158:
1155:
1152:
1149:
1142:
1139:
1136:
1133:
1130:
1127:
1124:
1121:
1117:
1116:
1113:
1109:
1108:
1105:
1099:
1095:
1092:
1088:
1087:
1083:
1080:
1057:
1053:
1052:
1048:
1045:
1042:
1039:
1036:
1033:
1030:
1027:
1023:
1022:
1015:
999:
996:
990:
987:
983:
982:
979:
976:
973:
967:
960:
959:
956:
953:
950:
947:
944:
941:
938:
937:
936:
933:
930:
927:
893:
890:
884:
881:
859:
856:
840:
809:MIPS III is a
806:
803:
777:
774:
758:
712:
709:
706:
705:
702:
699:
693:
692:
689:
686:
683:
680:
674:
673:
670:
667:
664:
661:
658:
655:
649:
648:
645:
631:
628:
600:
597:
576:
573:
571:
568:
546:
545:
525:
523:
512:
509:
430:game console.
424:Emotion Engine
311:
310:
290:
288:
277:
274:
256:multithreading
237:floating-point
201:
200:
197:
195:Floating point
191:
190:
187:
181:
180:
174:
173:
166:
162:
161:
152:
148:
147:
144:
140:
139:
134:
128:
127:
124:
118:
117:
114:
108:
107:
102:
98:
97:
92:
86:
85:
82:
78:
77:
64:
60:
59:
53:
49:
48:
39:
26:
9:
6:
4:
3:
2:
7624:
7613:
7610:
7608:
7605:
7603:
7600:
7598:
7595:
7594:
7592:
7577:
7574:
7572:
7569:
7567:
7564:
7562:
7559:
7557:
7554:
7552:
7549:
7547:
7544:
7542:
7539:
7537:
7534:
7533:
7531:
7527:
7520:
7517:
7515:
7512:
7510:
7507:
7505:
7502:
7500:
7497:
7495:
7492:
7490:
7487:
7486:
7484:
7482:
7476:
7466:
7463:
7461:
7458:
7456:
7453:
7451:
7448:
7446:
7443:
7439:
7436:
7434:
7431:
7429:
7426:
7425:
7424:
7421:
7420:
7418:
7416:
7412:
7406:
7403:
7399:
7396:
7394:
7391:
7390:
7389:
7386:
7382:
7379:
7378:
7377:
7374:
7372:
7369:
7367:
7366:Demultiplexer
7364:
7362:
7359:
7358:
7356:
7354:
7350:
7344:
7341:
7339:
7336:
7333:
7331:
7328:
7326:
7323:
7321:
7318:
7316:
7313:
7312:
7310:
7308:
7304:
7298:
7295:
7293:
7290:
7288:
7287:Memory buffer
7285:
7283:
7282:Register file
7280:
7278:
7275:
7273:
7270:
7268:
7265:
7264:
7262:
7260:
7256:
7248:
7245:
7243:
7240:
7239:
7238:
7235:
7233:
7230:
7228:
7225:
7223:
7222:Combinational
7220:
7219:
7217:
7215:
7211:
7205:
7202:
7198:
7195:
7194:
7192:
7189:
7187:
7184:
7182:
7179:
7174:
7171:
7169:
7166:
7165:
7163:
7160:
7157:
7154:
7151:
7148:
7145:
7142:
7141:
7139:
7137:
7131:
7125:
7122:
7120:
7117:
7115:
7112:
7110:
7107:
7103:
7100:
7098:
7095:
7093:
7090:
7088:
7085:
7083:
7080:
7078:
7075:
7074:
7073:
7070:
7068:
7065:
7064:
7062:
7058:
7052:
7049:
7047:
7044:
7042:
7039:
7037:
7034:
7033:
7031:
7027:
7019:
7016:
7015:
7014:
7011:
7009:
7006:
7004:
7001:
6999:
6996:
6994:
6991:
6989:
6986:
6984:
6981:
6979:
6976:
6974:
6971:
6969:
6966:
6964:
6961:
6959:
6956:
6954:
6951:
6949:
6946:
6944:
6941:
6940:
6938:
6936:
6932:
6922:
6919:
6917:
6914:
6912:
6909:
6906:
6903:
6900:
6897:
6894:
6891:
6888:
6885:
6883:
6880:
6877:
6874:
6872:
6869:
6867:
6864:
6863:
6861:
6859:
6853:
6846:
6843:
6841:
6838:
6835:
6832:
6829:
6826:
6825:
6823:
6817:
6811:
6808:
6806:
6803:
6801:
6798:
6796:
6793:
6791:
6788:
6786:
6783:
6781:
6778:
6777:
6775:
6771:
6764:
6761:
6758:
6755:
6752:
6749:
6747:
6744:
6742:
6739:
6737:
6734:
6732:
6729:
6727:
6724:
6722:
6719:
6717:
6714:
6712:
6709:
6707:
6704:
6702:
6699:
6695:
6692:
6691:
6689:
6686:
6683:
6680:
6679:
6677:
6675:
6671:
6665:
6662:
6660:
6657:
6654:
6651:
6648:
6645:
6642:
6639:
6636:
6633:
6630:
6627:
6622:
6619:
6618:
6616:
6613:
6611:
6608:
6607:
6605:
6603:
6597:
6585:
6582:
6581:
6580:
6577:
6575:
6572:
6568:
6565:
6563:
6560:
6558:
6555:
6553:
6550:
6549:
6548:
6545:
6543:
6540:
6539:
6537:
6535:
6531:
6525:
6522:
6520:
6517:
6515:
6512:
6508:
6505:
6503:
6500:
6499:
6498:
6495:
6493:
6490:
6489:
6487:
6485:
6481:
6475:
6472:
6470:
6467:
6463:
6460:
6459:
6458:
6455:
6451:
6448:
6446:
6443:
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6441:
6438:
6434:
6431:
6429:
6426:
6425:
6424:
6421:
6419:
6416:
6412:
6409:
6407:
6404:
6403:
6402:
6399:
6398:
6396:
6392:
6389:
6387:
6383:
6373:
6370:
6368:
6365:
6364:
6362:
6360:
6356:
6350:
6347:
6345:
6342:
6338:
6335:
6333:
6330:
6329:
6328:
6325:
6323:
6322:Scoreboarding
6320:
6319:
6317:
6315:
6311:
6305:
6304:False sharing
6302:
6300:
6297:
6295:
6292:
6290:
6287:
6286:
6284:
6282:
6278:
6272:
6269:
6267:
6264:
6262:
6259:
6258:
6256:
6254:
6250:
6247:
6245:
6241:
6231:
6228:
6226:
6223:
6221:
6218:
6215:
6211:
6208:
6206:
6203:
6201:
6198:
6196:
6193:
6192:
6190:
6188:
6185:
6183:
6180:
6178:
6175:
6173:
6170:
6168:
6165:
6163:
6160:
6158:
6155:
6153:
6150:
6148:
6145:
6143:
6140:
6138:
6135:
6133:
6130:
6126:
6123:
6121:
6118:
6116:
6113:
6112:
6110:
6108:
6105:
6103:
6100:
6098:
6097:Stanford MIPS
6095:
6093:
6090:
6088:
6085:
6083:
6080:
6078:
6075:
6073:
6070:
6069:
6067:
6061:
6053:
6050:
6049:
6048:
6045:
6043:
6040:
6038:
6035:
6033:
6030:
6028:
6025:
6023:
6020:
6018:
6015:
6011:
6008:
6007:
6006:
6003:
5999:
5996:
5995:
5994:
5991:
5989:
5986:
5984:
5981:
5979:
5976:
5974:
5971:
5970:
5968:
5964:
5961:
5959:
5958:architectures
5953:
5947:
5944:
5942:
5939:
5937:
5934:
5932:
5929:
5927:
5926:Heterogeneous
5924:
5920:
5917:
5915:
5912:
5911:
5910:
5907:
5905:
5902:
5898:
5895:
5893:
5890:
5888:
5885:
5883:
5880:
5879:
5878:
5877:Memory access
5875:
5873:
5870:
5868:
5865:
5863:
5860:
5858:
5855:
5851:
5848:
5847:
5846:
5843:
5841:
5838:
5836:
5833:
5832:
5830:
5828:
5824:
5816:
5813:
5811:
5810:Random-access
5808:
5806:
5803:
5801:
5798:
5797:
5796:
5793:
5791:
5790:Stack machine
5788:
5786:
5783:
5779:
5776:
5774:
5771:
5769:
5766:
5764:
5761:
5759:
5756:
5754:
5751:
5749:
5746:
5744:
5741:
5740:
5739:
5736:
5732:
5729:
5727:
5724:
5722:
5719:
5717:
5714:
5712:
5709:
5707:
5706:with datapath
5704:
5703:
5702:
5699:
5697:
5694:
5692:
5689:
5688:
5686:
5684:
5680:
5676:
5669:
5664:
5662:
5657:
5655:
5650:
5649:
5646:
5634:
5630:
5626:
5623:
5621:
5618:
5616:
5612:
5609:
5607:
5604:
5602:
5599:
5597:
5593:
5590:
5588:
5585:
5583:
5580:
5578:
5575:
5573:
5570:
5568:
5565:
5562:
5560:
5557:
5555:
5552:
5550:
5547:
5546:
5544:
5540:
5534:
5530:
5527:
5524:
5522:
5519:
5517:
5514:
5512:
5509:
5507:
5504:
5502:
5498:
5494:
5491:
5488:
5486:
5483:
5481:
5478:
5476:
5473:
5471:
5470:LatticeMico32
5467:
5464:
5462:
5459:
5457:
5454:
5452:
5449:
5447:
5444:
5442:
5439:
5436:
5435:
5433:
5429:
5423:
5422:Stanford MIPS
5420:
5418:
5417:Berkeley RISC
5415:
5413:
5410:
5409:
5407:
5403:
5398:
5391:
5386:
5384:
5379:
5377:
5372:
5371:
5368:
5352:
5351:
5347:
5345:
5344:
5340:
5339:
5337:
5335:
5331:
5323:
5320:
5318:
5315:
5313:
5310:
5308:
5305:
5303:
5300:
5298:
5295:
5293:
5290:
5289:
5288:
5285:
5283:
5280:
5278:
5275:
5274:
5272:
5270:
5266:
5258:
5255:
5254:
5253:
5250:
5246:
5243:
5242:
5241:
5238:
5234:
5231:
5230:
5229:
5226:
5225:
5223:
5221:
5217:
5211:
5208:
5207:
5205:
5203:
5199:
5193:
5190:
5188:
5185:
5184:
5182:
5180:
5176:
5173:
5167:
5154:
5151:
5148:
5147:
5146:
5143:
5142:
5140:
5134:
5125:
5124:
5123:
5120:
5119:
5117:
5111:
5108:
5104:
5094:
5091:
5086:
5083:
5081:LS2F/LS2F1000
5080:
5079:
5078:
5075:
5074:
5072:
5066:
5063:
5061:
5060:Supercomputer
5057:
5047:
5044:
5043:PlayStation 2
5041:
5038:
5035:
5032:
5029:
5026:
5025:PlayStation 1
5023:
5022:
5020:
5016:
5013:
5009:
4996:
4995:
4994:
4991:
4986:
4985:
4984:
4981:
4980:
4978:
4972:
4963:
4962:
4961:
4958:
4954:
4951:
4950:
4948:
4943:
4942:
4941:
4938:
4933:
4932:
4931:
4928:
4927:
4925:
4919:
4910:
4909:
4908:
4905:
4904:
4902:
4898:
4889:
4888:
4887:
4884:
4883:
4881:
4877:
4868:
4867:
4866:
4863:
4858:
4855:
4854:
4853:
4850:
4845:
4842:
4841:
4840:
4837:
4836:
4834:
4830:
4821:
4818:
4815:
4814:
4813:
4810:
4805:
4802:
4799:
4798:
4797:
4794:
4793:
4791:
4787:
4778:
4775:
4774:
4773:
4770:
4765:
4762:
4759:
4756:
4753:
4750:
4747:
4744:
4743:
4742:
4739:
4734:
4731:
4728:
4725:
4724:
4723:
4720:
4719:
4717:
4713:
4704:
4703:
4702:
4699:
4698:
4696:
4692:
4683:
4682:
4681:
4678:
4673:
4672:
4670:
4667:
4662:
4661:
4660:
4657:
4652:
4649:
4648:
4647:
4644:
4643:
4641:
4637:
4634:
4630:
4617:
4614:
4611:
4608:
4605:
4602:
4599:
4598:
4597:
4594:
4593:
4591:
4585:
4579:
4575:
4574:
4572:
4568:
4562:
4559:
4556:
4555:
4553:
4549:
4546:
4542:
4538:
4525:
4522:
4521:
4520:
4517:
4516:
4514:
4508:
4499:
4494:
4491:
4489:
4486:
4485:
4483:
4478:
4475:
4474:
4472:
4469:
4465:
4462:
4458:
4455:
4451:
4447:
4444:
4443:
4441:
4440:
4439:
4436:
4435:
4433:
4427:
4424:
4418:
4405:
4402:
4399:
4396:
4393:
4390:
4387:
4384:
4381:
4380:
4379:
4376:
4375:
4373:
4367:
4364:
4358:
4352:
4349:
4347:
4344:
4342:
4339:
4338:
4335:
4326:
4321:
4319:
4314:
4312:
4307:
4306:
4303:
4297:
4293:
4290:
4287:
4285:
4281:
4278:
4275:
4272:
4268:
4265:
4263:
4259:
4256:
4253:
4252:
4242:
4236:
4232:
4227:
4223:
4221:1-55860-410-3
4217:
4213:
4208:
4204:
4202:1-55860-604-1
4198:
4194:
4189:
4188:
4182:
4178:
4174:
4170:
4168:1-55860-297-6
4164:
4160:
4155:
4154:
4144:
4140:
4135:
4119:
4115:
4111:
4105:
4099:
4095:
4090:
4082:
4078:
4072:
4057:
4053:
4049:
4043:
4039:
4035:
4031:
4030:
4022:
4011:September 29,
4006:
4002:
3996:
3981:
3977:
3972:
3967:
3963:
3959:
3952:
3937:
3930:
3926:
3920:
3901:
3897:
3890:
3889:
3881:
3875:
3871:
3866:
3857:
3851:
3835:
3831:
3816:
3812:
3806:
3790:
3786:
3780:
3764:
3760:
3754:
3738:
3734:
3728:
3712:
3708:
3702:
3683:
3679:
3672:
3665:
3646:
3639:
3633:
3622:September 21,
3617:
3613:
3609:
3603:
3584:
3580:
3573:
3572:
3565:
3554:
3547:
3540:
3532:
3528:
3521:
3505:
3501:
3495:
3479:
3475:
3474:
3470:
3463:
3455:
3451:
3445:
3443:
3423:
3419:
3413:
3405:
3399:
3395:
3388:
3380:
3376:
3372:
3366:
3358:
3354:
3350:
3344:
3336:
3330:
3326:
3319:
3308:
3292:
3288:
3284:
3278:
3259:
3252:
3246:
3227:
3220:
3214:
3195:
3191:
3184:
3183:
3176:
3157:
3154:. p. 5.
3150:
3144:
3142:
3134:
3130:
3128:9780123944245
3124:
3120:
3116:
3112:
3105:
3089:
3085:
3084:
3079:
3072:
3056:
3052:
3048:
3041:
3025:
3021:
3015:
2999:
2995:
2989:
2973:
2969:
2963:
2947:
2943:
2939:
2932:
2916:
2912:
2906:
2890:
2886:
2880:
2864:
2860:
2854:
2846:
2842:
2841:
2836:
2830:
2822:
2818:
2814:
2808:
2792:
2788:
2787:Business Wire
2784:
2778:
2776:
2774:
2772:
2770:
2758:
2747:
2744:(15): 24–28.
2743:
2739:
2738:
2730:
2723:
2721:
2712:
2708:
2704:
2698:
2682:
2678:
2677:www.d.umn.edu
2674:
2668:
2652:
2648:
2644:
2637:
2635:
2618:
2614:
2607:
2591:
2587:
2583:
2577:
2561:
2557:
2553:
2547:
2531:
2527:
2523:
2522:"MIPS-3D ASE"
2517:
2501:
2497:
2493:
2487:
2471:
2467:
2463:
2457:
2449:
2447:1-55860-410-3
2443:
2439:
2432:
2430:
2428:
2426:
2424:
2422:
2420:
2418:
2410:
2404:
2402:
2382:
2378:
2372:
2365:
2364:
2356:
2352:
2343:
2340:
2338:
2335:
2333:
2330:
2328:
2325:
2323:
2320:
2319:
2313:
2311:
2307:
2304:
2300:
2296:
2293:
2292:interruptions
2289:
2285:
2282:
2281:MIPS routines
2278:
2274:
2271:
2266:
2263:
2261:
2257:
2253:
2249:
2244:
2242:
2238:
2233:
2231:
2227:
2223:
2218:
2215:
2213:
2208:
2205:
2200:
2198:
2194:
2184:
2182:
2179:
2175:
2170:
2167:
2164:
2160:
2156:
2152:
2151:PlayStation 2
2148:
2145:
2141:
2137:
2132:
2130:
2126:
2122:
2118:
2114:
2110:
2106:
2102:
2098:
2094:
2090:
2086:
2082:
2078:
2067:
2055:
2050:
2041:
2040:
2031:
2028:February 2020
2022:
2018:
2015:This section
2013:
2010:
2006:
2005:
1997:
1990:
1966:
1963:
1958:
1953:
1952:
1948:
1946:
1945:frame pointer
1943:
1938:
1933:
1932:
1928:
1926:
1925:stack pointer
1923:
1918:
1913:
1912:
1908:
1905:
1900:
1895:
1894:
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1878:
1869:
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1864:
1861:
1852:
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1812:
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1800:
1791:
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1757:
1748:
1739:
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1734:
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1654:frame pointer
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1632:
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1397:
1391:
1372:
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1324:
1323:stack pointer
1319:
1308:
1296:
1292:
1274:
1270:
1264:
1262:
1242:
1239:
1234:
1223:
1221:
1218:
1215:
1212:
1209:
1206:
1202:
1198:
1195:
1192:
1187:
1182:
1179:
1176:
1173:
1172:
1168:
1165:
1162:
1159:
1156:
1153:
1150:
1147:
1143:
1140:
1137:
1134:
1131:
1128:
1125:
1122:
1119:
1118:
1114:
1111:
1110:
1106:
1103:
1100:
1096:
1093:
1090:
1089:
1084:
1081:
1078:
1074:
1070:
1066:
1062:
1058:
1055:
1054:
1049:
1046:
1043:
1040:
1037:
1034:
1031:
1028:
1025:
1024:
1020:
1016:
1013:
1012:
1011:
1009:
1005:
995:
986:
980:
977:
974:
971:
970:branch likely
968:
965:
964:
963:
957:
954:
951:
948:
945:
942:
939:
934:
931:
928:
925:
924:
922:
921:
920:
917:
907:
903:
899:
892:MIPS32/MIPS64
889:
880:
876:
874:
868:
866:
855:
851:
849:
844:
836:
834:
830:
825:
821:
816:
812:
802:
798:
795:
794:branch-likely
791:
787:
783:
773:
770:
766:
762:
756:
751:
747:
743:
739:
736:
731:
725:
723:
718:
704:address (26)
700:
698:
695:
687:
684:
681:
679:
676:
671:
668:
665:
662:
659:
656:
654:
651:
643:
642:
639:
636:
627:
624:
622:
618:
614:
613:link register
596:
594:
590:
586:
582:
567:
565:
561:
557:
553:
542:
539:February 2020
533:
529:
526:This section
524:
521:
517:
516:
508:
505:
503:
497:
494:
490:
488:
484:
480:
476:
472:
468:
464:
460:
456:
452:
448:
444:
438:
436:
431:
429:
428:PlayStation 2
425:
421:
417:
413:
410:Technologies
408:
403:
401:
397:
393:
389:
385:
381:
377:
373:
369:
364:
360:
356:
354:
350:
346:
342:
338:
336:
332:
328:
324:
318:
307:
304:February 2020
298:
294:
291:This section
289:
286:
282:
281:
273:
271:
267:
263:
259:
257:
253:
249:
245:
241:
238:
234:
229:
225:
223:
219:
215:
211:
207:
198:
196:
192:
188:
186:
182:
179:
175:
171:
167:
163:
160:
156:
153:
149:
145:
141:
138:
135:
133:
129:
125:
123:
119:
115:
113:
109:
106:
103:
99:
96:
93:
91:
87:
83:
79:
65:
61:
57:
54:
50:
47:
43:
40:
36:
30:
19:
7576:Chip carrier
7514:Clock gating
7433:Mixed-signal
7330:Write buffer
7307:Control unit
7119:Clock signal
6858:accelerators
6840:Cypress PSoC
6497:Simultaneous
6314:Out-of-order
6101:
5946:Neuromorphic
5827:Architecture
5785:Belt machine
5778:Zeno machine
5711:Hierarchical
5559:Apollo PRISM
5542:Discontinued
5474:
5466:LatticeMico8
5350:H2 "Capitan"
5348:
5341:
5178:
4446:Ben NanoNote
4340:
4230:
4212:See MIPS Run
4211:
4186:
4158:
4134:
4122:. Retrieved
4113:
4104:
4089:
4071:
4059:. Retrieved
4028:
4021:
4009:. Retrieved
3995:
3983:. Retrieved
3961:
3951:
3939:. Retrieved
3919:
3907:. Retrieved
3887:
3880:
3865:
3838:. Retrieved
3819:. Retrieved
3815:the original
3805:
3793:. Retrieved
3779:
3767:. Retrieved
3753:
3741:. Retrieved
3727:
3715:. Retrieved
3701:
3691:December 22,
3689:. Retrieved
3664:
3652:. Retrieved
3632:
3620:. Retrieved
3616:the original
3611:
3602:
3590:. Retrieved
3583:the original
3570:
3564:
3539:
3520:
3508:. Retrieved
3504:the original
3494:
3482:. Retrieved
3472:
3462:
3454:the original
3429:. Retrieved
3412:
3393:
3387:
3379:the original
3374:
3365:
3352:
3343:
3325:See MIPS Run
3324:
3318:
3307:
3297:February 11,
3295:. Retrieved
3291:the original
3286:
3277:
3267:December 15,
3265:. Retrieved
3245:
3235:December 15,
3233:. Retrieved
3213:
3201:. Retrieved
3181:
3175:
3165:December 27,
3163:. Retrieved
3132:
3110:
3104:
3092:. Retrieved
3081:
3071:
3059:. Retrieved
3050:
3040:
3028:. Retrieved
3014:
3004:December 16,
3002:. Retrieved
2988:
2978:December 16,
2976:. Retrieved
2962:
2950:. Retrieved
2941:
2931:
2921:December 18,
2919:. Retrieved
2905:
2895:December 19,
2893:. Retrieved
2879:
2869:December 19,
2867:. Retrieved
2853:
2845:the original
2838:
2829:
2821:the original
2807:
2797:February 11,
2795:. Retrieved
2757:
2741:
2735:
2711:the original
2697:
2685:. Retrieved
2676:
2667:
2655:. Retrieved
2646:
2621:. Retrieved
2606:
2594:. Retrieved
2585:
2576:
2564:. Retrieved
2555:
2546:
2534:. Retrieved
2530:the original
2516:
2504:. Retrieved
2495:
2486:
2474:. Retrieved
2470:the original
2465:
2456:
2438:See MIPS Run
2437:
2408:
2390:November 28,
2388:. Retrieved
2362:
2355:
2303:system calls
2267:
2264:
2245:
2234:
2219:
2216:
2211:
2209:
2201:
2190:
2171:
2168:
2138:such as the
2133:
2074:
2061:
2053:
2025:
2021:adding to it
2016:
1991:
1974:
1373:
1362:
1327:
1320:
1309:
1297:
1293:
1265:
1235:
1232:
1003:
1001:
992:
984:
969:
961:
918:
902:multiply-add
895:
886:
877:
869:
861:
852:
847:
845:
837:
832:
828:
823:
819:
808:
799:
793:
789:
785:
781:
779:
771:
767:
763:
752:
748:
744:
740:
734:
726:
714:
696:
677:
652:
637:
633:
625:
620:
616:
602:
584:
578:
552:coprocessors
549:
536:
532:adding to it
527:
506:
498:
495:
491:
439:
432:
404:
357:
339:
334:
333:was renamed
330:
320:
301:
297:adding to it
292:
260:
258:capability.
230:
226:
209:
205:
204:
168:Partly. The
29:
7361:Multiplexer
7325:Data buffer
7036:Single-core
7008:bit slicing
6866:Coprocessor
6721:Coprocessor
6602:performance
6524:Cooperative
6514:Speculative
6474:Distributed
6433:Superscalar
6418:Instruction
6386:Parallelism
6359:Speculative
6191:System/3x0
6063:Instruction
5840:Von Neumann
5753:Post–Turing
5554:AMD Am29000
5039:R4000-based
5031:Nintendo 64
4819:Fusiv Vx180
4468:Game Gadget
4461:Dingoo A320
4420:Application
3962:IEEE Access
3941:January 25,
3909:January 25,
3840:January 13,
3821:January 13,
3759:"EduMIPS64"
3353:gcc.gnu.org
3094:January 19,
3061:December 1,
2254:Octeon I),
2147:PlayStation
2140:Nintendo 64
2093:workstation
2064:August 2020
1862:temporaries
1810:temporaries
1571:temporaries
1519:temporaries
1382:registers (
560:PlayStation
418:(1996) and
400:PlayStation
396:Nintendo 64
7591:Categories
7481:management
7376:Multiplier
7237:Logic gate
7227:Sequential
7134:Functional
7114:Clock rate
7087:Data cache
7060:Components
7041:Multi-core
7029:Core count
6519:Preemptive
6423:Pipelining
6406:Bit-serial
6349:Wide-issue
6294:Structural
6216:Tilera ISA
6182:MicroBlaze
6152:ETRAX CRIS
6047:Comparison
5892:Load–store
5872:Endianness
5592:Intel i860
5529:MicroBlaze
5343:H1 "Beast"
5171:processors
5138:compatible
5115:compatible
5070:compatible
5033:NEC VR4300
4976:compatible
4923:compatible
4715:24Kc/24KEc
4632:Networking
4589:compatible
4512:compatible
4431:compatible
4422:processors
4371:compatible
4362:processors
3654:August 17,
3592:August 17,
3510:August 17,
3431:August 17,
3287:imgtec.com
3203:August 24,
2536:January 4,
2348:References
2187:Simulators
1714:constant 0
1423:constant 0
1205:smart card
848:supervisor
701:opcode (6)
682:opcode (6)
672:funct (6)
657:opcode (6)
579:MIPS is a
315:See also:
151:Extensions
132:Endianness
105:Load–store
63:Introduced
7415:Circuitry
7335:Microcode
7259:Registers
7102:coherence
7077:CPU cache
6935:Word size
6600:Processor
6244:Execution
6147:DEC Alpha
6125:Power ISA
5941:Cognitive
5748:Universal
5587:DEC PRISM
5533:PicoBlaze
5485:Power ISA
5106:Aerospace
4061:August 2,
4056:245387555
3980:2169-3536
3733:"Imperas"
3030:March 11,
2657:March 28,
2596:March 20,
2566:March 20,
2552:"MIPS16e"
2506:March 20,
2476:March 20,
1196:SmartMIPS
1061:LSI Logic
1051:securely.
1019:interrupt
989:microMIPS
833:Load Word
829:Load Word
669:shamt (5)
599:Registers
463:LSI Logic
178:Registers
146:4 KB
143:Page size
122:Branching
58:(32 → 64)
7353:Datapath
7046:Manycore
7018:variable
6856:Hardware
6492:Temporal
6172:OpenRISC
5867:Cellular
5857:Dataflow
5850:modified
5480:OpenRISC
5461:eSi-RISC
5441:Blackfin
5220:MIPS III
5093:SiCortex
5087:LS3B1000
5084:LS3A1000
4983:Broadcom
4930:Broadcom
4911:RTL8198C
4886:MediaTek
4865:Broadcom
4852:MediaTek
4741:MediaTek
4659:MediaTek
4639:4Kc/4KEc
4600:LS1A0300
4570:4Kc/4KEc
4495:GCW-Zero
4492:NEOGEO-X
4466:JZ4750 (
4459:JZ4740 (
4452:JZ4730 (
4406:LS3B4000
4403:LS3B3000
4400:LS3B2000
4397:LS3B1500
4394:LS3B1000
4292:Archived
4280:Archived
4258:Archived
4183:(2004).
4124:July 25,
4118:Archived
4081:Archived
4005:Archived
3985:July 24,
3964:: 1–17.
3900:Archived
3860:(source)
3850:cite web
3834:Archived
3789:Archived
3763:Archived
3737:Archived
3711:Archived
3682:Archived
3645:Archived
3553:Archived
3531:Archived
3484:June 19,
3478:Archived
3422:Archived
3357:Archived
3258:Archived
3226:Archived
3194:Archived
3156:Archived
3088:Archived
3055:Archived
3024:Archived
2998:Archived
2972:Archived
2952:July 18,
2946:Archived
2942:EE Times
2915:Archived
2889:Archived
2863:Archived
2840:EE Times
2791:Archived
2746:Archived
2681:Archived
2651:Archived
2617:Archived
2590:Archived
2560:Archived
2500:Archived
2381:Archived
2316:See also
2312:, etc.)
2306:Archived
2295:Archived
2284:Archived
2273:Archived
2174:MediaTek
2117:SiCortex
2089:personal
2079:such as
1316:alloca()
1238:System V
1014:MIPS MCU
805:MIPS III
735:relation
570:Versions
502:Loongson
455:Broadcom
325:for its
112:Encoding
38:Designer
18:MIPS III
7529:Related
7460:Quantum
7450:Digital
7445:Boolean
7343:Counter
7242:Quantum
7003:512-bit
6998:256-bit
6993:128-bit
6836:(MPSoC)
6821:on chip
6819:Systems
6637:(FLOPS)
6450:Process
6299:Control
6281:Hazards
6167:Itanium
6162:Unicore
6120:PowerPC
5845:Harvard
5805:Pointer
5800:Counter
5758:Quantum
5629:PowerPC
5620:PA-RISC
5572:Clipper
5521:Unicore
5490:Renesas
5412:IBM 801
5405:Origins
5317:R16000A
5307:R14000A
5297:R12000A
5269:MIPS IV
5202:MIPS II
5169:Classic
5018:various
4987:various
4953:Alchemy
4944:various
4934:various
4907:Realtek
4869:BCM4706
4846:QCA9558
4701:Marvell
4609:LS1C101
4606:LS1C300
4578:Xilleon
4561:PIC32MX
4484:JZ4770
4473:JZ4760
4442:JZ4720
4360:General
4269:at the
3894:(MSc).
3795:May 30,
3769:May 30,
3743:May 30,
3717:May 30,
2687:May 17,
2623:May 28,
2256:Imperas
2197:Imperas
2085:routers
2054:updated
1273:x32 ABI
1220:MIPS-3D
1077:Toshiba
858:MIPS IV
776:MIPS II
730:bitwise
611:is the
487:unlucky
459:Philips
447:Toshiba
276:History
233:MIPS-3D
216:(RISC)
159:MIPS-3D
81:Version
71: (
7465:Switch
7455:Analog
7193:(IMC)
7164:(MMU)
7013:others
6988:64-bit
6983:48-bit
6978:32-bit
6973:24-bit
6968:16-bit
6963:15-bit
6958:12-bit
6795:Mobile
6711:Stream
6706:Barrel
6701:Vector
6690:(GPU)
6649:(SUPS)
6617:(IPC)
6469:Memory
6462:Vector
6445:Thread
6428:Scalar
6230:Others
6177:RISC-V
6142:SuperH
6111:Power
6107:MIPS-X
6082:PDP-11
5931:Fabric
5683:Models
5615:M·CORE
5606:MIPS-X
5526:Xilinx
5516:Sunway
5506:RISC-V
5497:SuperH
5431:Active
5334:MIPS V
5322:R18000
5312:R16000
5302:R14000
5292:R12000
5287:R10000
5245:R4300i
5179:MIPS I
5149:LS1E04
5136:MIPS32
5113:MIPS64
5068:MIPS64
5011:Gaming
4997:Octeon
4993:Cavium
4974:MIPS64
4940:Cavium
4921:MIPS32
4900:1074Kc
4890:MT7621
4879:1004Kc
4859:RT3883
4856:RT3662
4843:AR9344
4812:Ikanos
4806:GRX388
4803:VRX288
4796:Lantiq
4776:DANUBE
4772:Lantiq
4766:MT7688
4763:MT7628
4760:MT7620
4757:RT6856
4754:RT5350
4751:RT3350
4748:RT3052
4745:RT3050
4735:AR9331
4732:AR9132
4729:AR7161
4726:AR7240
4684:AMAZON
4680:Lantiq
4663:RT2880
4653:AR2318
4650:AR2313
4587:MIPS32
4510:MIPS64
4500:JZ4780
4429:MIPS32
4369:MIPS64
4237:
4218:
4199:
4165:
4143:GitHub
4114:WepSIM
4098:GitHub
4054:
4044:
3978:
3874:GitHub
3500:"NUBI"
3400:
3331:
3125:
2444:
2373:
2260:CoWare
2252:Cavium
2248:Simics
2237:GXemul
2228:, and
2193:OVPsim
2181:PIC32M
2163:TOP500
2153:, and
2127:, and
2097:server
2095:, and
1705:$ zero
1693:Number
1414:$ zero
1402:Number
1213:(MDMX)
1146:endian
1075:, and
1056:MIPS16
883:MIPS V
822:, and
815:64-bit
788:, and
688:rt (5)
685:rs (5)
666:rd (5)
663:rt (5)
660:rs (5)
593:memory
575:MIPS I
511:Design
475:Cavium
451:SiByte
420:RM7000
412:R10000
335:MIPS I
270:RISC-V
170:R16000
90:Design
56:64-bit
7521:(PPW)
7479:Power
7371:Adder
7247:Array
7214:Logic
7175:(TLB)
7158:(FPU)
7152:(AGU)
7146:(ALU)
7136:units
7072:Cache
6953:8-bit
6948:4-bit
6943:1-bit
6907:(TPU)
6901:(DSP)
6895:(PPU)
6889:(VPU)
6878:(GPU)
6847:(NoC)
6830:(SoC)
6765:(PoP)
6759:(SiP)
6753:(MCM)
6694:GPGPU
6684:(CPU)
6674:Types
6655:(PPW)
6643:(TPS)
6631:(IPS)
6623:(CPI)
6394:Level
6205:S/390
6200:S/370
6195:S/360
6137:SPARC
6115:POWER
5998:TRIPS
5966:Types
5625:POWER
5582:CRISP
5567:AVR32
5564:Atmel
5549:Alpha
5511:SPARC
5282:R8000
5277:R5000
5257:R4700
5252:R4600
5240:R4200
5233:R4400
5228:R4000
5210:R6000
5192:R3000
5187:R2000
4800:AR188
4779:VINAX
4052:S2CID
3932:(PDF)
3903:(PDF)
3892:(PDF)
3685:(PDF)
3674:(PDF)
3648:(PDF)
3641:(PDF)
3586:(PDF)
3575:(PDF)
3556:(PDF)
3549:(PDF)
3425:(PDF)
3261:(PDF)
3254:(PDF)
3229:(PDF)
3222:(PDF)
3197:(PDF)
3186:(PDF)
3159:(PDF)
3152:(PDF)
2749:(PDF)
2732:(PDF)
2384:(PDF)
2367:(PDF)
2230:macOS
2226:Linux
1269:ILP32
914:SYNCI
416:R5000
407:R8000
388:R4200
384:R4600
363:R4000
345:R6000
327:R2000
266:Alpha
116:Fixed
7499:ACPI
7232:Glue
7124:FIFO
7067:Core
6805:ASIP
6746:CPLD
6741:FPOA
6736:FPGA
6731:ASIC
6584:SPMD
6579:MIMD
6574:MISD
6567:SWAR
6547:SIMD
6542:SISD
6457:Data
6440:Task
6411:Word
6157:M32R
6102:MIPS
6065:sets
6032:ZISC
6027:NISC
6022:OISC
6017:MISC
6010:EPIC
6005:VLIW
5993:EDGE
5983:RISC
5978:CISC
5887:HUMA
5882:NUMA
5633:ROMP
5601:META
5596:i960
5577:CR16
5501:V850
5493:M32R
5475:MIPS
5155:LS1J
4832:74Kc
4789:34Kc
4618:LS1H
4615:LS1G
4612:LS1D
4603:LS1B
4523:LS2H
4235:ISBN
4216:ISBN
4197:ISBN
4163:ISBN
4126:2022
4063:2022
4042:ISBN
4013:2021
3987:2024
3976:ISSN
3943:2021
3911:2021
3856:link
3842:2012
3823:2012
3797:2012
3771:2012
3745:2012
3719:2012
3693:2011
3656:2020
3624:2018
3594:2020
3512:2020
3486:2020
3433:2020
3398:ISBN
3329:ISBN
3299:2016
3269:2023
3237:2023
3205:2022
3167:2023
3123:ISBN
3096:2024
3063:2021
3032:2021
3006:2019
2980:2019
2954:2022
2923:2018
2897:2018
2871:2018
2799:2016
2689:2023
2659:2021
2625:2009
2598:2020
2586:MIPS
2568:2020
2556:MIPS
2538:2014
2508:2020
2496:MIPS
2478:2020
2466:MIPS
2442:ISBN
2392:2018
2371:ISBN
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