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Load–store architecture

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For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a
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Computer architecture: pipelined and parallel processor design
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The earliest example of a load–store architecture was the
101: 62:operations (which only occur between registers). 291: 204: 159: 46:that divides instructions into two categories: 274: 281: 267: 210:Memory systems and pipelined processors 155: 153: 151: 149: 14: 292: 100:instruction set architecture such as 233: 146: 27:Type of instruction set architecture 24: 25: 316: 237: 119:) use the load–store approach. 198: 181: 89:are load–store architectures. 40:register–register architecture 13: 1: 139: 253:. You can help Knowledge by 134:Register–memory architecture 94:register–memory architecture 44:instruction set architecture 7: 122: 10: 321: 305:Computer engineering stubs 232: 36:load–store architecture 249:-related article is a 69:architectures such as 300:Computer architecture 247:computer-engineering 212:. pp. 512–513. 32:computer engineering 189:"AMD GCN reference" 54:between memory and 262: 261: 113:vector processors 16:(Redirected from 312: 283: 276: 269: 241: 234: 224: 223: 206:Harvey G. Cragon 202: 196: 195: 193: 185: 179: 178: 161:Michael J. Flynn 157: 115:(including many 96:(for example, a 21: 320: 319: 315: 314: 313: 311: 310: 309: 290: 289: 288: 287: 230: 228: 227: 220: 203: 199: 191: 187: 186: 182: 175: 158: 147: 142: 129:Load–store unit 125: 28: 23: 22: 15: 12: 11: 5: 318: 308: 307: 302: 286: 285: 278: 271: 263: 260: 259: 242: 226: 225: 218: 197: 180: 173: 144: 143: 141: 138: 137: 136: 131: 124: 121: 52:load and store 26: 9: 6: 4: 3: 2: 317: 306: 303: 301: 298: 297: 295: 284: 279: 277: 272: 270: 265: 264: 258: 256: 252: 248: 243: 240: 236: 235: 231: 221: 215: 211: 207: 201: 190: 184: 176: 170: 166: 162: 156: 154: 152: 150: 145: 135: 132: 130: 127: 126: 120: 118: 114: 111:. Almost all 110: 105: 103: 99: 95: 90: 88: 84: 80: 76: 72: 68: 63: 61: 57: 53: 49: 45: 41: 37: 33: 19: 255:expanding it 244: 229: 209: 200: 183: 164: 106: 91: 64: 39: 35: 29: 294:Categories 219:0867204745 174:0867202041 140:References 18:Load–store 56:registers 208:(1996). 163:(1995). 123:See also 109:CDC 6600 50:access ( 42:) is an 71:PowerPC 216:  171:  85:, and 79:RISC-V 58:) and 48:memory 38:(or a 245:This 192:(PDF) 75:SPARC 65:Some 251:stub 214:ISBN 169:ISBN 117:GPUs 98:CISC 87:MIPS 67:RISC 34:, a 102:x86 83:ARM 60:ALU 30:In 296:: 167:. 148:^ 81:, 77:, 73:, 282:e 275:t 268:v 257:. 222:. 194:. 177:. 20:)

Index

Load–store
computer engineering
instruction set architecture
memory
load and store
registers
ALU
RISC
PowerPC
SPARC
RISC-V
ARM
MIPS
register–memory architecture
CISC
x86
CDC 6600
vector processors
GPUs
Load–store unit
Register–memory architecture




Michael J. Flynn
ISBN
0867202041
"AMD GCN reference"
Harvey G. Cragon

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