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Gunning transceiver logic

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and higher voltage levels. AGTL+ stands for either assisted Gunning transceiver logic or advanced Gunning transceiver logic. These are GTL signaling derivatives used by Intel microprocessors.
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JEDEC Standard JESD8-3A, Gunning Transceiver Logic (GTL) Low-Level, High Speed Interface Standard for Digital Integrated Circuits
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use GTL. As of 2008, GTL in these FSBs has a maximum frequency of 1.6 GHz. The front-side bus of the
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is specified to be 100 MHz, although some applications use higher frequencies. GTL is defined by
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standard JESD 8-3 (1993) and was invented by William Gunning while working for
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logic—and symmetrical parallel resistive termination. The maximum signaling
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swing between 0.4 volts and 1.2 volts—much lower than that used in
184:"GTLP vs. GTL: A Performance Comparison from a System Perspective" 255: 96: 330: 294: 247: 116: 112: 218:"GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic" 318: 104: 142:microprocessors uses GTL+ (or GTLP) developed by 445: 146:, an upgraded version of GTL which has defined 271: 85:) is a type of logic signaling used to drive 278: 264: 401:Current mode logic / Source-coupled logic 66:Learn how and when to remove this message 29:This article includes a list of general 446: 166: 259: 15: 13: 285: 35:it lacks sufficient corresponding 14: 475: 20: 365:Direct-coupled transistor logic 199:, December 2000, archived from 160: 1: 153: 7: 395:Transistor–transistor logic 10: 480: 383:Integrated injection logic 167:Shimpi, Anand Lal (2008), 410: 389:Resistor–transistor logic 377:Gunning transceiver logic 340: 313:Depletion-load NMOS logic 293: 170:Intel's Atom Architecture 121:Palo Alto Research Center 79:Gunning transceiver logic 197:Fairchild Semiconductor 144:Fairchild Semiconductor 50:more precise citations. 353:Diode–transistor logic 371:Emitter-coupled logic 325:Pass transistor logic 341:Other technologies 441: 440: 319:Complementary MOS 231:Texas Instruments 132:Intel Pentium Pro 76: 75: 68: 471: 433:Four-phase logic 315:(including HMOS) 280: 273: 266: 257: 256: 251: 245: 234: 226:Application Note 222: 213: 212: 211: 205: 188: 174: 173: 164: 128:front-side buses 71: 64: 60: 57: 51: 46:this article by 37:inline citations 24: 23: 16: 479: 478: 474: 473: 472: 470: 469: 468: 459:JEDEC standards 444: 443: 442: 437: 406: 336: 289: 284: 254: 243: 237: 220: 216: 209: 207: 203: 186: 182: 178: 177: 165: 161: 156: 72: 61: 55: 52: 42:Please help to 41: 25: 21: 12: 11: 5: 477: 467: 466: 464:Logic families 461: 456: 454:Computer buses 439: 438: 436: 435: 430: 425: 420: 414: 412: 408: 407: 405: 404: 398: 392: 386: 380: 374: 368: 362: 359:Open collector 356: 350: 344: 342: 338: 337: 335: 334: 328: 322: 316: 310: 305: 299: 297: 295:MOS technology 291: 290: 287:Logic families 283: 282: 275: 268: 260: 253: 252: 235: 214: 179: 176: 175: 158: 157: 155: 152: 74: 73: 28: 26: 19: 9: 6: 4: 3: 2: 476: 465: 462: 460: 457: 455: 452: 451: 449: 434: 431: 429: 426: 424: 421: 419: 416: 415: 413: 409: 402: 399: 396: 393: 390: 387: 384: 381: 378: 375: 372: 369: 366: 363: 360: 357: 354: 351: 349: 346: 345: 343: 339: 332: 329: 326: 323: 320: 317: 314: 311: 309: 306: 304: 301: 300: 298: 296: 292: 288: 281: 276: 274: 269: 267: 262: 261: 258: 249: 242: 241: 236: 232: 228: 227: 219: 215: 206:on 2013-09-22 202: 198: 194: 193: 185: 181: 180: 172: 171: 163: 159: 151: 149: 145: 141: 137: 133: 129: 124: 122: 118: 114: 110: 106: 102: 98: 94: 91: 88: 84: 80: 70: 67: 59: 49: 45: 39: 38: 32: 27: 18: 17: 428:Domino logic 376: 331:Bipolar–CMOS 239: 224: 208:, retrieved 201:the original 190: 169: 162: 125: 82: 78: 77: 62: 53: 34: 348:Diode logic 140:Pentium III 95:. It has a 48:introducing 448:Categories 308:NMOS logic 303:PMOS logic 250:, May 2007 210:2008-03-18 154:References 148:slew rates 136:Pentium II 126:All Intel 87:electronic 56:March 2014 31:references 403:(CML/SCL) 109:frequency 90:backplane 333:(BiCMOS) 423:Dynamic 192:AN-1070 119:at the 97:voltage 44:improve 418:Static 367:(DCTL) 321:(CMOS) 233:, 1997 33:, but 411:Types 397:(TTL) 391:(RTL) 379:(GTL) 373:(ECL) 355:(DTL) 327:(PTL) 248:JEDEC 244:(PDF) 221:(PDF) 204:(PDF) 187:(PDF) 117:Xerox 113:JEDEC 93:buses 385:(IL) 361:(OC) 138:and 105:CMOS 103:and 101:TTL 83:GTL 450:: 246:, 229:, 223:, 195:, 189:, 134:, 123:. 279:e 272:t 265:v 81:( 69:) 63:( 58:) 54:( 40:.

Index

references
inline citations
improve
introducing
Learn how and when to remove this message
electronic
backplane
buses
voltage
TTL
CMOS
frequency
JEDEC
Xerox
Palo Alto Research Center
front-side buses
Intel Pentium Pro
Pentium II
Pentium III
Fairchild Semiconductor
slew rates
Intel's Atom Architecture
"GTLP vs. GTL: A Performance Comparison from a System Perspective"
AN-1070
Fairchild Semiconductor
the original
"GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic"
Application Note
Texas Instruments
JEDEC Standard JESD8-3A, Gunning Transceiver Logic (GTL) Low-Level, High Speed Interface Standard for Digital Integrated Circuits

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