812:). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3 GHz, under uniform traffic) reaches 200 GB per second.
417:(ISA) added a second 8237 DMA controller to provide three additional, and as highlighted by resource clashes with the XT's additional expandability over the original PC, much-needed channels (5–7; channel 4 is used as a cascade to the first 8237). The page register was also rewired to address the full 16 MB memory address space of the 80286 CPU. This second controller was also integrated in a way capable of performing 16-bit transfers when an I/O device is used as the data source and/or destination (as it actually only processes data itself for memory-to-memory transfers, otherwise simply
25:
321:
442:/s maximum 8-bit transfer capability at 5 MHz, but no more than 0.9 MB/s in the PC/XT and 1.6 MB/s for 16-bit transfers in the AT due to ISA bus overheads and other interference such as memory refresh interruptions) and unavailability of any speed grades that would allow installation of direct replacements operating at speeds higher than the original PC's standard 4.77 MHz clock, these devices have been effectively obsolete since the late 1980s. Particularly, the advent of the
298:
data per request, until the entire block of data has been transferred. By continually obtaining and releasing the control of the system bus, the DMA controller essentially interleaves instruction and data transfers. The CPU processes an instruction, then the DMA controller transfers one data value, and so on. Data is not transferred as quickly, but CPU is not idled for as long as in burst mode. Cycle stealing mode is useful for controllers that monitor data in real time.
474:) the "ISA" bus with their own much higher-performance DMA subsystems (up to a maximum of 33 MB/s for EISA, 40 MB/s MCA, typically 133 MB/s VLB/PCI) made the original DMA controllers seem more of a performance millstone than a booster. They were supported to the extent they are required to support built-in legacy PC hardware on later machines. The pieces of legacy hardware that continued to use ISA DMA after 32-bit expansion buses became common were
2315:
165:
717:(NICs) to DMA directly to the Last level cache (L3 cache) of local CPUs and avoid costly fetching of the I/O data from system RAM. As a result, DDIO reduces the overall I/O processing latency, allows processing of the I/O to be performed entirely in-cache, prevents the available RAM bandwidth/latency from becoming a performance bottleneck, and may lower the power consumption by allowing RAM to remain longer in low-powered state.
265:, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU, but renders the CPU inactive for relatively long periods of time. The mode is also called "Block Transfer Mode".
634:, which will in turn convert them to DDR operations and send them out on the memory bus. As a result, there are quite a number of steps involved in a PCI DMA transfer; however, that poses little problem, since the PCI device or PCI bus itself are an order of magnitude slower than the rest of the components (see
306:
Transparent mode takes the most time to transfer a block of data, yet it is also the most efficient mode in terms of overall system performance. In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses. The primary advantage of
297:
signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one unit of data transfer, the control of the system bus is deasserted to the CPU via BG. It is then continually requested again via BR, transferring one unit of
247:
system, also known as a first-party DMA system, the CPU and peripherals can each be granted control of the memory bus. Where a peripheral can become a bus master, it can directly write to system memory without the involvement of the CPU, providing memory address and control signals as required. Some
390:
segments within that space (although the source and destination channels could address different segments). Additionally, the controller could only be used for transfers to, from or between expansion bus I/O devices, as the 8237 could only perform memory-to-memory transfers using channels 0 & 1,
349:
for DMA writes or cache flush for DMA reads. Non-coherent systems leave this to software, where the OS must then ensure that the cache lines are flushed before an outgoing DMA transfer is started and invalidated before a memory range affected by an incoming DMA transfer is accessed. The OS must make
788:
incorporates a DMA engine for each of its 9 processing elements including one Power processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from
199:
that can be written and read by the CPU. These include a memory address register, a byte count register, and one or more control registers. Depending on what features the DMA controller provides, these control registers might specify some combination of the source, the destination, the direction of
506:
Each DMA channel has a 16-bit address register and a 16-bit count register associated with it. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to
330:
problems. Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external
430:
issue remained, with individual transfers unable to cross segments (instead "wrapping around" to the start of the same segment) even in 16-bit mode, although this was in practice more a problem of programming complexity than performance as the continued need for DRAM refresh (however handled) to
207:
to transfer, and the memory address to use. The CPU then commands the peripheral device to initiate a data transfer. The DMA controller then provides addresses and read/write control lines to the system memory. Each time a byte of data is ready to be transferred between the peripheral device and
422:
transfers were now technically possible due to the freeing up of channel 0 from having to handle DRAM refresh, from a practical standpoint they were of limited value because of the controller's consequent low throughput compared to what the CPU could now achieve (i.e., a 16-bit, more optimised
421:
the data flow between other parts of the 16-bit system, making its own data bus width relatively immaterial), doubling data throughput when the upper three channels are used. For compatibility, the lower four DMA channels were still limited to 8-bit transfers only, and whilst memory-to-memory
107:
from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including
103:, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an
538:
of computer systems with DMA functionality, represent electronic signaling lines between the CPU and DMA controller. Each DMA channel has one
Request and one Acknowledge line. A device that uses DMA must be configured to use both lines of the assigned DMA channel.
307:
transparent mode is that the CPU never stops executing its programs and the DMA transfer is free in terms of time, while the disadvantage is that the hardware needs to determine when the CPU is not using the system buses, which can be complex. This is also called "
614:
if several devices request bus ownership simultaneously, since there can only be one bus master at one time. When the component is granted ownership, it will issue normal read and write commands on the PCI bus, which will be claimed by the PCI bus controller.
750:
Therefore, high bandwidth devices such as network controllers that need to transfer huge amounts of data to/from system memory will have two interface adapters to the AHB: a master and a slave interface. This is because on-chip buses like AHB do not support
280:
is used in systems in which the CPU should not be disabled for the length of time needed for burst transfer modes. In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using
350:
sure that the memory range is not accessed by any running threads in the meantime. The latter approach introduces some overhead to the DMA operation, as most hardware requires a loop to invalidate each cache line individually.
868:
or multibuffering. For example, the on-chip memory is split into two buffers; the processor may be operating on data in one, while the DMA engine is loading and storing data in the other. This allows the system to avoid
747:) can write/read I/O registers or (less commonly) local memory blocks inside the device. A master interface can be used by the device to perform DMA transactions to/from system memory without heavily loading the CPU.
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parallel port controller when ECP mode is selected. In cases where an original 8237s or direct compatibles were still used, transfer to or from these devices may still be limited to the first 16 MB of main
518:
DMA allows the transfer of data to and from multiple memory areas in a single DMA transaction. It is equivalent to the chaining together of multiple simple DMA requests. The motivation is to off-load multiple
610:") and request to read from and write to system memory. More precisely, a PCI component requests bus ownership from the PCI bus controller (usually PCI host bridge, and PCI to PCI bridge), which will
653:(DAC) mechanism, if implemented on both the PCI bus and the device itself, enables 64-bit DMA addressing. Otherwise, the operating system would need to work around the problem by either using costly
132:
inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.
378:
DMA controller capable of providing four DMA channels (numbered 0–3). These DMA channels performed 8-bit transfers (as the 8237 was an 8-bit device, ideally matched to the PC's
689:
developer Andrew Grover performed benchmarks using I/OAT to offload network traffic copies and found no more than 10% improvement in CPU utilization with receiving workloads.
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processor in 1985 and its capacity for 32-bit transfers (although great improvements in the efficiency of address calculation and block memory moves in Intel CPUs after the
1477:
1453:
743:. AMBA defines two kinds of AHB components: master and slave. A slave interface is similar to programmed I/O through which the software (running on embedded CPU, e.g.
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the transfer (reading from the I/O device or writing to the I/O device), the size of the transfer unit, and/or the number of bytes to transfer in one burst.
740:
135:
DMA can also be used for "memory to memory" copying or moving of data within memory. DMA can offload expensive memory operations, such as large copies or
649:(PAE), a 36-bit addressing mode. In such a case, a device using DMA with a 32-bit address bus is unable to address memory above the 4 GB line. The new
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Similarly, if the cached copy of X is not invalidated when a device writes a new value to the memory, then the CPU will operate on a stale value of X.
128:. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a
1203:
755:
the bus or alternating the direction of any line on the bus. Like PCI, no central DMA controller is required since the DMA is bus-mastering, but an
203:
To carry out an input, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of
1429:
1286:"Achieving Lowest Latencies at Highest Message Rates with Intel Xeon Processor E5-2600 and Solarflare SFN6122F 10 GbE Server Adapter"
2310:
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
335:. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.
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2283:
726:
1912:
1775:
459:
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the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this
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1314:
1000:
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This issue can be addressed in one of two ways in system design: Cache-coherent systems implement a method in hardware, called
1963:
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1285:
1232:
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Hybrids also exist, where the secondary L2 cache is coherent while the L1 cache (typically on-CPU) is managed by software.
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architecture has no central DMA controller, unlike ISA. Instead, A PCI device can request control of the bus ("become the
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below the middle of the image are the DMA controller (l.) and - unusual - an extra dedicated DMA controller (r.) for the
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1406:
2016:
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1845:
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68:
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running at a minimum of 6 MHz, vs an 8-bit controller locked at 4.77 MHz). In both cases, the 64 kB
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1504:
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memory, the DMA controller increments its internal address register until the full block of data is transferred.
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instead of system RAM. As a result, CPU caches are used as the primary source and destination for I/O, allowing
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1735:
1040:
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402:", and consequently block memory moves in the PC, limited by the general PIO speed of the CPU, were very slow.
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measures must be provided to put the processor into a hold condition so that bus contention does not occur.
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685:(I/OAT), which can offload memory copying from the main CPU, freeing it to do other work. In 2006, Intel's
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2211:
2150:
2005:
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962:
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1110:
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Internally, a multichannel DMA engine is usually present in the device to perform multiple concurrent
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808:(note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the
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2337:
857:
33:
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2318:
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2185:
1840:
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100:
93:
88:) is a feature of computer systems that allows certain hardware subsystems to access main system
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Standard DMA, also called third-party DMA, uses a DMA controller. A DMA controller can generate
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874:
654:
631:
50:
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A modern x86 CPU may use more than 4 GB of memory, either utilizing the native 64-bit mode of
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2139:
2092:
1948:
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861:
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Further performance-oriented enhancements to the DMA mechanism have been introduced in Intel
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processor) may benefit from software overlapping DMA memory operations with processing, via
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could still easily outstrip the 8237), as well as the development of further evolutions to (
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2135:
1988:
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938:
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125:
8:
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modes), Parallel Port (ECP capable port), certain SoundBlaster Clones like the OPTi 928
346:
176:
129:
2037:
1659:
1595:
1061:
1036:
950:
944:
923:
853:
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623:
345:, whereby external writes are signaled to the cache controller which then performs a
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operations, from the CPU to a dedicated DMA engine. An implementation example is the
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1357:
1081:
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744:
732:
332:
1900:
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1001:"DMA Fundamentals on various PC platforms, National Instruments, pages 6 & 7"
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89:
1510:
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regardless of the system's actual address space or amount of installed memory.
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386:/8088-standard) megabyte of RAM, and were limited to addressing single 64
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192:
136:
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As an example of DMA engine incorporated in a general-purpose CPU, some Intel
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1983:
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890:
658:
475:
244:
232:
113:
1507:, from A. F. Harvey and Data Acquisition Division Staff NATIONAL INSTRUMENTS
2010:
1953:
1805:
1710:
793:(in contrast to cache-coherent CMP architectures such as Intel's cancelled
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520:
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2020:
1958:
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prevented use of large (and fast, but uninterruptible) block transfers.
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infrared controller when FIR (fast infrared) mode is selected, and an
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2145:
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2107:
2042:
1917:
1705:
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809:
739:, typical system bus infrastructure is a complex on-chip bus such as
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508:
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483:
406:
292:
104:
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1835:
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1182:
953: – Electronic communication subsystem on an integrated circuit
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cards that needed to maintain full hardware compatibility with the
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only), user hardware for all others, usually sound card 16-bit DMA
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2252:
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1715:
1187:
1137:"Bus Specifics - Writing Device Drivers for Oracle® Solaris 11.3"
905:
698:
662:
455:
399:
1233:"Intel Data Direct I/O (Intel DDIO): Frequently Asked Questions"
622:-based PC, the southbridge will forward the transactions to the
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1557:, Embedded Linux Conference 2014, San Jose, by Laurent Pinchart
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is required in case of multiple masters present on the system.
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begin the transfer. When the transfer is complete, the device
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and initiate memory read or write cycles. It contains several
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1995:
1968:
1850:
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794:
666:
451:
447:
443:
423:
383:
379:
371:
1344:"Cell Multiprocessor Communication Network: Built for Speed"
1208:
Overview of I/OAT on Linux, with links to several benchmarks
908: – An integrated circuit for rapid data synchronization
432:
2221:
2206:
2067:
1978:
1973:
1815:
1060:. McGraw-Hill International Book Company. p. 426-427.
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678:
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to provide address translation services if one is present.
583:
573:
550:
491:
224:
220:
1161:"Physical Address Extension — PAE Memory and Windows"
398:. This prevented it from being used as a general-purpose "
2170:
1795:
1790:
920: – Cyberattack exploiting high-speed expansion ports
790:
500:
486:
devices on motherboards that often integrated a built-in
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of which channel 0 in the PC (& XT) was dedicated to
216:
124:. DMA is also used for intra-chip data transfer in some
928:
Pages displaying short descriptions of redirect targets
895:
Pages displaying short descriptions of redirect targets
709:) feature, allowing the DMA "windows" to reside within
1163:. Microsoft Windows Hardware Development Central. 2005
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CPU/bus architecture), could only address the first (
979:
Pages displaying wikidata descriptions as a fallback
843:μPD71071, capable of addressing a 16M-byte of memory
840:μPD71037, capable of addressing a 64K-byte of memory
914: – High-performance input/output architecture
995:
993:
211:Some examples of buses using third-party DMA are
2329:
1454:"pPD71037 Direct Memory Access (DMA) Controller"
971: – Data transfer method for ATA Hard drives
902: – MCU hardware feature for task offloading
450:meant that PIO transfers even by the 16-bit-bus
1913:Coherent Accelerator Processor Interface (CAPI)
1312:
965: – Low-level hardware direct memory access
431:monopolise the bus approximately every 15
1031:(2nd ed.). Osborne McGraw Hill. pp.
990:
947: – Computer memory management methodology
1576:
1335:
1195:
523:interrupt and data copy tasks from the CPU.
1259:
1108:
1005:Universidad Nacional de la Plata, Argentina
893: – Computer storage interface standard
556:User hardware, usually sound card 8-bit DMA
438:Due to their lagging performance (1.6
187:in the first series of this computer model.
1583:
1569:
1407:"Z80® DMA Direct Memory Access Controller"
877:, at the expense of needing a predictable
766:operations as programmed by the software.
1315:"Pushing the Limits of Kernel Networking"
1262:"Pushing the Limits of Kernel Networking"
1074:
959: – Process of device status sampling
727:Advanced Microcontroller Bus Architecture
657:(DOS/Windows nomenclature) also known as
69:Learn how and when to remove this message
1505:DMA Fundamentals on Various PC Platforms
1118:PC Architecture for Technicians: Level 1
1018:
163:
32:This article includes a list of general
1341:
1024:
2330:
1530:, Jonathan Corbet, Alessandro Rubini,
1201:
1180:
1058:Computer Architecture and Organization
268:
1564:
1181:Corbet, Jonathan (December 8, 2005).
1055:
977: – Microsoft DMA access standard
935: – Specialized computer hardware
681:chipsets include a DMA engine called
251:
1430:"Sharp 1986 Semiconductor Data Book"
805:
542:16-bit ISA permitted bus mastering.
18:
1082:"Intel 8237 & 8237-2 Datasheet"
926: – Method of CPU communication
413:(more familiarly retronymed as the
301:
99:Without DMA, when the CPU is using
13:
1384:"Am9517A Multimode DMA Controller"
941: – Processing data technology
815:
534:. These symbols, seen on hardware
314:
38:it lacks sufficient corresponding
14:
2369:
1548:
1528:Linux Device Drivers, 3rd Edition
1515:Linux Device Drivers, 2nd Edition
2314:
2313:
1555:Mastering the DMA and IOMMU APIs
780:As an example usage of DMA in a
331:memory version of X, assuming a
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238:
23:
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1399:
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900:Autonomous peripheral operation
579:Cascade to PC/XT DMA controller
175:computer (1990). The two large
1313:Alexander Duyck (2015-08-19).
1174:
1153:
1129:
1102:
1049:
545:Standard ISA DMA assignments:
415:Industry Standard Architecture
159:
1:
1908:Intel Ultra Path Interconnect
1542:DMA Modes & Bus Mastering
1342:Kistler, Michael (May 2006).
1202:Grover, Andrew (2006-06-01).
984:
847:
837:LH0083, compatible to Z80 DMA
782:multiprocessor-system-on-chip
715:network interface controllers
309:Hidden DMA data transfer mode
256:
154:
1886:Intel QuickPath Interconnect
1876:Direct Media Interface (DMI)
665:/Linux), or it could use an
7:
1183:"Memory copies in hardware"
963:Remote direct memory access
884:
683:I/O Acceleration Technology
356:
141:I/O Acceleration Technology
16:Feature of computer systems
10:
2374:
1871:Compute Express Link (CXL)
1537:DMA and Interrupt Handling
1517:, Alessandro Rubini &
1497:
1260:Rashid Khan (2015-09-29).
1109:Intel Corp. (2003-04-25),
957:Polling (computer science)
773:
724:
647:Physical Address Extension
2307:
2266:
2245:
2194:
2108:IEEE-1284 (parallel port)
2030:
2023:logical device interface)
1926:
1678:
1612:
1478:"µPD71071 DMA Controller"
858:digital signal processors
741:AMBA High-performance Bus
636:list of device bandwidths
1204:"I/OAT on LinuxNet wiki"
672:
143:. DMA is of interest in
769:
692:
572:modes, and replaced by
548:
462:) or replacements for (
101:programmed input/output
94:central processing unit
53:more precise citations.
2348:Computer storage buses
1670:List of bus bandwidths
1524:Memory Mapping and DMA
1056:Hayes, John.P (1978).
1025:Osborne, Adam (1980).
720:
701:processors with their
630:on the CPU die) using
597:
480:Sound Blaster standard
374:), there was only one
361:
188:
2353:Hardware acceleration
1111:"Chapter 12: ISA Bus"
933:Hardware acceleration
879:memory access pattern
804:DMA in Cell is fully
784:, IBM/Sony/Toshiba's
776:Cell (microprocessor)
618:As an example, on an
167:
126:multi-core processors
92:independently of the
2113:IEEE-1394 (FireWire)
1851:PCI Extended (PCI-X)
975:Virtual DMA Services
939:In-memory processing
651:Double Address Cycle
181:magneto-optical disc
130:processing circuitry
82:Direct memory access
1954:Parallel ATA (PATA)
1322:linuxfoundation.org
1089:JKbox RC702 subsite
795:general-purpose GPU
370:(and the follow-up
269:Cycle stealing mode
177:integrated circuits
149:in-memory computing
1861:PCI Express (PCIe)
1532:Greg Kroah-Hartman
1483:. p. 940(5g1)
1459:. p. 832(5b1)
1362:10.1109/MM.2006.49
553:Refresh (obsolete)
514:Scatter-gather or
347:cache invalidation
252:Modes of operation
197:hardware registers
189:
183:used instead of a
2325:
2324:
2311:
2038:Apple Desktop Bus
2015:PCI Express (via
1974:Serial ATA (SATA)
1660:Network on a chip
1435:. p. 255-269
1033:5–64 through 5–93
951:Network on a chip
945:Memory management
924:Memory-mapped I/O
856:and DMA (such as
854:scratchpad memory
733:systems-on-a-chip
624:memory controller
227:; however, their
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78:
71:
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1771:HP Precision Bus
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1248:
1247:
1237:
1229:
1223:
1222:
1220:
1219:
1210:. Archived from
1199:
1193:
1192:
1178:
1172:
1171:
1169:
1168:
1157:
1151:
1150:
1148:
1147:
1133:
1127:
1126:
1125:
1124:
1115:
1106:
1100:
1099:
1097:
1095:
1086:
1078:
1072:
1071:
1053:
1047:
1046:
1022:
1016:
1015:
1013:
1011:
997:
980:
929:
896:
866:double buffering
852:Processors with
737:embedded systems
532:Data acknowledge
428:segment boundary
366:In the original
333:write-back cache
326:DMA can lead to
323:
302:Transparent mode
229:host controllers
193:memory addresses
74:
67:
63:
60:
54:
49:this article by
40:inline citations
27:
26:
19:
2373:
2372:
2368:
2367:
2366:
2364:
2363:
2362:
2338:Computer memory
2328:
2327:
2326:
2321:
2312:
2303:
2262:
2241:
2190:
2103:IEEE-488 (GPIB)
2026:
1922:
1901:Infinity Fabric
1731:Europe Card Bus
1674:
1608:
1589:
1551:
1546:
1519:Jonathan Corbet
1500:
1495:
1486:
1484:
1480:
1476:
1475:
1471:
1462:
1460:
1456:
1452:
1451:
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1438:
1436:
1432:
1428:
1427:
1423:
1414:
1412:
1409:
1405:
1404:
1400:
1391:
1389:
1386:
1382:
1381:
1377:
1340:
1336:
1327:
1325:
1317:
1311:
1307:
1298:
1296:
1288:
1284:
1283:
1279:
1270:
1268:
1258:
1254:
1245:
1243:
1235:
1231:
1230:
1226:
1217:
1215:
1200:
1196:
1179:
1175:
1166:
1164:
1159:
1158:
1154:
1145:
1143:
1141:docs.oracle.com
1135:
1134:
1130:
1122:
1120:
1113:
1107:
1103:
1093:
1091:
1084:
1080:
1079:
1075:
1068:
1054:
1050:
1043:
1023:
1019:
1009:
1007:
999:
998:
991:
987:
978:
927:
894:
887:
875:burst transfers
850:
818:
816:DMA Controllers
778:
772:
729:
723:
703:Data Direct I/O
695:
675:
600:
595:
526:DRQ stands for
490:controller, an
409:, the enhanced
364:
359:
328:cache coherency
317:
315:Cache coherency
304:
271:
259:
254:
241:
185:hard disk drive
162:
157:
151:architectures.
145:network-on-chip
75:
64:
58:
55:
45:Please help to
44:
28:
24:
17:
12:
11:
5:
2371:
2361:
2360:
2355:
2350:
2345:
2340:
2323:
2322:
2308:
2305:
2304:
2302:
2301:
2296:
2291:
2281:
2276:
2270:
2268:
2264:
2263:
2261:
2260:
2255:
2249:
2247:
2243:
2242:
2240:
2239:
2234:
2229:
2224:
2219:
2214:
2212:Intel HD Audio
2209:
2204:
2202:ADAT Lightpipe
2198:
2196:
2192:
2191:
2189:
2188:
2183:
2178:
2173:
2168:
2163:
2158:
2153:
2148:
2143:
2125:
2120:
2115:
2110:
2105:
2100:
2095:
2090:
2085:
2080:
2075:
2070:
2065:
2060:
2055:
2050:
2045:
2040:
2034:
2032:
2028:
2027:
2025:
2024:
2013:
2008:
2003:
1998:
1993:
1992:
1991:
1986:
1976:
1971:
1966:
1961:
1956:
1951:
1946:
1941:
1936:
1930:
1928:
1924:
1923:
1921:
1920:
1915:
1910:
1905:
1904:
1903:
1896:HyperTransport
1893:
1888:
1883:
1878:
1873:
1868:
1863:
1858:
1853:
1848:
1843:
1838:
1833:
1828:
1823:
1818:
1813:
1808:
1803:
1798:
1793:
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1743:
1738:
1733:
1728:
1723:
1718:
1713:
1708:
1703:
1698:
1693:
1688:
1682:
1680:
1676:
1675:
1673:
1672:
1667:
1662:
1657:
1652:
1650:Bus contention
1647:
1642:
1637:
1632:
1627:
1625:Front-side bus
1622:
1616:
1614:
1610:
1609:
1606:computer buses
1588:
1587:
1580:
1573:
1565:
1559:
1558:
1550:
1549:External links
1547:
1545:
1544:
1539:
1534:
1521:
1511:mmap() and DMA
1508:
1501:
1499:
1496:
1494:
1493:
1469:
1445:
1421:
1398:
1375:
1334:
1305:
1293:solarflare.com
1277:
1252:
1224:
1194:
1173:
1152:
1128:
1101:
1073:
1066:
1048:
1041:
1017:
988:
986:
983:
982:
981:
972:
966:
960:
954:
948:
942:
936:
930:
921:
915:
909:
903:
897:
886:
883:
871:memory latency
849:
846:
845:
844:
841:
838:
835:
832:
827:
824:
817:
814:
810:standard sense
806:cache coherent
786:Cell processor
774:Main article:
771:
768:
764:scatter-gather
725:Main article:
722:
719:
694:
691:
674:
671:
659:bounce buffers
655:double buffers
599:
596:
594:
593:
590:
587:
580:
577:
568:(obsoleted by
563:
557:
554:
547:
393:dynamic memory
363:
360:
358:
355:
316:
313:
303:
300:
276:cycle stealing
270:
267:
258:
255:
253:
250:
240:
237:
161:
158:
156:
153:
137:scatter-gather
114:graphics cards
77:
76:
31:
29:
22:
15:
9:
6:
4:
3:
2:
2370:
2359:
2356:
2354:
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2346:
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2341:
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2336:
2335:
2333:
2320:
2306:
2300:
2297:
2295:
2292:
2289:
2285:
2282:
2280:
2277:
2275:
2274:Multidrop bus
2272:
2271:
2269:
2265:
2259:
2256:
2254:
2251:
2250:
2248:
2244:
2238:
2235:
2233:
2230:
2228:
2225:
2223:
2220:
2218:
2215:
2213:
2210:
2208:
2205:
2203:
2200:
2199:
2197:
2193:
2187:
2184:
2182:
2181:External PCIe
2179:
2177:
2174:
2172:
2169:
2167:
2164:
2162:
2161:Parallel SCSI
2159:
2157:
2154:
2152:
2149:
2147:
2144:
2141:
2137:
2133:
2129:
2126:
2124:
2121:
2119:
2116:
2114:
2111:
2109:
2106:
2104:
2101:
2099:
2096:
2094:
2091:
2089:
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2084:
2081:
2079:
2076:
2074:
2071:
2069:
2066:
2064:
2061:
2059:
2056:
2054:
2053:Commodore bus
2051:
2049:
2046:
2044:
2041:
2039:
2036:
2035:
2033:
2029:
2022:
2018:
2014:
2012:
2009:
2007:
2004:
2002:
2001:Fibre Channel
1999:
1997:
1994:
1990:
1987:
1985:
1982:
1981:
1980:
1977:
1975:
1972:
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1709:
1707:
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1702:
1699:
1697:
1694:
1692:
1689:
1687:
1684:
1683:
1681:
1677:
1671:
1668:
1666:
1665:Plug and play
1663:
1661:
1658:
1656:
1655:Bus mastering
1653:
1651:
1648:
1646:
1643:
1641:
1638:
1636:
1633:
1631:
1630:Back-side bus
1628:
1626:
1623:
1621:
1618:
1617:
1615:
1611:
1607:
1604:
1600:
1598:
1593:
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1581:
1579:
1574:
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1567:
1566:
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1502:
1479:
1473:
1455:
1449:
1431:
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1408:
1402:
1385:
1379:
1371:
1367:
1363:
1359:
1355:
1351:
1350:
1345:
1338:
1323:
1316:
1309:
1294:
1287:
1281:
1267:
1263:
1256:
1241:
1234:
1228:
1214:on 2016-05-05
1213:
1209:
1205:
1198:
1190:
1189:
1184:
1177:
1162:
1156:
1142:
1138:
1132:
1119:
1112:
1105:
1090:
1083:
1077:
1069:
1067:0-07-027363-4
1063:
1059:
1052:
1044:
1038:
1034:
1030:
1029:
1021:
1006:
1002:
996:
994:
989:
976:
973:
970:
967:
964:
961:
958:
955:
952:
949:
946:
943:
940:
937:
934:
931:
925:
922:
919:
916:
913:
910:
907:
904:
901:
898:
892:
891:AT Attachment
889:
888:
882:
880:
876:
872:
867:
863:
859:
855:
842:
839:
836:
833:
831:
828:
825:
823:
820:
819:
813:
811:
807:
802:
800:
796:
792:
787:
783:
777:
767:
765:
760:
758:
754:
748:
746:
742:
738:
734:
728:
718:
716:
712:
708:
704:
700:
690:
688:
684:
680:
670:
668:
664:
660:
656:
652:
648:
644:
639:
637:
633:
629:
625:
621:
616:
613:
609:
605:
592:User hardware
591:
589:User hardware
588:
585:
581:
578:
575:
571:
567:
564:
561:
558:
555:
552:
549:
546:
543:
540:
537:
533:
529:
524:
522:
517:
512:
510:
504:
502:
497:
493:
489:
485:
481:
477:
476:Sound Blaster
473:
469:
465:
461:
457:
453:
449:
445:
441:
436:
434:
429:
425:
420:
416:
412:
408:
403:
401:
397:
394:
389:
385:
381:
377:
373:
369:
354:
351:
348:
344:
339:
336:
334:
329:
324:
322:
312:
310:
299:
296:
294:
288:
286:
279:
277:
266:
264:
249:
246:
245:bus mastering
239:Bus mastering
236:
234:
233:bus mastering
230:
226:
222:
218:
214:
209:
206:
201:
198:
194:
186:
182:
178:
174:
170:
166:
152:
150:
146:
142:
138:
133:
131:
127:
123:
119:
118:network cards
115:
112:controllers,
111:
106:
102:
97:
95:
91:
87:
83:
73:
70:
62:
52:
48:
42:
41:
35:
30:
21:
20:
2358:Input/output
1806:TURBOchannel
1596:
1527:
1514:
1485:. Retrieved
1472:
1461:. Retrieved
1448:
1437:. Retrieved
1424:
1413:. Retrieved
1401:
1390:. Retrieved
1378:
1356:(3): 10–23.
1353:
1347:
1337:
1326:. Retrieved
1321:
1308:
1297:. Retrieved
1295:. 2012-06-07
1292:
1280:
1269:. Retrieved
1265:
1255:
1244:. Retrieved
1242:. March 2012
1227:
1216:. Retrieved
1212:the original
1207:
1197:
1186:
1176:
1165:. Retrieved
1155:
1144:. Retrieved
1140:
1131:
1121:, retrieved
1117:
1104:
1092:. Retrieved
1088:
1076:
1057:
1051:
1027:
1020:
1008:. Retrieved
1004:
873:and exploit
851:
803:
779:
761:
749:
730:
706:
702:
699:Xeon E5
696:
687:Linux kernel
676:
645:CPU, or the
640:
617:
601:
544:
541:
531:
528:Data request
527:
525:
521:input/output
516:vectored I/O
513:
505:
437:
418:
404:
365:
352:
343:bus snooping
340:
337:
325:
318:
308:
305:
290:
282:
274:
272:
262:
260:
242:
210:
202:
190:
134:
98:
85:
81:
80:
65:
56:
37:
2343:Motherboard
2279:CoreConnect
2258:ExpressCard
2186:Thunderbolt
2176:Camera Link
1959:Bus and Tag
1645:Address bus
1640:Control bus
1635:Daisy chain
1324:. p. 5
912:Channel I/O
753:tri-stating
582:Hard Disk (
560:Floppy disk
530:; DACK for
488:floppy disk
419:controlling
285:Bus Request
169:Motherboard
160:Third-party
122:sound cards
51:introducing
2332:Categories
2132:ACCESS.bus
2031:Peripheral
1831:InfiniBand
1826:HP GSC bus
1620:System bus
1487:2024-01-05
1463:2024-01-06
1439:2024-01-13
1415:2024-01-07
1392:2024-01-06
1349:IEEE Micro
1328:2015-10-11
1299:2015-10-11
1271:2015-10-11
1266:redhat.com
1246:2015-10-11
1218:2006-12-12
1167:2008-04-07
1146:2020-12-18
1123:2015-01-27
1042:0931988349
985:References
918:DMA attack
848:Pipelining
830:Intel 8237
822:Intel 8257
711:CPU caches
628:integrated
626:(which is
620:Intel Core
608:bus master
562:controller
536:schematics
509:interrupts
376:Intel 8237
263:burst mode
257:Burst mode
155:Principles
110:disk drive
34:references
2093:Lightning
2043:Atari SIO
1918:SpaceWire
1751:Zorro III
1691:S-100 bus
1686:SS-50 bus
1679:Standards
1599:standards
1592:Technical
612:arbitrate
566:Hard disk
511:the CPU.
496:IEEE 1284
484:Super I/O
407:IBM PC/AT
405:With the
293:Bus Grant
105:interrupt
2319:Category
2294:Wishbone
2267:Embedded
2246:Portable
2166:Profibus
2098:DMX512-A
1984:Parallel
1836:Ethernet
1746:Zorro II
1696:Multibus
1597:de facto
1094:20 April
1010:20 April
885:See also
860:and the
799:Larrabee
357:Examples
219:(before
173:NeXTcube
59:May 2023
2299:SLIMbus
2253:PC Card
2237:TOSLINK
1927:Storage
1881:RapidIO
1761:FASTBUS
1716:STD Bus
1613:General
1526:, from
1513:, from
1498:Sources
1370:7735690
1188:LWN.net
906:Blitter
834:Z80 DMA
757:arbiter
663:FreeBSD
400:Blitter
396:refresh
223:), and
96:(CPU).
47:improve
2232:S/PDIF
2123:1-Wire
2088:RS-485
2083:RS-423
2078:RS-422
2073:RS-232
1934:ST-506
1891:NVLink
1741:STEbus
1701:Unibus
1368:
1064:
1039:
826:Am9517
643:x86-64
482:; and
411:AT bus
368:IBM PC
90:memory
36:, but
2227:McASP
2195:Audio
2140:SMBus
2136:PMBus
2118:UNI/O
2058:HP-IL
2011:SATAe
1996:ESCON
1969:HIPPI
1801:NuBus
1756:CAMAC
1726:Q-Bus
1721:SMBus
1706:VAXBI
1603:wired
1481:(PDF)
1457:(PDF)
1433:(PDF)
1410:(PDF)
1387:(PDF)
1366:S2CID
1318:(PDF)
1289:(PDF)
1240:Intel
1236:(PDF)
1114:(PDF)
1085:(PDF)
673:I/OAT
667:IOMMU
456:386SX
448:80186
444:80386
424:80286
384:i8086
380:i8088
372:PC/XT
243:In a
205:words
171:of a
2284:AMBA
2222:MADI
2207:AES3
2068:MIDI
2021:NVMe
2017:AHCI
1979:SCSI
1964:DSSI
1939:ESDI
1816:SBus
1776:EISA
1711:MBus
1601:for
1594:and
1096:2019
1062:ISBN
1037:ISBN
1012:2019
969:UDMA
862:Cell
770:Cell
735:and
707:DDIO
693:DDIO
679:Xeon
584:PS/2
574:UDMA
551:DRAM
492:IrDA
470:and
460:EISA
454:and
291:BG (
289:and
283:BR (
278:mode
273:The
231:use
225:SATA
221:USB4
213:PATA
147:and
120:and
2288:AXI
2217:I²S
2171:USB
2156:D²B
2151:SPI
2146:I3C
2128:I²C
2063:HIL
2048:DCB
2019:or
2006:SSA
1989:SAS
1949:SMD
1944:IPI
1866:AGP
1856:PXI
1846:PCI
1841:UPA
1821:VLB
1811:MCA
1796:VPX
1791:VXS
1786:VXI
1781:VME
1766:LPC
1736:ISA
1358:doi
801:).
791:CPU
745:ARM
731:In
721:AHB
638:).
632:DMI
604:PCI
598:PCI
570:PIO
501:RAM
472:PCI
468:VLB
464:MCA
452:286
362:ISA
311:".
261:In
217:USB
86:DMA
2334::
2138:,
2134:,
1364:.
1354:26
1352:.
1346:.
1320:.
1291:.
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