1024:
1059:
290:
technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance. DDR2 started to become competitive against the older DDR standard by the end of 2004, as modules with lower latencies became available.
320:
312:
304:
39:
328:
received or transmitted its data over the data bus in two data bus clock cycles (each clock cycle transferred two bits of data). Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data could be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array could be accessed. DDR2 SDRAM was designed with such a scheme to avoid an excessive increase in power consumption.
270:. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules. The maximum capacity on commercially available DDR2 DIMMs is 8GB, but chipset support and availability for those DIMMs is sparse and more common 2GB per DIMM are used.
1019:
DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory
289:
DDR2 was officially introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR
1169:
was commonly used in graphics cards and some tablet PCs. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use "GDDR2". These cards actually use standard DDR2 chips designed for use as main system memory although operating
1121:
DDR2 DIMMs are not backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin SO-DIMMs for DDR and DDR2; however, the notch
366:
Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest
343:
is greatly increased as a trade-off. The DDR2 prefetch buffer is four bits deep, whereas it is two bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is
327:
The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length was two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits were read or written to or from a four-bit-deep prefetch queue. This queue
370:
According to JEDEC the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring
1111:
The highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (bus clock rate) for the best PC2-8500 modules is
1011:
Some manufacturers label their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the respective names suggested by JEDEC. At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate whilst others simply round up for the
1065:
Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional
1050:, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200 ECC is a PC2-4200 module with ECC. An additional
259:), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.
1097:
do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their
1289:
262:
Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same
1148:
graphics card. However, this GDDR2 memory used on graphics cards is not DDR2 per se, but rather an early midpoint between DDR and DDR2 technologies. Using "DDR2" to refer to GDDR2 is a
1170:
with higher latencies to achieve higher clock rates. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards.
1553:
1450:
1125:
Higher-speed DDR2 DIMMs can be mixed with lower-speed DDR2 DIMMs, although the memory controller will operate all DIMMs at same speed as the lowest-speed DIMM present.
1290:
https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/modules/parity_rdimm/htf36c256_512_1gx72pz.pdf?rev=e8e3928f09794d61809f92abf36bfb24
1514:
1558:
1155:. In particular, the performance-enhancing doubling of the I/O clock rate is missing. It had severe overheating issues due to the nominal DDR voltages.
1266:
286:
standards organization presented
Samsung with its Technical Recognition Award for the company's efforts in developing and standardizing DDR2.
1868:
1302:
1020:
modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
1873:
347:
Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble
1632:
1624:
217:
66:
1082:
in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the same module but with additional ECC.
1904:
1536:
Note**: JEDEC website requires registration ($ 2,500 membership) for viewing or downloading of these documents:
1585:
1525:
1331:
Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100 MHz) = 10 ns per clock cycle.
344:
between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.
1734:
1594:
1501:"JEDEC Standard No. 21C: 4.20.13 240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification"
1273:
1023:
1210:
1112:
comparable to that of 10 ns = 4 / (bus clock rate) for the best PC-3200 modules.
1238:
1141:
and introduced in July 2002. The first commercial product to claim using the "DDR2" technology was the
1190:
391:
in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth).
221:
1425:
1376:
1863:
1438:
1306:
245:
1686:
1412:
1363:
465:
263:
241:
1058:
1847:
1489:
457:
160:
1878:
363:. This packaging change was necessary to maintain signal integrity at higher bus speeds.
8:
1455:
1195:
1163:, which is based on DDR2 SDRAM, though with several additions suited for graphics cards.
1086:
319:
1054:
can be added at the end of the designation, P standing for parity (ex : PC2-5300P).
1718:
1578:
332:
1563:
1341:
1205:
1071:
371:
permanent damage (although they may not actually function correctly at that level).
228:
standard (JESD79-2); first published in
September 2003. DDR2 succeeded the original
1390:
1319:
1156:
403:
213:
1670:
408:
348:
336:
252:
147:
311:
1899:
1108:
Registered and un-buffered SDRAM generally cannot be mixed on the same channel.
413:
340:
267:
303:
255:
as in DDR SDRAM (transferring data on the rising and falling edges of the bus
16:
Second generation of double-data-rate synchronous dynamic random-access memory
1893:
1824:
1739:
1571:
1149:
38:
1537:
1500:
1494:
1485:
1451:"Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics"
256:
1784:
1779:
1774:
1769:
1764:
1759:
1184:
1122:
on DDR2 modules is in a slightly different position than on DDR modules.
487:
1754:
1657:
1652:
1647:
1215:
1145:
1134:
1047:
444:
429:
233:
197:
125:
43:
Front and back of a 2GB PC2-5300 DDR2 RAM module for desktop PCs (DIMM)
331:
DDR2's bus frequency is boosted by electrical interface improvements,
1814:
1637:
1179:
360:
356:
229:
187:
1809:
1614:
1609:
1559:
DDR2 low latency vs high bandwidth, Core 2 Duo (Conroe) performance
1243:
1152:
1486:
JEDEC standard: DDR2 SDRAM Specification: JESD79-2F, November 2009
1842:
1706:
1460:
1200:
1138:
384:
279:
172:
52:
1796:
1681:
1142:
323:
Comparison of memory modules for portable/mobile PCs (SO-DIMM)
1804:
1749:
1744:
1711:
1696:
1676:
1664:
1506:
1397:
1348:
1166:
1160:
1042:
In addition to bandwidth and capacity variants, modules can:
352:
283:
225:
56:
1837:
1832:
1701:
1691:
1239:"Samsung Demonstrates World's First DDR 3 Memory Prototype"
470:
380:
237:
206:
Double Data Rate 2 Synchronous
Dynamic Random-Access Memory
23:
Double Data Rate 2 Synchronous
Dynamic Random-Access Memory
434:
387:
have 200 pins and often come identified by an additional
30:
1490:
http://www.jedec.org/standards-documents/docs/jesd-79-2e
1593:
1548:
383:
with 240 pins and a single locating notch. Laptop DDR2
1070:
in their designation, whereas non-registered (a.k.a. "
1159:
has since designed the GDDR technology further into
355:package of the previous memory generations such as
315:
Comparison of memory modules for desktop PCs (DIMM)
736:Relative speed comparison between similar modules
1891:
379:For use in computers, DDR2 SDRAM is supplied in
1512:
1579:
1300:
1515:"DDR2 SDRAM interfaces for next-gen systems"
1187:(definition of "CAS 5-5-5-15", for example)
232:specification, and was itself succeeded by
1586:
1572:
1128:
37:
1116:
1538:http://www.jedec.org/standards-documents
1057:
1022:
318:
310:
302:
218:synchronous dynamic random-access memory
67:Synchronous dynamic random-access memory
251:In addition to double pumping the data
1892:
1233:
1231:
1567:
1439:Mushkin PC2-5300 vs. Corsair PC2-5400
679:
625:
582:
539:
496:
412:
407:
402:
399:
307:PC2-5300 DDR2 SO-DIMM (for notebooks)
1305:. X-bit Laboratories. Archived from
374:
1228:
1062:Intel ® 6402 Advanced Memory Buffer
395:Comparison of DDR2 SDRAM standards
13:
1509:Solid State Technology Association
1479:
14:
1916:
1542:
1089:modules, which are designated by
278:DDR2 SDRAM was first produced by
293:
1443:
1267:"JEDEC Publishes DDR2 Standard"
1038:DIMM's Notch Positions compared
339:and off-chip drivers. However,
1432:
1383:
1334:
1325:
1313:
1303:"DDR2 vs. DDR: Revenge gained"
1294:
1283:
1259:
1:
1554:Overview of DDR-II technology
1322:(section 5, tables 15 and 16)
1221:
1595:Dynamic random-access memory
1522:Electronic Engineering Times
1391:"SPECIALITY DDR2-1066 SDRAM"
1272:. 2003-09-12. Archived from
1078:identified by an additional
7:
1211:List of interface bit rates
1173:
351:package as compared to the
298:
10:
1921:
1342:"DDR2 SDRAM SPECIFICATION"
273:
1856:
1823:
1795:
1727:
1623:
1602:
1495:JEDEC standard: DDR2-1066
1191:Dual-channel architecture
745:
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72:
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36:
28:
1905:South Korean inventions
1129:Relation to GDDR memory
1420:Cite journal requires
1371:Cite journal requires
1117:Backward compatibility
1063:
1039:
367:available data rates.
324:
316:
308:
282:in 2001. In 2003, the
86:; 21 years ago
1061:
1046:Optionally implement
1026:
322:
314:
306:
1513:Razak Mohammed Ali.
117:DDR2-1066 (PC2-8500)
1456:Samsung Electronics
1400:. November 2007: 70
1301:Ilya Gavrichenkov.
1196:Fully Buffered DIMM
1137:, was developed by
737:
396:
246:backward compatible
114:DDR2-800 (PC2-6400)
111:DDR2-667 (PC2-5333)
108:DDR2-533 (PC2-4266)
105:DDR2-400 (PC2-3200)
25:
1719:Hybrid Memory Cube
1247:. 17 February 2005
1064:
1040:
735:
394:
333:on-die termination
325:
317:
309:
242:forward compatible
19:
1887:
1886:
1206:Registered memory
1133:GDDR2, a form of
1007:
1006:
733:
732:
474:
375:Chips and modules
203:
202:
1912:
1879:Transistor count
1588:
1581:
1574:
1565:
1564:
1532:
1530:
1524:. Archived from
1519:
1473:
1472:
1470:
1468:
1463:. 23 August 2003
1447:
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1429:
1423:
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1405:
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1380:
1374:
1369:
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1357:
1356:
1351:. April 2008: 78
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492:
468:
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397:
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337:prefetch buffers
266:but with better
214:double data rate
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92:
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41:
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18:
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1911:
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1671:Fast Cycle DRAM
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1482:
1480:Further reading
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1146:GeForce FX 5800
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5:
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1869:SDRAM timeline
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1825:Memory modules
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1543:External links
1541:
1534:
1533:
1531:on 2007-09-26.
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1474:
1442:
1431:
1422:|journal=
1382:
1373:|journal=
1333:
1324:
1320:JEDEC JESD 208
1312:
1309:on 2006-11-21.
1293:
1282:
1279:on 2003-12-04.
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1087:fully buffered
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989:
988:PC2-8500 5-5-5
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968:PC2-8500 6-6-6
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948:PC2-8500 7-7-7
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928:PC2-6400 4-4-4
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244:with DDR3 nor
236:in 2007. DDR2
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91:September 2003
84:September 2003
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1864:DRAM timeline
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458:Transfer rate
446:
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418:
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405:
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294:Specification
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166:400–1066 MT/s
164:
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161:Transfer rate
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1667:(Mobile DDR)
1642:
1603:Asynchronous
1535:
1526:the original
1521:
1465:. Retrieved
1454:
1445:
1434:
1413:cite journal
1402:. Retrieved
1385:
1364:cite journal
1353:. Retrieved
1336:
1327:
1315:
1307:the original
1296:
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1274:the original
1261:
1249:. Retrieved
1242:
1165:
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261:
257:clock signal
250:
240:are neither
209:
205:
204:
81:Release date
1625:Synchronous
1185:CAS latency
488:CAS latency
451:Clock rate
441:Cycle time
184:Predecessor
154:200–533 MHz
131:100–266 MHz
1894:Categories
1404:2009-03-14
1355:2009-03-14
1222:References
1216:DDR3 SDRAM
1150:colloquial
1135:GDDR SDRAM
1098:insertion.
1072:unbuffered
686:PC2-8500*
680:DDR2-1066
589:PC2-5300*
546:PC2-4200*
430:Clock rate
248:with DDR.
234:DDR3 SDRAM
224:. It is a
210:DDR2 SDRAM
198:DDR3 SDRAM
150:clock rate
141:10–3.75 ns
137:Cycle time
126:Clock rate
73:Generation
20:DDR2 SDRAM
1874:Bandwidth
1815:XDR2 DRAM
1638:DDR SDRAM
1180:DDR SDRAM
1085:Be aware
675:12 or 15
632:PC2-6400
626:DDR2-800
621:12 or 15
583:DDR2-667
540:DDR2-533
503:PC2-3200
497:DDR2-400
466:Bandwidth
420:Standard
361:SDR SDRAM
357:DDR SDRAM
264:bandwidth
230:DDR SDRAM
222:interface
194:Successor
188:DDR SDRAM
99:Standards
49:Developer
1810:XDR DRAM
1728:Graphics
1615:EDO DRAM
1610:FPM DRAM
1244:Phys.org
1174:See also
1153:misnomer
746:PC-6400
743:PC-5300
385:SO-DIMMs
299:Overview
220:(SDRAM)
29:Type of
1843:UniDIMM
1707:HBM-PIM
1673:(FCRAM)
1467:26 June
1461:Samsung
1251:23 June
1201:SO-DIMM
1139:Samsung
1074:") RAM
729:13.125
426:Module
414:Timings
341:latency
280:Samsung
274:History
268:latency
212:) is a
173:Voltage
89: (
53:Samsung
1797:Rambus
1682:RLDRAM
1597:(DRAM)
1143:Nvidia
1076:may be
1036:Server
763:4-4-4
760:5-5-5
757:6-6-6
754:4-4-4
751:5-5-5
726:7-7-7
718:11.25
715:6-6-6
707:9.375
704:5-5-5
672:6-6-6
661:5-5-5
650:4-4-4
618:5-5-5
607:4-4-4
575:4-4-4
567:11.25
564:3-3-3
532:4-4-4
521:3-3-3
461:(MT/s)
216:(DDR)
1900:SDRAM
1857:Lists
1805:RDRAM
1785:GDDR7
1780:GDDR6
1775:GDDR5
1770:GDDR4
1765:GDDR3
1760:GDDR2
1750:SGRAM
1745:MDRAM
1712:HBM3E
1697:HBM2E
1677:eDRAM
1665:LPDDR
1633:SDRAM
1529:(PDF)
1518:(PDF)
1507:JEDEC
1398:JEDEC
1394:(PDF)
1349:JEDEC
1345:(PDF)
1277:(PDF)
1270:(PDF)
1167:GDDR3
1161:GDDR3
1103:Note:
1027:DDR2
1017:Note:
1012:name.
701:8533
698:1066
692:3.75
664:12.5
647:6400
604:5333
561:4266
518:3200
453:(MHz)
423:Type
400:Name
381:DIMMs
353:TSSOP
284:JEDEC
238:DIMMs
226:JEDEC
178:1.8 V
57:JEDEC
1848:CAMM
1838:DIMM
1833:SIMM
1755:GDDR
1740:WRAM
1735:VRAM
1702:HBM3
1692:HBM2
1658:DDR5
1653:DDR4
1648:DDR3
1643:DDR2
1469:2019
1426:help
1377:help
1253:2019
1000:−24%
997:−37%
977:−25%
957:−12%
940:−20%
937:−33%
917:−16%
900:+20%
877:−19%
860:+21%
837:−24%
820:+21%
800:+20%
780:+60%
777:+33%
695:533
689:266
644:800
641:400
635:200
601:667
598:333
592:166
558:533
555:266
552:7.5
549:133
515:400
512:200
506:100
491:(ns)
477:CL-T
471:MB/s
404:Chip
359:and
63:Type
1687:HBM
1488:**
1157:ATI
1093:or
1048:ECC
1031:vs
980:−9%
960:+6%
880:−3%
840:−9%
653:10
610:12
578:12
535:20
524:15
509:10
479:RCD
435:MHz
409:Bus
349:BGA
253:bus
148:Bus
31:RAM
1896::
1520:.
1503:**
1497:**
1459:.
1453:.
1417::
1415:}}
1411:{{
1396:.
1368::
1366:}}
1362:{{
1241:.
1230:^
1095:FB
1009:*
1003:%
983:%
963:%
943:%
923:%
903:%
883:%
863:%
843:%
823:%
803:%
783:%
723:F
712:E
683:D
669:E
658:D
638:5
629:C
615:D
595:6
586:C
572:C
543:B
529:C
500:B
483:RP
481:-T
445:ns
335:,
1587:e
1580:t
1573:v
1471:.
1428:)
1424:(
1407:.
1379:)
1375:(
1358:.
1255:.
1091:F
1080:U
1068:R
1052:P
1033:F
1029:P
994:%
991:%
974:%
971:%
954:%
951:%
934:%
931:%
920:=
914:%
911:%
897:=
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857:=
854:%
851:%
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817:=
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811:%
797:=
794:%
791:%
774:%
771:%
473:)
469:(
447:)
443:(
437:)
433:(
389:S
208:(
93:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
