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DRAM connects to the microprocessor over a parallel bus. In 2015, the present standard is DDR3, a third generation of double-data rate memory bus operating at 1.5 V. Typical motherboards now come with two DDR3 channels so they can simultaneously access two banks of memory modules. DDR4 is ...
167:, in which each memory channel accesses two RAM modules simultaneously. The two technologies are independent of each other and many motherboards use both, by using DDR memory in a dual channel configuration.
234:, the product of the transfer rate and the bus width in bytes. DDR SDRAM operating with a 100 MHz clock is called DDR-200 (after its 200 MT/s data transfer rate), and a 64-bit (8-byte) wide
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operated at that data rate is called PC-1600, after its 1600 MB/s peak (theoretical) bandwidth. Likewise, 12.8 GB/s transfer rate DDR3-1600 is called PC3-12800.
97:. This, however, requires that the clock signal changes twice per transfer, while the data lines change at most once per transfer. When operating at a high bandwidth,
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processors. It is more recently being used for other systems with high data transfer speed requirements – as an example, for the output of
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105:. By using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate.
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DDR SDRAM uses double-data-rate signalling only on the data lines. Address and control signals are still sent to the DRAM once per clock
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224:", but many refer casually to a "1000 MHz bus," even though no signal cycles faster than 500 MHz.
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Describing the bandwidth of a double-pumped bus can be confusing. Each clock edge is referred to as a
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33:. The dots are where data transfers take place, measured in millions of transfers per second (MT/s).
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per second. Careful usage generally talks about "500 MHz, double data rate" or "1000
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Harris, Sarah L.; Harris, David Money (2016). "I/O Systems: 9.6.3 DDR3 Memory".
407:(to be precise, on the rising edge of the clock), and timing parameters such as
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uses two 7-bit double data rate command/address buses to each DIMM, where a
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are specified in clock cycles. Some less common DRAM interfaces, notably
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is to make it perform one transfer per full cycle (rise and fall) of a
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clock driver chip converts to a 14-bit SDR bus to each memory chip.
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by transferring data twice per clock cycle. This is also known as
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that transfers data on both the rising and falling edges of the
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popularized the technique of referring to the bus bandwidth in
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Some examples of popular designations of DDR modules:
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216:per second, but many people refer to the number of
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108:This technique has been used for microprocessor
512:Hennessy, John L.; Patterson, David A. (2007).
515:Computer architecture: a quantitative approach
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518:. Amsterdam: Morgan Kaufmann. p. 314.
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541:Digital Design and Computer Architecture
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89:The simplest way to design a clocked
543:. Elsevier. p. 531.e1–531.e64.
577:"double data rate (DDR) Definition"
190:Relation of bandwidth and frequency
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549:10.1016/b978-0-12-800056-4.00015-7
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163:DDR should not be confused with
101:limitations constrain the clock
16:Method of computer bus operation
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625:(data sheet). Analog Devices.
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178:. This tactic was chosen by
170:An alternative to double or
158:analog-to-digital converters
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602:"PCI Express Battles PCI-X"
483:List of interface bit rates
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488:Pumping (computer systems)
77:is used in the context of
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261:Theoretical bandwidth
200:, with two beats (one
57:and hence doubles the
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564:operating at 1.2V ...
385:DDR5-6400, PC5-51200
368:DDR5-4800, PC5-38400
351:DDR4-3200, PC4-25600
334:DDR4-2400, PC4-19200
317:DDR3-1600, PC3-12800
25:A comparison between
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606:Tom's Hardware Guide
232:megabytes per second
174:is to make the link
124:), graphics memory (
643:Digital electronics
300:DDR2-800, PC2-6400
116:, expansion buses (
91:electronic circuit
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600:Schmid, Patrick.
558:978-0-12-800056-4
525:978-0-12-370490-0
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283:DDR-400, PC-3200
266:DDR-200, PC-1600
110:front-side busses
79:NAND flash memory
71:double transition
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257:Transfer rate
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63:double pumped
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648:Clock signal
620:"AD9467 ADC"
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584:. Retrieved
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250:Memory clock
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172:quad pumping
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165:dual channel
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114:Ultra-3 SCSI
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95:clock signal
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73:. The term
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55:clock signal
51:computer bus
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478:GDDR6 SDRAM
474:GDDR5 SDRAM
470:GDDR4 SDRAM
466:GDDR3 SDRAM
409:CAS latency
184:PCI Express
144:), and the
130:main memory
75:toggle mode
67:dual-pumped
637:Categories
586:2024-04-07
499:References
462:GDDR SDRAM
457:DDR5 SDRAM
453:DDR4 SDRAM
449:DDR3 SDRAM
445:DDR2 SDRAM
429:registered
397:51.2 GB/s
394:6400 MT/s
380:38.4 GB/s
377:4800 MT/s
363:25.6 GB/s
360:3200 MT/s
346:19.2 GB/s
343:2400 MT/s
329:12.8 GB/s
326:1600 MT/s
180:InfiniBand
441:DDR SDRAM
312:6.4 GB/s
309:800 MT/s
295:3.2 GB/s
292:400 MT/s
278:1.6 GB/s
275:200 MT/s
228:DDR SDRAM
218:transfers
154:Athlon 64
103:frequency
39:computing
435:See also
421:XDR DRAM
206:downbeat
204:and one
160:(ADCs).
140:through
85:Overview
148:bus on
555:
522:
413:LPDDR2
214:cycles
202:upbeat
132:(both
69:, and
623:(PDF)
581:Intel
417:GDDR5
405:cycle
247:Names
210:hertz
134:RDRAM
122:PCI-X
553:ISBN
520:ISBN
476:and
455:and
425:DDR5
419:and
236:DIMM
222:MT/s
197:beat
182:and
142:DDR5
138:DDR1
136:and
126:GDDR
545:doi
152:'s
150:AMD
128:),
118:AGP
47:DDR
37:In
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45:(
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
