387:. In contrast, a CPU is capable of initiating transactions to multiple peripherals and address spaces at a time, and will support more than one thread ID on its AXI initiator ports and AXI target ports. This is why a CPU will typically support a full spec AXI bus. A typical example of a front side AXI switch would include a full specification AXI initiator connected to a CPU initiator, and several AXI-Lite targets connected to the AXI switch from different peripheral devices.
563:
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399:
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66:
168:
25:
1037:
1884:
1605:
1051:, meaning that there may be multiple data transfers (or beats) for a single request. This makes it useful in the cases where it is necessary to transfer large amount of data from or to a specific pattern of addresses. In AXI, bursts can be of three types, selected by the signals ARBURST (for reads) or AWBURST (for writes):
378:
Thread IDs on an initiator port are not globally defined, thus an AXI switch with multiple initiator ports will internally prefix the initiator port index to the thread ID, and provide this concatenated thread ID to the target device, then on return of the transaction to its initiator port of origin,
374:
may be assigned a thread ID for a particular initiator port memory access such as read addr1, write addr1, read addr1, and this sequence will complete in order because each transaction has the same initiator port thread ID. Another thread running on the CPU may have another initiator port thread ID
2401:
The protocol used by many SoC designers today is AXI, or
Advanced eXtensible Interface, and is part of the Arm Advanced Microcontroller Bus Architecture (AMBA) specification. It is especially prevalent in Xilinx's Zynq devices, providing the interface between the processing system and programmable
369:
Thread IDs allow a single initiator port to support multiple threads, where each thread has in-order access to the AXI address space, however each thread ID initiated from a single initiator port may complete out of order with respect to each other. For instance in the case where one thread ID is
1902:
Example of an AXI read transaction. The initiator requests 4 beats (ARLEN + 1) of 4 Bytes each starting from address 0x0 with INCR type. The target returns 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc, all with the OKAY status. Only the most relevant
2125:
AXI4-Stream is a simplified, lightweight bus protocol designed specifically for high-speed streaming data applications. It supports only unidirectional data flow, without the need for addressing or complex handshaking. An AXI Stream is similar to an AXI write data channel, with some important
1948:
Example of an AXI write transaction. The initiator drives 4 beats (AWLEN + 1) of 4 Bytes each starting from address 0x0 with INCR type, writing 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc. The target returns 'OKAY' as write response for the whole
1614:
1313:
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WRAP bursts are similar to the INCR ones, as each transfer has an address equal to the previous one plus the transfer size. However, with WRAP bursts, if the address of the current beat reaches the "Higher
Address boundary", it is reset to the "Wrap boundary":
1303:
382:
AXI-Lite bus is an AXI bus that only supports a single ID thread per initiator. This bus is typically used for an end point that only needs to communicate with a single initiator device at a time, for example, a simple peripheral such as a
1935:
plus any other optional signals. Each beat of the target's response is done with a RVALID/RREADY handshake and, on the last transfer, the target has to assert RLAST to inform that no more beats will follow without a new read request.
1879:{\displaystyle {\mathit {WrapBoundary}}=\left\lfloor {\frac {\mathit {StartAddress}}{{\mathit {NumberBytes}}\cdot {\mathit {BurstLength}}}}\right\rfloor \cdot ({\mathit {NumberBytes}}\cdot {\mathit {BurstLength}})}
1600:{\displaystyle {\mathit {Address}}_{i}={\mathit {WrapBoundary}}+({\mathit {StartAddress}}+{\mathit {i}}\cdot {\mathit {TransferSize}})\ \mathrm {mod} \ ({\mathit {BurstLength}}\cdot {\mathit {TransferSize}})}
2228:
TDATA is the primary payload used to provide the data that is passing across the interface. TDATA_WIDTH must be an integer number of bytes and is recommended to be 8, 16, 32, 64, 128, 256, 512 or 1024-bits.
1154:
1987:
After the completion of both the transactions, the target has to send back to the initiator the status of the write over the Write response channel, by returning the result over the BRESP signal.
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this thread ID prefix will be used to locate the initiator port and the prefix will be truncated. This is why the target port thread ID is wider in bits than the initiator port thread ID.
1158:
In INCR bursts, on the other hand, each beat has an address equal to the previous one plus the transfer size. This burst type is commonly used to read or write sequential memory areas.
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specification (AMBA). AXI had been introduced in 2003 with the AMBA3 specification. In 2010, a new revision of AMBA, AMBA4, defined the AXI4, AXI4-Lite and AXI4-Stream
1065:
In FIXED bursts, each beat within the transfer has the same address. This is useful for repeated access at the same memory location, such as when reading or writing a
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TUSER is a user-defined sideband information that can be transmitted along the data stream. TUSER_WIDTH is recommended to be an integer multiple of TDATA_WIDTH/8.
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blocked by a slow peripheral, another thread ID may continue independently of the order of the first thread ID. Another example, one thread on a
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TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
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TKEEP is the byte qualifier that indicates whether content of the associated byte of TDATA is processed as part of the data stream.
277:, which can be included depending on the specific requirements of the design, making AXI a versatile bus for numerous applications.
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signal is driven by the source to inform the destination entity that the payload on the channel is valid and can be read from that
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TVALID indicates the
Transmitter is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.
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assigned to it, and its memory access will be in order as well but may be intermixed with the first thread IDs transactions.
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390:(Additionally, the AXI-Lite bus is restricted to only support transaction lengths of a single data word per transaction.)
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A single AXI Stream transmitter can drive multiple streams which may be interleaved but reordering is not permitted.
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the "strobe" bits on WSTRB (if present), which conditionally mark the individual WDATA bytes as "valid" or "invalid"
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2014:
AXI4-Lite removes part of the AXI4 signals but follows the AXI4 specification for the remaining ones. Being a
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The address information are provided over the Write address channel, in a similar manner as a read operation:
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mechanism, both the source and the destination can control the flow of data, throttling the speed if needed.
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1298:{\displaystyle {\mathit {Address}}_{i}={\mathit {StartAddress}}+{\mathit {i}}\cdot {\mathit {TransferSize}}}
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An initiator has also to provide the data related to the specified address(es) on the Write data channel:
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TDEST provides routing information for the data stream. TDEST_WIDTH is recommended to be no more than 8.
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To start a write operation, the initiator has to provide both the address information and the data ones.
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to include N:M interconnects, able to extend the bus to topologies with multiple initiators and targets.
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is between a single initiator and a single target, the specification includes detailed descriptions and
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Additionally, the other auxiliary signals, if present, are used to define more specific transfers.
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After the usual ARVALID/ARREADY handshake, the target has to provide on the Read data channel:
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Like in the read path, on the last data word, WLAST has to be asserted by the initiator.
410:. In this example, the destination entity waits for a high VALID to assert its own READY.
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signal is driven by the receiving entity to notify that it is prepared to receive data.
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2018:
of AXI4, AXI4-Lite transactions are fully compatible with AXI4 devices, permitting the
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1907:
To start a read transaction, the initiator has to provide on the Read address channel:
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603:
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AXI5 Stream protocol introduces wake-up signaling and signal protection using parity.
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ACLK is a global clock signal. All signals are sampled on the rising edge of ACLK.
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between AXI4-Lite initiators and AXI4 targets without additional conversion logic.
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Region identifier, to access multiple logical interfaces from a single physical one
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TID is a data stream identifier. TID_WIDTH is recommended to be no more than 8.
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all data accesses use the full data bus width, which can be either 32 or 64 bits
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is asserted, a source must maintain the assertion until a handshake occurs.
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structure with reduced features and complexity. Notable differences are:
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and many of its partners as a main communication bus in their products.
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no bursts, instead data is packed into packets, frames and data streams
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TWAKEUP identifies any activity associated with AXI-Stream interface.
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the burst type, either FIXED, INCR or WRAP, on AWBURST (if present)
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the burst type, either FIXED, INCR or WRAP, on ARBURST (if present)
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Memory type, how the transaction has to progress through the system
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Byte strobe, to indicate which bytes of the WDATA signal are valid
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Read response, to specify the status of the current RDATA signal
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2385:"Introduction to AXI Protocol: Understanding the AXI interface"
2015:
1996:
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254:) is an on-chip communication bus protocol and is part of the
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Two main rules are defined for the control of these signals:
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the data corresponding to the specified address(es) on RDATA
1149:{\displaystyle {\mathit {Address}}={\mathit {StartAddress}}}
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transaction. Only the most relevant signals are shown here.
384:
568:
AXI Write
Address, Write Data and Write Response channels.
461:. An individual data transfer, so a clock cycle when both
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AMBA AXI4, AXI4-Lite and AXI4-Stream have been adopted by
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is independent from each other and has its own couple of
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2214:
TREADY indicates that a
Receiver can accept a transfer.
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1316:
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2133:
no limit on the data length which may be continuous
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927:Write response, to specify the status of the burst
457:, or terminate the transmission, by de-asserting
196:, and by adding encyclopedic text written from a
3726:
3310:Coherent Accelerator Processor Interface (CAPI)
976:
586:Signals of the Read and Write Address channels
266:and its specification is freely available from
1960:the start address has to be provided on AWADDR
2973:
2136:data width can be any integer number of bytes
776:Signals of the Read and Write Data channels
693:, security level and data/instruction access
1970:and, if present, all the optional signals.
1011:
1009:
1007:
1005:
1003:
1001:
999:
997:
995:
531:Other than some basic ordering rules, each
337:. Unsourced material may be challenged and
53:Learn how and when to remove these messages
2980:
2966:
2271:TLAST indicates the boundary of a packet.
2892:"AMBA AXI and ACE Protocol Specification"
2855:"AMBA AXI and ACE Protocol Specification"
2818:"AMBA AXI and ACE Protocol Specification"
2788:"AMBA AXI and ACE Protocol Specification"
2748:"AMBA AXI and ACE Protocol Specification"
2711:"AMBA AXI and ACE Protocol Specification"
2674:"AMBA AXI and ACE Protocol Specification"
2637:"AMBA AXI and ACE Protocol Specification"
2600:"AMBA AXI and ACE Protocol Specification"
2563:"AMBA AXI and ACE Protocol Specification"
2526:"AMBA AXI and ACE Protocol Specification"
2453:"AMBA AXI and ACE Protocol Specification"
2416:"AMBA AXI and ACE Protocol Specification"
2340:Advanced Microcontroller Bus Architecture
2126:differences on how the data is arranged:
357:Learn how and when to remove this message
256:Advanced Microcontroller Bus Architecture
234:Learn how and when to remove this message
216:Learn how and when to remove this message
150:Learn how and when to remove this message
2889:
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1943:
1897:
1035:
1018:
992:
989:Different behavior between AXI3 and AXI4
912:Write response ID, to identify multiple
556:AXI Read Address and Read Data channels.
397:
1917:the burst length on ARLEN (if present).
3727:
2007:all bursts are composed by 1 beat only
1966:the burst length on AWLEN (if present)
1040:Example of FIXED, INCR and WRAP bursts
899:Signals of the Write Response channel
86:Please improve this article by adding
2961:
2776:
2382:
620:Address of the first bit of the burst
2383:Toole, Christina (24 October 2016).
335:adding citations to reliable sources
302:
280:While the communication over an AXI
161:
59:
18:
177:contains text that is written in a
13:
2827:. pp. 121–128. Archived from
2425:. pp. 109–118. Archived from
2186:ARESETn is a global reset signal.
1999:of the AXI4 protocol, providing a
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1354:
1320:
1257:
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1204:
1170:
1108:
1080:
476:A source must not wait for a high
14:
3751:
2924:
602:Address ID, to identify multiple
273:AMBA AXI specifies many optional
34:This article has multiple issues.
3711:
3710:
2757:. pp. 45–47. Archived from
2683:. pp. 28–34. Archived from
2572:. pp. 22–23. Archived from
2535:. pp. 37–38. Archived from
2462:. pp. 23–24. Archived from
1931:the status of each beat on RRESP
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166:
64:
23:
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2846:
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2739:
2702:
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631:Number of bits inside the burst
507:In the AXI specification, five
99:"Advanced eXtensible Interface"
42:or discuss these issues on the
2591:
2554:
2517:
2499:
2489:"AMBA AXI4 Interface Protocol"
2481:
2444:
2407:
2362:
1873:
1793:
1594:
1511:
1491:
1395:
792:Data ID, to identify multiple
1:
3305:Intel Ultra Path Interconnect
2901:. p. 122. Archived from
2864:. p. 124. Archived from
2355:
2120:
449:signals are high in the same
298:
248:Advanced eXtensible Interface
88:secondary or tertiary sources
3283:Intel QuickPath Interconnect
3273:Direct Media Interface (DMI)
2720:. p. 22. Archived from
2646:. p. 38. Archived from
2609:. p. 40. Archived from
2025:
1990:
469:are high, is called "beat".
393:
7:
2402:logic sections of the chip.
2333:
1911:the start address on ARADDR
502:
10:
3756:
3268:Compute Express Link (CXL)
580:
527:Write Response channel (B)
521:Write Address channel (AW)
3704:
3663:
3642:
3591:
3505:IEEE-1284 (parallel port)
3427:
3420:logical device interface)
3323:
3075:
3009:
2350:Master/slave (technology)
1939:
1031:
515:Read Address channel (AR)
1893:
1024:Available only with AXI3
1015:Available only with AXI4
434:onwards. Similarly, the
2953:Xilinx AXI introduction
2345:Wishbone (computer bus)
1903:signals are shown here.
907:Write Response channel
3067:List of bus bandwidths
2370:"AMBA | Documentation"
2039:Write response channel
1950:
1904:
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1601:
1299:
1150:
1041:
664:Lock type, to provide
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524:Write Data channel (W)
411:
75:relies excessively on
2033:Write address channel
1947:
1901:
1881:
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1300:
1151:
1039:
597:Read Address channel
594:Write Address channel
518:Read Data channel (R)
401:
198:neutral point of view
16:Computer bus protocol
3510:IEEE-1394 (FireWire)
3248:PCI Extended (PCI-X)
2948:ARM AXI introduction
2042:Read address channel
1615:
1314:
1164:
1075:
414:AXI defines a basic
331:improve this section
190:promotional language
3351:Parallel ATA (PATA)
900:
841:Last bit identifier
777:
587:
416:handshake mechanism
404:handshake mechanism
3258:PCI Express (PCIe)
2941:2019-07-05 at the
2936:AXI4 specification
2045:Read data channel
2036:Write data channel
1951:
1905:
1876:
1597:
1295:
1146:
1042:
904:Signal description
898:
787:Read Data channel
784:Write Data channel
781:Signal description
775:
707:of the transaction
705:Quality of service
591:Signal description
585:
412:
192:and inappropriate
3722:
3721:
3708:
3435:Apple Desktop Bus
3412:PCI Express (via
3371:Serial ATA (SATA)
3057:Network on a chip
2899:developer.arm.com
2862:developer.arm.com
2825:developer.arm.com
2795:developer.arm.com
2755:developer.arm.com
2718:developer.arm.com
2681:developer.arm.com
2644:developer.arm.com
2607:developer.arm.com
2570:developer.arm.com
2533:developer.arm.com
2460:developer.arm.com
2423:developer.arm.com
2331:
2330:
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2115:
1977:the data on WDATA
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935:User-defined data
896:
895:
852:User-defined data
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729:User-defined data
689:Protection type:
666:atomic operations
653:Type of the burst
418:, composed by an
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3740:System on a chip
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3168:HP Precision Bus
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2020:interoperability
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1882:
1877:
1872:
1871:
1832:
1831:
1789:
1785:
1783:
1782:
1781:
1742:
1741:
1704:
1666:
1657:
1656:
1606:
1604:
1603:
1598:
1593:
1592:
1550:
1549:
1508:
1507:
1494:
1490:
1489:
1447:
1446:
1437:
1436:
1391:
1390:
1348:
1347:
1342:
1341:
1304:
1302:
1301:
1296:
1294:
1293:
1251:
1250:
1241:
1240:
1198:
1197:
1192:
1191:
1155:
1153:
1152:
1147:
1145:
1144:
1102:
1101:
1025:
1022:
1016:
1013:
990:
987:
959:
945:
901:
897:
882:
865:
778:
774:
759:
742:
642:Size of each bit
588:
584:
565:
553:
538:
490:
483:
479:
468:
464:
460:
456:
448:
444:
437:
429:
425:
421:
406:of the AMBA AXI
362:
355:
351:
348:
342:
311:
303:
239:
232:
221:
214:
210:
207:
201:
179:promotional tone
170:
169:
162:
155:
148:
144:
141:
135:
133:
92:
68:
60:
49:
27:
26:
19:
3755:
3754:
3750:
3749:
3748:
3746:
3745:
3744:
3725:
3724:
3723:
3718:
3709:
3700:
3659:
3638:
3587:
3500:IEEE-488 (GPIB)
3423:
3319:
3298:Infinity Fabric
3128:Europe Card Bus
3071:
3005:
2986:
2943:Wayback Machine
2927:
2922:
2921:
2911:
2909:
2905:
2894:
2888:
2884:
2874:
2872:
2868:
2857:
2851:
2847:
2837:
2835:
2831:
2820:
2814:
2810:
2800:
2798:
2790:
2784:
2777:
2767:
2765:
2761:
2750:
2744:
2740:
2730:
2728:
2724:
2713:
2707:
2703:
2693:
2691:
2687:
2676:
2670:
2666:
2656:
2654:
2650:
2639:
2633:
2629:
2619:
2617:
2613:
2602:
2596:
2592:
2582:
2580:
2576:
2565:
2559:
2555:
2545:
2543:
2539:
2528:
2522:
2518:
2505:
2504:
2500:
2487:
2486:
2482:
2472:
2470:
2466:
2455:
2449:
2445:
2435:
2433:
2429:
2418:
2412:
2408:
2394:
2392:
2381:
2377:
2372:. Arm Holdings.
2368:
2367:
2363:
2358:
2336:
2123:
2028:
1995:AXI4-Lite is a
1993:
1942:
1896:
1891:
1837:
1836:
1797:
1796:
1747:
1746:
1707:
1706:
1705:
1667:
1665:
1661:
1619:
1618:
1616:
1613:
1612:
1555:
1554:
1515:
1514:
1497:
1452:
1451:
1442:
1441:
1399:
1398:
1353:
1352:
1343:
1319:
1318:
1317:
1315:
1312:
1311:
1256:
1255:
1246:
1245:
1203:
1202:
1193:
1169:
1168:
1167:
1165:
1162:
1161:
1107:
1106:
1079:
1078:
1076:
1073:
1072:
1034:
1029:
1028:
1023:
1019:
1014:
993:
988:
977:
957:
943:
880:
863:
810:Read/Write data
757:
740:
583:
578:
573:
572:
571:
570:
569:
566:
558:
557:
554:
536:
511:are described:
505:
495:Thanks to this
488:
481:
477:
466:
462:
458:
454:
446:
442:
435:
427:
423:
419:
396:
363:
352:
346:
343:
328:
312:
301:
240:
229:
228:
227:
222:
211:
205:
202:
183:
171:
167:
156:
145:
139:
136:
93:
91:
85:
81:primary sources
69:
28:
24:
17:
12:
11:
5:
3753:
3743:
3742:
3737:
3735:Computer buses
3720:
3719:
3705:
3702:
3701:
3699:
3698:
3693:
3688:
3678:
3673:
3667:
3665:
3661:
3660:
3658:
3657:
3652:
3646:
3644:
3640:
3639:
3637:
3636:
3631:
3626:
3621:
3616:
3611:
3609:Intel HD Audio
3606:
3601:
3599:ADAT Lightpipe
3595:
3593:
3589:
3588:
3586:
3585:
3580:
3575:
3570:
3565:
3560:
3555:
3550:
3545:
3540:
3522:
3517:
3512:
3507:
3502:
3497:
3492:
3487:
3482:
3477:
3472:
3467:
3462:
3457:
3452:
3447:
3442:
3437:
3431:
3429:
3425:
3424:
3422:
3421:
3410:
3405:
3400:
3395:
3390:
3389:
3388:
3383:
3373:
3368:
3363:
3358:
3353:
3348:
3343:
3338:
3333:
3327:
3325:
3321:
3320:
3318:
3317:
3312:
3307:
3302:
3301:
3300:
3293:HyperTransport
3290:
3285:
3280:
3275:
3270:
3265:
3260:
3255:
3250:
3245:
3240:
3235:
3230:
3225:
3220:
3215:
3210:
3205:
3200:
3195:
3190:
3185:
3180:
3175:
3170:
3165:
3160:
3155:
3150:
3145:
3140:
3135:
3130:
3125:
3120:
3115:
3110:
3105:
3100:
3095:
3090:
3085:
3079:
3077:
3073:
3072:
3070:
3069:
3064:
3059:
3054:
3049:
3047:Bus contention
3044:
3039:
3034:
3029:
3024:
3022:Front-side bus
3019:
3013:
3011:
3007:
3006:
3003:computer buses
2985:
2984:
2977:
2970:
2962:
2956:
2955:
2950:
2945:
2933:
2926:
2925:External links
2923:
2920:
2919:
2908:on 5 July 2019
2890:Arm Holdings.
2882:
2871:on 5 July 2019
2853:Arm Holdings.
2845:
2834:on 5 July 2019
2816:Arm Holdings.
2808:
2786:Arm Holdings.
2775:
2764:on 5 July 2019
2746:Arm Holdings.
2738:
2727:on 5 July 2019
2709:Arm Holdings.
2701:
2690:on 5 July 2019
2672:Arm Holdings.
2664:
2653:on 5 July 2019
2635:Arm Holdings.
2627:
2616:on 5 July 2019
2598:Arm Holdings.
2590:
2579:on 5 July 2019
2561:Arm Holdings.
2553:
2542:on 5 July 2019
2524:Arm Holdings.
2516:
2511:www.xilinx.com
2498:
2493:www.xilinx.com
2480:
2469:on 5 July 2019
2451:Arm Holdings.
2443:
2432:on 5 July 2019
2414:Arm Holdings.
2406:
2375:
2360:
2359:
2357:
2354:
2353:
2352:
2347:
2342:
2335:
2332:
2329:
2328:
2325:
2322:
2319:
2315:
2314:
2311:
2308:
2305:
2301:
2300:
2297:
2294:
2291:
2287:
2286:
2283:
2280:
2277:
2273:
2272:
2269:
2266:
2263:
2259:
2258:
2255:
2252:
2249:
2245:
2244:
2241:
2238:
2235:
2231:
2230:
2226:
2223:
2220:
2216:
2215:
2212:
2209:
2206:
2202:
2201:
2198:
2195:
2192:
2188:
2187:
2184:
2181:
2178:
2174:
2173:
2170:
2167:
2164:
2160:
2159:
2156:
2153:
2150:
2138:
2137:
2134:
2131:
2122:
2119:
2114:
2113:
2110:
2107:
2105:
2102:
2098:
2097:
2094:
2091:
2088:
2085:
2081:
2080:
2077:
2074:
2071:
2068:
2064:
2063:
2060:
2057:
2054:
2051:
2047:
2046:
2043:
2040:
2037:
2034:
2027:
2024:
2012:
2011:
2008:
1992:
1989:
1982:
1981:
1978:
1968:
1967:
1964:
1961:
1941:
1938:
1933:
1932:
1929:
1919:
1918:
1915:
1912:
1895:
1892:
1890:
1887:
1875:
1870:
1867:
1864:
1861:
1858:
1855:
1852:
1849:
1846:
1843:
1840:
1835:
1830:
1827:
1824:
1821:
1818:
1815:
1812:
1809:
1806:
1803:
1800:
1795:
1792:
1788:
1780:
1777:
1774:
1771:
1768:
1765:
1762:
1759:
1756:
1753:
1750:
1745:
1740:
1737:
1734:
1731:
1728:
1725:
1722:
1719:
1716:
1713:
1710:
1703:
1700:
1697:
1694:
1691:
1688:
1685:
1682:
1679:
1676:
1673:
1670:
1664:
1660:
1655:
1652:
1649:
1646:
1643:
1640:
1637:
1634:
1631:
1628:
1625:
1622:
1596:
1591:
1588:
1585:
1582:
1579:
1576:
1573:
1570:
1567:
1564:
1561:
1558:
1553:
1548:
1545:
1542:
1539:
1536:
1533:
1530:
1527:
1524:
1521:
1518:
1513:
1506:
1503:
1500:
1493:
1488:
1485:
1482:
1479:
1476:
1473:
1470:
1467:
1464:
1461:
1458:
1455:
1450:
1445:
1440:
1435:
1432:
1429:
1426:
1423:
1420:
1417:
1414:
1411:
1408:
1405:
1402:
1397:
1394:
1389:
1386:
1383:
1380:
1377:
1374:
1371:
1368:
1365:
1362:
1359:
1356:
1351:
1346:
1340:
1337:
1334:
1331:
1328:
1325:
1322:
1292:
1289:
1286:
1283:
1280:
1277:
1274:
1271:
1268:
1265:
1262:
1259:
1254:
1249:
1244:
1239:
1236:
1233:
1230:
1227:
1224:
1221:
1218:
1215:
1212:
1209:
1206:
1201:
1196:
1190:
1187:
1184:
1181:
1178:
1175:
1172:
1143:
1140:
1137:
1134:
1131:
1128:
1125:
1122:
1119:
1116:
1113:
1110:
1105:
1100:
1097:
1094:
1091:
1088:
1085:
1082:
1063:
1062:
1059:
1056:
1033:
1030:
1027:
1026:
1017:
991:
974:
973:
968:
967:
964:
954:
953:
950:
940:
939:
936:
932:
931:
928:
924:
923:
920:
916:over a single
909:
908:
905:
894:
893:
890:
887:
877:
876:
873:
870:
860:
859:
856:
853:
849:
848:
845:
842:
838:
837:
835:
832:
828:
827:
824:
822:
818:
817:
814:
811:
807:
806:
803:
800:
796:over a single
789:
788:
785:
782:
771:
770:
767:
764:
754:
753:
750:
747:
737:
736:
733:
730:
726:
725:
722:
719:
715:
714:
711:
708:
701:
700:
697:
694:
686:
685:
682:
679:
675:
674:
671:
668:
661:
660:
657:
654:
650:
649:
646:
643:
639:
638:
635:
632:
628:
627:
624:
621:
617:
616:
613:
610:
606:over a single
599:
598:
595:
592:
582:
579:
577:
574:
567:
560:
559:
555:
548:
547:
546:
545:
544:
529:
528:
525:
522:
519:
516:
504:
501:
493:
492:
485:
441:When both the
395:
392:
365:
364:
315:
313:
306:
300:
297:
242:
241:
224:
223:
194:external links
174:
172:
165:
158:
157:
72:
70:
63:
58:
32:
31:
29:
22:
15:
9:
6:
4:
3:
2:
3752:
3741:
3738:
3736:
3733:
3732:
3730:
3717:
3703:
3697:
3694:
3692:
3689:
3686:
3682:
3679:
3677:
3674:
3672:
3671:Multidrop bus
3669:
3668:
3666:
3662:
3656:
3653:
3651:
3648:
3647:
3645:
3641:
3635:
3632:
3630:
3627:
3625:
3622:
3620:
3617:
3615:
3612:
3610:
3607:
3605:
3602:
3600:
3597:
3596:
3594:
3590:
3584:
3581:
3579:
3578:External PCIe
3576:
3574:
3571:
3569:
3566:
3564:
3561:
3559:
3558:Parallel SCSI
3556:
3554:
3551:
3549:
3546:
3544:
3541:
3538:
3534:
3530:
3526:
3523:
3521:
3518:
3516:
3513:
3511:
3508:
3506:
3503:
3501:
3498:
3496:
3493:
3491:
3488:
3486:
3483:
3481:
3478:
3476:
3473:
3471:
3468:
3466:
3463:
3461:
3458:
3456:
3453:
3451:
3450:Commodore bus
3448:
3446:
3443:
3441:
3438:
3436:
3433:
3432:
3430:
3426:
3419:
3415:
3411:
3409:
3406:
3404:
3401:
3399:
3398:Fibre Channel
3396:
3394:
3391:
3387:
3384:
3382:
3379:
3378:
3377:
3374:
3372:
3369:
3367:
3364:
3362:
3359:
3357:
3354:
3352:
3349:
3347:
3344:
3342:
3339:
3337:
3334:
3332:
3329:
3328:
3326:
3322:
3316:
3313:
3311:
3308:
3306:
3303:
3299:
3296:
3295:
3294:
3291:
3289:
3286:
3284:
3281:
3279:
3276:
3274:
3271:
3269:
3266:
3264:
3261:
3259:
3256:
3254:
3251:
3249:
3246:
3244:
3241:
3239:
3236:
3234:
3231:
3229:
3226:
3224:
3221:
3219:
3216:
3214:
3211:
3209:
3206:
3204:
3201:
3199:
3196:
3194:
3191:
3189:
3186:
3184:
3181:
3179:
3176:
3174:
3171:
3169:
3166:
3164:
3161:
3159:
3156:
3154:
3151:
3149:
3146:
3144:
3141:
3139:
3136:
3134:
3131:
3129:
3126:
3124:
3121:
3119:
3116:
3114:
3111:
3109:
3106:
3104:
3101:
3099:
3096:
3094:
3091:
3089:
3086:
3084:
3081:
3080:
3078:
3074:
3068:
3065:
3063:
3062:Plug and play
3060:
3058:
3055:
3053:
3052:Bus mastering
3050:
3048:
3045:
3043:
3040:
3038:
3035:
3033:
3030:
3028:
3027:Back-side bus
3025:
3023:
3020:
3018:
3015:
3014:
3012:
3008:
3004:
3001:
2997:
2995:
2990:
2983:
2978:
2976:
2971:
2969:
2964:
2963:
2960:
2954:
2951:
2949:
2946:
2944:
2940:
2937:
2934:
2932:
2929:
2928:
2904:
2900:
2893:
2886:
2867:
2863:
2856:
2849:
2830:
2826:
2819:
2812:
2796:
2789:
2782:
2780:
2760:
2756:
2749:
2742:
2723:
2719:
2712:
2705:
2686:
2682:
2675:
2668:
2649:
2645:
2638:
2631:
2612:
2608:
2601:
2594:
2575:
2571:
2564:
2557:
2538:
2534:
2527:
2520:
2513:. Xilinx Inc.
2512:
2508:
2502:
2495:. Xilinx Inc.
2494:
2490:
2484:
2465:
2461:
2454:
2447:
2428:
2424:
2417:
2410:
2403:
2391:. Arm Limited
2390:
2386:
2379:
2371:
2365:
2361:
2351:
2348:
2346:
2343:
2341:
2338:
2337:
2326:
2323:
2320:
2317:
2316:
2312:
2309:
2306:
2303:
2302:
2298:
2295:
2292:
2289:
2288:
2284:
2281:
2278:
2275:
2274:
2270:
2267:
2264:
2261:
2260:
2256:
2254:TDATA_WIDTH/8
2253:
2250:
2247:
2246:
2242:
2240:TDATA_WIDTH/8
2239:
2236:
2233:
2232:
2227:
2224:
2221:
2218:
2217:
2213:
2210:
2207:
2204:
2203:
2199:
2196:
2193:
2190:
2189:
2185:
2182:
2179:
2176:
2175:
2171:
2168:
2165:
2162:
2161:
2157:
2154:
2151:
2148:
2147:
2144:
2141:
2135:
2132:
2129:
2128:
2127:
2118:
2111:
2108:
2106:
2103:
2100:
2099:
2095:
2092:
2089:
2086:
2083:
2082:
2078:
2075:
2072:
2069:
2066:
2065:
2061:
2058:
2055:
2052:
2049:
2048:
2044:
2041:
2038:
2035:
2032:
2031:
2023:
2021:
2017:
2009:
2006:
2005:
2004:
2002:
2001:register-like
1998:
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537:xVALID/xREADY
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316:This section
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175:This article
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101: –
100:
96:
95:Find sources:
89:
83:
82:
78:
73:This article
71:
67:
62:
61:
56:
54:
47:
46:
41:
40:
35:
30:
21:
20:
3684:
3203:TURBOchannel
2993:
2931:AMBA webpage
2910:. Retrieved
2903:the original
2898:
2885:
2873:. Retrieved
2866:the original
2861:
2848:
2836:. Retrieved
2829:the original
2824:
2811:
2799:. Retrieved
2797:. p. 44
2794:
2766:. Retrieved
2759:the original
2754:
2741:
2729:. Retrieved
2722:the original
2717:
2704:
2692:. Retrieved
2685:the original
2680:
2667:
2655:. Retrieved
2648:the original
2643:
2630:
2618:. Retrieved
2611:the original
2606:
2593:
2581:. Retrieved
2574:the original
2569:
2556:
2544:. Retrieved
2537:the original
2532:
2519:
2510:
2501:
2492:
2483:
2471:. Retrieved
2464:the original
2459:
2446:
2434:. Retrieved
2427:the original
2422:
2409:
2400:
2395:11 September
2393:. Retrieved
2388:
2378:
2364:
2158:Description
2142:
2139:
2124:
2117:
2013:
1994:
1986:
1983:
1972:
1969:
1955:
1952:
1934:
1923:
1920:
1906:
1889:Transactions
1611:
1608:
1310:
1306:
1160:
1157:
1071:
1064:
1043:
1020:
971:
530:
506:
494:
471:
440:
426:signal. The
413:
389:
381:
377:
368:
353:
344:
329:Please help
317:
290:
279:
272:
264:royalty-free
251:
247:
245:
230:
212:
203:
188:by removing
184:Please help
176:
146:
137:
127:
120:
113:
106:
94:
74:
50:
43:
37:
36:Please help
33:
3676:CoreConnect
3655:ExpressCard
3583:Thunderbolt
3573:Camera Link
3356:Bus and Tag
3042:Address bus
3037:Control bus
3032:Daisy chain
2321:Transmitter
2310:TUSER_WIDTH
2307:Transmitter
2296:TDEST_WIDTH
2293:Transmitter
2279:Transmitter
2265:Transmitter
2251:Transmitter
2237:Transmitter
2225:TDATA_WIDTH
2222:Transmitter
2194:Transmitter
1046:burst-based
451:clock cycle
432:clock cycle
3729:Categories
3529:ACCESS.bus
3428:Peripheral
3228:InfiniBand
3223:HP GSC bus
3017:System bus
2356:References
2121:AXI-Stream
480:to assert
299:Thread IDs
206:April 2022
186:improve it
140:April 2022
110:newspapers
77:references
39:improve it
3490:Lightning
3440:Atari SIO
3315:SpaceWire
3148:Zorro III
3088:S-100 bus
3083:SS-50 bus
3076:Standards
2996:standards
2989:Technical
2507:"AXI4 IP"
2282:TID_WIDTH
1991:AXI4-Lite
1834:⋅
1791:⋅
1744:⋅
1552:⋅
1449:⋅
1253:⋅
1044:AXI is a
961:handshake
947:handshake
884:handshake
867:handshake
761:handshake
744:handshake
724:ARREGION
691:privilege
542:signals.
540:handshake
497:handshake
394:Handshake
318:does not
262:. AXI is
260:protocols
45:talk page
3716:Category
3691:Wishbone
3664:Embedded
3643:Portable
3563:Profibus
3495:DMX512-A
3381:Parallel
3233:Ethernet
3143:Zorro II
3093:Multibus
2994:de facto
2939:Archived
2334:See also
2208:Receiver
1787:⌋
1663:⌊
1049:protocol
769:ARREADY
752:ARVALID
721:AWREGION
684:ARCACHE
659:ARBURST
509:channels
503:Channels
408:protocol
347:May 2020
3696:SLIMbus
3650:PC Card
3634:TOSLINK
3324:Storage
3278:RapidIO
3158:FASTBUS
3113:STD Bus
3010:General
2389:arm.com
2318:TWAKEUP
2177:ARESETn
2079:RREADY
2076:ARREADY
2067:AWREADY
2062:RVALID
2059:ARVALID
2050:AWVALID
2026:Signals
966:BREADY
952:BVALID
918:channel
914:streams
892:RREADY
875:RVALID
798:channel
794:streams
766:AWREADY
749:AWVALID
735:ARUSER
699:ARPROT
681:AWCACHE
673:ARLOCK
656:AWBURST
648:ARSIZE
626:ARADDR
608:channel
604:streams
581:Signals
533:channel
339:removed
324:sources
286:signals
275:signals
124:scholar
3629:S/PDIF
3520:1-Wire
3485:RS-485
3480:RS-423
3475:RS-422
3470:RS-232
3331:ST-506
3288:NVLink
3138:STEbus
3098:Unibus
2912:5 July
2875:5 July
2838:5 July
2801:5 July
2768:5 July
2731:5 July
2694:5 July
2657:5 July
2620:5 July
2583:5 July
2546:5 July
2473:5 July
2436:5 July
2205:TREADY
2191:TVALID
2152:Source
2149:Signal
2112:RRESP
2109:ARPROT
2101:AWPROT
2096:RDATA
2093:ARADDR
2084:AWADDR
2073:BREADY
2070:WREADY
2056:BVALID
2053:WVALID
2016:subset
1997:subset
1940:Writes
1509:
1495:
1032:Bursts
963:signal
958:xREADY
949:signal
944:xVALID
938:BUSER
930:BRESP
889:WREADY
886:signal
881:xREADY
872:WVALID
869:signal
864:xVALID
858:RUSER
847:RLAST
826:RRESP
816:RDATA
763:signal
758:xREADY
746:signal
741:xVALID
732:AWUSER
713:ARQOS
696:AWPROT
670:AWLOCK
645:AWSIZE
637:ARLEN
623:AWADDR
489:xVALID
482:xVALID
478:xREADY
467:xREADY
463:xVALID
459:xVALID
455:xVALID
447:xREADY
443:xVALID
436:xREADY
428:xVALID
424:xREADY
420:xVALID
402:Basic
293:Xilinx
126:
119:
112:
105:
97:
3624:McASP
3592:Audio
3537:SMBus
3533:PMBus
3515:UNI/O
3455:HP-IL
3408:SATAe
3393:ESCON
3366:HIPPI
3198:NuBus
3153:CAMAC
3123:Q-Bus
3118:SMBus
3103:VAXBI
3000:wired
2906:(PDF)
2895:(PDF)
2869:(PDF)
2858:(PDF)
2832:(PDF)
2821:(PDF)
2791:(PDF)
2762:(PDF)
2751:(PDF)
2725:(PDF)
2714:(PDF)
2688:(PDF)
2677:(PDF)
2651:(PDF)
2640:(PDF)
2614:(PDF)
2603:(PDF)
2577:(PDF)
2566:(PDF)
2540:(PDF)
2529:(PDF)
2467:(PDF)
2456:(PDF)
2430:(PDF)
2419:(PDF)
2304:TUSER
2290:TDEST
2262:TLAST
2248:TKEEP
2234:TSTRB
2219:TDATA
2180:Reset
2166:Clock
2155:Width
2104:WSTRB
2090:BRESP
2087:WDATA
1894:Reads
1609:with
1055:FIXED
855:WUSER
844:WLAST
834:WSTRB
813:WDATA
710:AWQOS
634:AWLEN
615:ARID
487:Once
131:JSTOR
117:books
3681:AMBA
3619:MADI
3604:AES3
3465:MIDI
3418:NVMe
3414:AHCI
3376:SCSI
3361:DSSI
3336:ESDI
3213:SBus
3173:EISA
3108:MBus
2998:for
2991:and
2914:2019
2877:2019
2840:2019
2803:2019
2770:2019
2733:2019
2696:2019
2659:2019
2622:2019
2585:2019
2548:2019
2475:2019
2438:2019
2397:2023
2163:ACLK
1067:FIFO
1061:WRAP
1058:INCR
922:BID
805:RID
612:AWID
465:and
445:and
422:and
385:UART
322:any
320:cite
246:The
103:news
3685:AXI
3614:I²S
3568:USB
3553:D²B
3548:SPI
3543:I3C
3525:I²C
3460:HIL
3445:DCB
3416:or
3403:SSA
3386:SAS
3346:SMD
3341:IPI
3263:AGP
3253:PXI
3243:PCI
3238:UPA
3218:VLB
3208:MCA
3193:VPX
3188:VXS
3183:VXI
3178:VME
3163:LPC
3133:ISA
2276:TID
802:WID
576:AXI
372:CPU
333:by
282:bus
268:ARM
252:AXI
79:to
3731::
3535:,
3531:,
2897:.
2860:.
2823:.
2793:.
2778:^
2753:.
2716:.
2679:.
2642:.
2605:.
2568:.
2531:.
2509:.
2491:.
2458:.
2421:.
2399:.
2387:.
1069:.
994:^
978:^
270:.
90:.
48:.
3687:)
3683:(
3539:)
3527:(
2981:e
2974:t
2967:v
2916:.
2879:.
2842:.
2805:.
2772:.
2735:.
2698:.
2661:.
2624:.
2587:.
2550:.
2477:.
2440:.
2324:1
2268:1
2211:1
2197:1
2183:1
2169:1
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1869:h
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1633:B
1630:p
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1621:W
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1200:=
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1099:s
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345:(
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250:(
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231:(
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213:(
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204:(
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182:.
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138:(
128:·
121:·
114:·
107:·
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55:)
51:(
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