25:
1266:
are to be written. Because there are 256 possible patterns and only 32 bytes in the burst, it is straightforward to find one. Even when multiple devices are connected in parallel, a mask byte can always be found when the bus is at most 128 bits wide. (This would produce 256 bytes per burst, but a masked write command is only used if at least one of them is not to be written.)
122:
164:. It eliminates the unusually high latency problems that plagued early forms of RDRAM. Also, XDR DRAM has heavy emphasis on per-pin bandwidth, which can benefit further cost control on PCB production. This is because fewer lanes are needed for the same amount of bandwidth. Rambus owns the rights to the technology. XDR is used by
1265:
a bitmap indicating which bytes are to be written; it would not be large enough for the 32 bytes in a write burst. Rather, it is a bit pattern which the DRAM controller fills unwritten bytes with. The DRAM controller is responsible for finding a pattern which does not appear in the other bytes that
1236:
This operates equivalently to standard SDRAM's activate command, specifying a row address to be loaded into the bank's sense amplifier array. To save power, a chip may be configured to only activate a portion of the sense amplifier array. In this case, the SR1..0 bits specify the half or quarter of
343:
request/command bus (RQ11..0), and a bidirectional differential data bus up to 16 bits wide (DQ15..0/DQN15..0). The request bus may be connected to several memory chips in parallel, but the data bus is point to point; only one RAM chip may be connected to it. To support different amounts of memory
1387:
On reset, each chip drives its SDO pin low (1). When reset is released, a series of SCK pulses are sent to the chips. Each chip drives its SDO output high (0) one cycle after seeing its SDI input high (0). Further, it counts the number of cycles that elapse between releasing reset and seeing its
1383:
XDR DRAMs are probed and configured using a low-speed serial bus. The RST, SCK, and CMD signals are driven by the controller to every chip in parallel. The SDI and SDO lines are daisy-chained together, with the last SDO output connected to the controller, and the first SDI input tied high (logic
1249:
If the chip is using a data bus less than 16 bits wide, one or more of the sub-column address bits are used to select the portion of the column to be presented on the data bus. If the data bus is 8 bits wide, SC3 is used to identify which half of the read data to access; if the data bus is 4 bits
1245:
These operate analogously to a standard SDRAM's read or write commands, specifying a column address. Data is provided to the chip a few cycles after a write command (typically 3), and is output by the chip several cycles after a read command (typically 6). Just as with other forms of SDRAM, the
347:
In addition, each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained
1307:
Refresh commands are also different from a conventional SDRAM. There is no "refresh all banks" command, and the refresh operation is divided into separate activate and precharge operations so the timing is determined by the memory controller. The refresh counter is also programmable by the
1246:
DRAM controller is responsible for ensuring that the data bus is not scheduled for use in both directions at the same time. Data is always transferred in 16-transfer bursts, lasting 2 clock cycles. Thus, for a ×16 device, 256 bits (32 bytes) are transferred per burst.
344:
with a fixed-width memory controller, the chips have a programmable interface width. A 32-bit-wide DRAM controller may support 2 16-bit chips, or be connected to 4 memory chips each of which supplies 8 bits of data, or up to 16 chips configured with 2-bit interfaces.
1425:
8 bits of data. If this is a read command, the bits provided must be 0, and the register's value is produced on the SDO pin of the selected chip. All non-selected chips connect their SDI inputs to their SDO outputs, so the controller will see the
1269:
Each byte is the 8 consecutive bits transferred across one data line during a particular clock cycle. M0 is matched to the first data bit transferred during a clock cycle, and M7 is matched to the last bit.
1227:
Some commands contain delay fields; these delay the effect of that command by the given number of clock cycles. This permits multiple commands (to different banks) to take effect on the same clock cycle.
1375:
The fourth subcommand places the chip in power-down mode. In this mode, it performs internal refresh and ignores the high-speed data lines. It must be woken up using the low-speed serial bus.
1372:
field. Although there are 16 possibilities, only 4 are actually used. Three subcommands start and stop output driver calibration (which must be performed periodically, every 100 ms).
1261:
The masked write command is similar to a normal write, but no command delay is permitted and a mask byte is supplied. This permits controlling which 8-bit fields are written. This is
1253:
Unlike conventional SDRAM, there is no provision for choosing the order in which the data is supplied within a burst. Thus, it is not possible to perform critical-word-first reads.
1388:
SDI input high, and copies that count to an internal chip ID register. Commands sent by the controller over the CMD line include an address which must match the chip ID field.
365:
The data bus operates at 8x the speed of the clock; a 400 MHz clock generates 3200 MT/s. All data reads and writes operate in 16-transfer bursts lasting 2 clock cycles.
1396:
Each command either reads or writes a single 8-bit register, using an 8-bit address. This allows up to 256 registers, but only the range 1–31 is currently assigned.
1237:
the row to activate, and following read/write commands' column addresses are required to be limited to that portion. (Refresh operations always use the full row.)
1301:
bits specify a refresh operation. Each may be separately enabled. If enabled, each may have a different command delay and must be addressed to a different bank.
1399:
Normally, the CMD line is left high (logic 0) and SCK pulses have no effect. To send a command, a sequence of 32 bits is clocked out over the CMD lines:
314:
1273:
This convention also interferes with performing critical-word-first reads; any word must include bits from at least the first 8 bits transferred.
1493:
1835:
1840:
362:
relative to the clock input. Two consecutive 12-bit transfers (beginning with the falling edge of CFM) make a 24-bit command packet.
231:
1599:
1591:
1304:
Precharge commands may only be sent to one bank at a time; unlike a conventional SDRAM, there is no "precharge all banks" command.
1519:
1479:
1513:
160:
XDR was designed to be effective in small, high-bandwidth consumer systems, high-performance memory applications, and high-end
1351:
Load refresh register high; copy RQ7–0 to the high 8 bits of the refresh counter REFH (if implemented). No command delay.
1221:
1413:
A single/broadcast bit. If 0, only the device with the matching ID is selected. If 1, all devices execute the command.
227:
89:
108:
61:
1220:
There are a large number of timing constraints giving minimum times that must elapse between various commands (see
68:
1552:
1422:
A single bit of "0". This provides time to process read requests, and enable the SDO output in case of a read,
46:
1345:
Load refresh register middle; copy RQ7–0 to the middle 8 bits of the refresh counter REFM. No command delay.
339:
An XDR RAM chip's high-speed signals are a differential clock input (clock from master, CFM/CFMN), a 12-bit
1701:
1561:
1281:
This command is similar to a combination of a conventional SDRAM's precharge and refresh commands. The POP
137:
75:
1339:
Load refresh register low; copy RQ7–0 to the low 8 bits of the refresh counter REFL. No command delay.
1449:
1416:
6 bits of serial device ID. Device IDs are automatically assigned, starting with 0, on device reset.
57:
42:
1490:
1327:
Refresh activate; activate the row selected by the REFH/M/L register and selected bank for refresh.
161:
340:
35:
1830:
216:
1653:
1814:
1468:
1845:
8:
275:
1429:
A single bit of "0". This ends the command and provides time to disable the SDO output.
1685:
1545:
252:
1530:
82:
1525:
288:
284:
1368:
This command performs a number of miscellaneous functions, as determined by the XOP
359:
1637:
1497:
1866:
1333:
Refresh & increment; as for REFA, but also increment the REFH/M/L register.
223:
197:
Each chip provides 8, 16, or 32 programmable lanes, providing up to 230.4
1860:
1791:
1706:
1538:
169:
348:
together and eventually connect to a single pin on the memory controller.
1751:
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1741:
1736:
1731:
1726:
149:
1469:
AnandTech: Rambus in Cell
Processors and Intel's Dual Core Announcements
1721:
1624:
1619:
1614:
1609:
352:
145:
1781:
1604:
1444:
24:
1581:
1576:
355:; an asserted signal or logical 1 is represented by a low voltage.
202:
1321:
Refresh precharge; end the refresh operation on the selected bank.
1224:); the DRAM controller sending them must ensure they are all met.
1809:
1673:
198:
1763:
1648:
1410:
A read/write bit. If 0, this is a read, if 1 this is a write.
1771:
1716:
1711:
1678:
1663:
1643:
1631:
1439:
141:
1804:
1799:
1668:
1658:
165:
246:
Up to four bank-interleaved transactions at full bandwidth
121:
1560:
261:
Early-read-after-write support for maximum efficiency
297:
Dynamic data width support with dynamic clock gating
49:. Unsourced material may be challenged and removed.
1520:Rambus FlexIO CPU Interface provides XDR Interface
226:driver, voltage swing 0.2V. It is not the same as
1289:bits specify a precharge operation, while the ROP
1222:Dynamic random-access memory § Memory timing
1858:
1391:
280:Programmable ultra-low-voltage DRSL 200 mV swing
1480:Elpida Produces World's Fastest 7.2GHz XDR DRAM
1363:
862:
134:extreme data rate dynamic random-access memory
1546:
1063:
901:
718:
701:
676:
643:
598:
205:/s) at 900 MHz (7.2 GHz effective).
1276:
194:(ODR): Eight bits per clock cycle per lane.
175:
1553:
1539:
317:circuits compensate to a 2.5 ps resolution
109:Learn how and when to remove this message
307:
120:
1378:
1256:
1231:
368:Request packet formats are as follows:
320:XDR Interconnect uses minimum pin count
140:interface. It is based on and succeeds
1859:
1240:
1534:
1516:archived December 2011 at archive.org
1207:
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833:
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330:1.25/2.0/2.5/3.33 ns request packets
47:adding citations to reliable sources
18:
186:Initial clock rate at 400 MHz.
13:
14:
1878:
1522:archived July 2006 at archive.org
1507:
1250:wide, SC3 and SC2 are used, etc.
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144:. Competing technologies include
372:XDR DRAM request packet formats
249:Point-to-point data interconnect
237:Programmable on-chip termination
219:Rambus Signalling Levels (DRSL)
23:
294:Power-down self-refresh support
34:needs additional citations for
1484:
1473:
1462:
243:Eight bank memory architecture
180:
1:
1455:
1392:General structure of commands
1308:controller. Operations are:
1562:Dynamic random-access memory
1526:Qimonda XDR(TM) DRAM product
1315:Perform no refresh operation
358:The request bus operates at
138:dynamic random-access memory
16:Type of random-access memory
7:
1433:
1364:Calibrate/powerdown command
351:All single-ended lines are
334:
303:Sub-page activation support
240:Adaptive impedance matching
209:
155:
10:
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1419:8 bits of register address
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324:
258:Dynamic request scheduling
1823:
1790:
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1694:
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1450:List of device bandwidths
1407:, a command start signal.
1277:Precharge/refresh command
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176:Technical specifications
136:) is a high-performance
1514:Rambus XDR Product Page
222:This uses differential
1496:July 24, 2011, at the
300:Per-pin I/O power-down
126:
607:Precharge delay (0–3)
397:Calibrate/power-down
308:Ease of system design
264:Zero overhead refresh
124:
1379:Low-speed serial bus
1257:Masked write command
1232:Row activate command
43:improve this article
1241:Read/write commands
1130:Sub-column address
1004:Refresh delay (0–3)
877:Command delay (0–1)
857:Command delay (0–1)
373:
1686:Hybrid Memory Cube
1115:Sub-column address
402:Precharge/refresh
392:Column read/write
371:
269:Power requirements
253:Chip scale package
127:
1854:
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1491:XDR™ Architecture
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1846:Transistor count
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871:Precharge enable
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360:double data rate
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1638:Fast Cycle DRAM
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1498:Wayback Machine
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1185:Sub-row address
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920:
913:Refresh command
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653:
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378:
337:
327:
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215:Bi-directional
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191:Octal data rate
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1836:SDRAM timeline
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1792:Memory modules
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1508:External links
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776:Precharge bank
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224:open-collector
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201:/s (28.8
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1831:DRAM timeline
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1158:
1155:
1143:
1137:
1134:
1133:
1126:
1123:
1111:
1105:
1102:
1101:
1097:
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1085:
1079:
1076:
1075:
1071:
1068:
1066:
1054:
1048:
1045:
1044:
1040:
1037:
1034:
1028:
1022:
1019:
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1009:
1006:
1000:
989:
983:
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979:
975:
972:
957:
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949:
946:
931:
928:
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904:
892:
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870:
867:
865:
856:
853:
847:
844:
843:
821:
818:
817:
795:
792:
791:
788:Bank address
757:
754:
753:
728:
725:
724:
721:
704:
692:
689:
688:
684:
679:
667:
661:
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637:
626:
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612:
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583:
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557:
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541:
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513:
495:
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487:
454:
451:
450:
446:
443:
440:
437:
434:
431:
428:
425:
422:
419:
416:
415:
412:Masked write
407:Row Activate
386:
375:
369:
366:
363:
361:
356:
354:
349:
345:
342:
329:
328:
319:
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185:
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173:
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170:PlayStation 3
167:
163:
153:
151:
147:
143:
139:
135:
131:
123:
113:
110:
102:
99:December 2006
91:
88:
84:
81:
77:
74:
70:
67:
63:
60: –
59:
55:
54:Find sources:
48:
44:
38:
37:
32:This article
30:
26:
21:
20:
1776:
1634:(Mobile DDR)
1570:Asynchronous
1486:
1475:
1464:
1398:
1395:
1386:
1382:
1374:
1369:
1367:
1357:
1354:
1348:
1342:
1336:
1330:
1324:
1318:
1312:
1306:
1303:
1298:
1294:
1290:
1286:
1282:
1280:
1272:
1268:
1262:
1260:
1252:
1248:
1244:
1235:
1226:
1219:
1153:Refresh bank
1064:
902:
863:
782:Bank address
767:Bank address
719:
702:
677:
644:
599:
488:COLM opcode
447:Description
367:
364:
357:
350:
346:
341:single-ended
338:
217:differential
159:
133:
129:
128:
105:
96:
86:
79:
72:
65:
53:
41:Please help
36:verification
33:
1592:Synchronous
919:Row address
545:Row address
482:ROWA opcode
476:ROWP opcode
470:COLX opcode
441:Description
435:Description
429:Description
423:Description
181:Performance
1456:References
1403:4 bits of
885:high bits
883:Write mask
654:high bits
517:Write mask
464:COL opcode
353:active-low
283:Low-power
69:newspapers
58:"XDR DRAM"
1841:Bandwidth
1782:XDR2 DRAM
1605:DDR SDRAM
1445:XDR2 DRAM
1349:110: LRR2
1343:101: LRR1
1337:100: LRR0
1331:011: REFI
1325:010: REFA
1319:001: REFP
1313:000: NOPR
1015:low bits
741:Subopcode
632:high bits
547:high bits
519:low bits
315:FlexPhase
255:packaging
172:console.
125:XDR DRAM.
1861:Category
1777:XDR DRAM
1695:Graphics
1582:EDO DRAM
1577:FPM DRAM
1500:(Rambus)
1494:Archived
1434:See also
1358:reserved
1297:, and BR
1065:reserved
995:low bits
921:low bits
903:reserved
864:reserved
720:reserved
703:reserved
678:reserved
645:reserved
600:reserved
335:Protocol
313:Per-bit
210:Features
156:Overview
130:XDR DRAM
1810:UniDIMM
1674:HBM-PIM
1640:(FCRAM)
325:Latency
168:in the
83:scholar
1764:Rambus
1649:RLDRAM
1564:(DRAM)
1426:value.
1293:, DELR
1285:and BP
291:design
274:1.8 V
85:
78:
71:
64:
56:
1867:SDRAM
1824:Lists
1772:RDRAM
1752:GDDR7
1747:GDDR6
1742:GDDR5
1737:GDDR4
1732:GDDR3
1727:GDDR2
1717:SGRAM
1712:MDRAM
1679:HBM3E
1664:HBM2E
1644:eDRAM
1632:LPDDR
1600:SDRAM
1440:RDRAM
1035:DELR0
1001:DELR1
377:Clock
150:GDDR4
142:RDRAM
90:JSTOR
76:books
1815:CAMM
1805:DIMM
1800:SIMM
1722:GDDR
1707:WRAM
1702:VRAM
1669:HBM3
1659:HBM2
1625:DDR5
1620:DDR4
1615:DDR3
1610:DDR2
1405:1100
1384:0).
1214:SC0
1188:SC1
1159:SC2
970:ROP0
944:ROP1
910:ROP2
893:RQ10
874:DELA
868:POP2
854:DELC
848:RQ11
840:BC0
831:XOP0
814:BC1
805:XOP1
770:XOP2
750:C11
738:XOP3
638:POP0
604:POP1
496:RQ10
455:RQ11
387:NOP
382:Bit
379:edge
228:LVDS
199:Gbit
166:Sony
162:GPUs
148:and
146:DDR2
62:news
1654:HBM
1355:111
1263:not
1211:SR0
1208:BR0
1202:SC0
1196:RQ0
1182:SR1
1179:BR1
1173:SC1
1167:RQ1
1150:BR2
1144:SC2
1138:RQ2
1127:SC3
1112:SC3
1106:RQ3
1098:C4
1080:RQ4
1072:C5
1049:RQ5
1041:C6
1023:RQ6
984:RQ7
976:M4
958:RQ8
950:M5
932:RQ9
924:M6
837:BA0
834:BP0
828:BC0
822:RQ0
811:BA1
808:BP1
802:BC1
796:RQ1
785:BC2
779:BA2
773:BP2
764:BC2
758:RQ2
747:R15
735:C11
729:RQ3
716:C10
713:R14
699:C10
693:RQ4
685:C9
682:R13
662:RQ5
641:R12
621:RQ6
613:M0
610:R11
590:WRX
584:RQ7
576:M1
573:R10
558:RQ8
550:M2
527:RQ9
444:Bit
438:Bit
432:Bit
426:Bit
420:Bit
417:Bit
289:DLL
285:PLL
276:Vdd
45:by
1863::
1156:R0
1124:R1
1095:R2
1086:C4
1069:R3
1055:C5
1038:R4
1029:C6
1010:C7
1007:R5
990:C7
973:R6
947:R7
916:R8
880:M7
668:C9
649:C8
627:C8
542:R9
514:M3
203:GB
152:.
1554:e
1547:t
1540:v
1370:x
1299:x
1295:x
1291:x
1287:x
1283:x
1205:x
1199:x
1193:↑
1176:x
1170:x
1164:↑
1147:x
1141:x
1135:↑
1121:x
1118:x
1109:x
1103:↑
1092:x
1089:x
1083:x
1077:↑
1061:x
1058:x
1052:x
1046:↑
1032:x
1026:x
1020:↑
998:x
987:x
981:↑
967:x
964:x
961:x
955:↑
941:x
938:x
935:x
929:↑
907:x
899:x
896:x
890:↑
860:x
851:x
845:↑
825:x
819:↓
799:x
793:↓
761:x
755:↓
744:x
732:x
726:↓
710:x
707:x
696:x
690:↓
674:x
671:x
665:x
659:↓
635:x
624:x
618:↓
596:x
587:x
581:↓
570:1
567:0
564:1
561:0
555:↓
539:1
536:1
533:0
530:0
524:↓
511:1
508:0
505:0
502:0
499:0
493:↓
485:1
479:0
473:0
467:0
461:0
458:0
452:↓
287:/
230:.
132:(
112:)
106:(
101:)
97:(
87:·
80:·
73:·
66:·
39:.
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