382:
321:
73:. There are also types that have both serial and parallel input and types with serial and parallel output. There are also "bidirectional" shift registers, which allow shifting in both directions: L โ R or R โ L. The serial input and last output of a shift register can also be connected to create a "circular shift register". A PIPO register (parallel in, parallel out) is simply a
346:) the serial data is first loaded into an internal buffer register, then upon receipt of a load signal the state of the buffer register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.
54:, while each bit was stored serially in the shift registers. There is an inherent trade-off in the design of bit arrays; putting more flip-flops in a row allows a single shifter to store more bits, but requires more clock cycles to push the data through all of the shifters before the data can be read back out again.
354:
This configuration has the data input on lines D1 through D4 in parallel format, D1 being the most significant bit. To write the data to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement
551:
of 6-bit upper-case characters using 54 200-bit shift registers (arranged in 6 tracks of 9 packs), providing storage for 1800 characters. The shift register design meant that scrolling the terminal display could be accomplished by simply pausing the display output to skip one line of characters. A
296:
The data is stored after each flip-flop on the "Q" output, so there are four storage "slots" available in this arrangement, hence it is a 4-bit register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As "data in" presents
300:
So the serial output of the entire register is 00010110. It can be seen that if data were to be continued to input, it would get exactly what was put in (10110000), but offset by four "data advance" cycles. This arrangement is the hardware equivalent of a
327:
This configuration allows conversion from serial to parallel format. Data input is serial, as described in the SISO section above. Once the data has been clocked in, it may be either read off at each output simultaneously, or it can be shifted out.
35:, which causes the data stored in the system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this configuration they were used as
297:
1,0,1,1,0,0,0,0 (in that order, with a pulse at "data advance" each timeโthis is called clocking or strobing) to the register, this is the result. The right hand column corresponds to the right-most flip-flop's output pin, and so on.
663:
355:
now acts as a PISO shift register, with D1 as the Data Input. However, as long as the number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.
490:
with the result being fed back to the input of one of the shift registers (the accumulator), which was one bit longer, since binary addition can only result in an answer that has the same size or is one bit longer.
446:
For more outputs, SIPO shift registers are used. The parallel outputs of the shift register and the desired state for all those devices can be sent out of the microcontroller using a single serial connection.
84:
a shift register, but is very fast โ an output is given within a single clock pulse. A "universal" shift register provides bidirectional serial-in and serial-out, as well as parallel-in and parallel-out.
466:, the timing does not depend on component values, but it requires an external clock, and the timing accuracy is limited by the granularity of this clock. An example of such a pulse extender is the
370:
359:
335:. All flip-flops operate at the given clock frequency. Each input bit makes its way down to the Nth output after N clock cycles, leading to parallel output.
285:
These are the simplest kind of shift registers. The data string is presented at "data in" and is shifted right one stage each time "data advance" is brought
486:
In early computers, shift registers were used to handle data processing: two numbers to be added were stored in two shift registers and clocked out into an
686:
737:
454:
or more complicated circuitry) is attached to a parallel input of the shift register, then the data is sent back serially to the microcontroller.
471:
845:
1090:
509:
to "shift right" and "shift left" the data in a register, effectively dividing by two or multiplying by two for each place shifted.
525:
in some devices built in the early 1970s. Shift registers don't need many pins or address decoding logic, so was much cheaper than
440:
343:
443:, which allows any number of binary devices to be accessed using only two to four pins, though more slowly than parallel I/O.
338:
In cases where the parallel outputs should not change during the serial loading process, it's desirable to use a latched or
588:
in the late 1940s. Shift registers made their way into integrated circuits in the 1960s as evidenced by early patents from
1152:
838:
627:
1147:
1137:
610:
831:
729:
678:
585:
436:
419:
Several bidirectional shift registers can also be connected in parallel for a hardware implementation of a
381:
632:
707:
366:
The animation below shows the write/shift sequence, including the internal state of the shift register.
46:
In most cases, several parallel shift registers would be used to build a larger memory pool known as a "
1209:
1121:
980:
403:
One of the most common uses of a shift register is to convert between serial and parallel interfaces.
1214:
1116:
463:
290:
28:
305:. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.
420:
302:
58:
1188:
1162:
1015:
487:
31:
where the output of one flip-flop is connected to the input of the next. They share a single
1183:
526:
62:
312: – each datum is lost once it has been shifted out of the right-most bit.
8:
1111:
548:
521:
shift registers (thousands of bits in size) were used in a similar manner to the earlier
77:
1178:
782:
593:
506:
289:. At each advance, the bit on the far left (i.e. "data in") is shifted into the first
605:
565:
544:
522:
40:
786:
475:
960:
774:
661:, Williams, Marshall, "Shift register delay circuit", issued 1985-07-16
581:
432:
74:
799:
658:
1080:
1075:
1050:
924:
638:
36:
24:
878:
369:
995:
950:
540:
293:'s output. The bit on the far right (i.e. "data out") is shifted out and lost.
813:
1203:
1095:
1055:
1035:
1025:
990:
854:
758:
589:
467:
450:
For more inputs, PISO shift registers are used. Each binary input (such as a
51:
778:
568:, a code-breaking machine built in 1944. It was a six-stage device built of
358:
320:
50:". Data was stored into the array and read back out in parallel, often as a
616:
411:
Serial-in serial-out shift registers can be used as simple delay circuits.
32:
1030:
888:
577:
569:
451:
339:
332:
286:
679:"Inside the Intel 1405: die photos of a shift register memory from 1970"
1157:
564:
One of the first known examples of a shift register was in the Mark 2
1070:
1000:
934:
573:
500:
47:
883:
762:
929:
903:
823:
553:
462:
Shift registers can also be used as pulse extenders. Compared to
385:
99:
Sample usage of a 4-bit shift register. Data input is 10110000.
1020:
985:
955:
919:
621:
398:
1045:
1040:
1065:
1085:
1060:
1010:
1005:
873:
868:
893:
441:
Serial
Peripheral Interface in daisy chain configuration
439:
pins are required than are available, sometimes over a
70:
66:
65:inputs and outputs. These are often configured as
392:
342:output. In a latched shift register (such as the
1201:
518:
349:
315:
474:create the core of the timing logic this way (
88:
16:Computer memory unit using cascaded flip-flops
839:
730:"Inside the Apple-1's shift-register memory"
43:systems in the late 1960s and early 1970s.
846:
832:
431:Shift registers are commonly attached to
331:In this configuration, each flip-flop is
676:
657:
576:. A shift register was also used in the
512:
380:
357:
757:
717:. Datapoint Corporation. December 1976.
1202:
494:
93:
827:
727:
708:"DataPoint 3300 Maintenance Manual"
13:
853:
814:"Electronic shift register system"
767:Annals of the History of Computing
481:
457:
368:
319:
14:
1226:
388:TC4015BP dual SIPO shift register
552:similar design was used for the
505:Many computer languages include
426:
71:"parallel-in, serial-out" (PISO)
67:"serial-in, parallel-out" (SIPO)
740:from the original on 2023-06-06
689:from the original on 2023-07-28
628:Serial Peripheral Interface Bus
488:arithmetic and logic unit (ALU)
806:
792:
751:
721:
700:
670:
651:
611:Linear-feedback shift register
393:Serial and parallel conversion
57:Shift registers can have both
1:
644:
350:Parallel-in serial-out (PISO)
316:Serial-in parallel-out (SIPO)
1138:block ciphers in stream mode
586:Institute for Advanced Study
437:general-purpose input/output
7:
633:Shift register lookup table
599:
547:display of 25 rows of
89:Serial-in serial-out (SISO)
10:
1231:
1122:alternating step generator
592:and Kent Smith working at
559:
543:, for example, stored its
498:
396:
308:This arrangement performs
1171:
1130:
1104:
973:
943:
912:
902:
861:
624:(Serializer/Deserializer)
464:monostable multivibrators
362:4-Bit PISO Shift Register
1117:self-shrinking generator
763:"The Design of Colossus"
414:
406:
800:"Shift register system"
779:10.1109/MAHC.1983.10079
376:
677:Shirriff, Ken (2014).
389:
373:
363:
324:
1189:stream cipher attacks
533:was sometimes called
531:shift register memory
513:Shift register memory
472:74164 shift registers
384:
372:
361:
323:
1184:correlation immunity
527:random-access memory
519:serial-in serial-out
1112:shrinking generator
862:Widely used ciphers
734:Ken Shirriff's blog
683:Ken Shirriff's blog
541:Datapoint 3300
495:Bitshift operations
310:destructive readout
100:
94:Destructive readout
27:using a cascade of
1179:correlation attack
759:Flowers, Thomas H.
594:General Instrument
584:and others at the
535:circulating memory
507:bitwise operations
390:
374:
364:
325:
98:
1210:Digital registers
1197:
1196:
969:
968:
606:Delay-line memory
523:delay-line memory
283:
282:
41:delay-line memory
1222:
910:
909:
848:
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712:
704:
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674:
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655:
582:John von Neumann
529:back then. Such
433:microcontrollers
101:
97:
1230:
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1225:
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1223:
1221:
1220:
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1215:Computer memory
1200:
1199:
1198:
1193:
1167:
1126:
1100:
965:
939:
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822:
821:
812:
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797:
793:
756:
752:
743:
741:
728:Shirriff, Ken.
726:
722:
710:
706:
705:
701:
692:
690:
675:
671:
664:
656:
652:
647:
639:Circular buffer
602:
562:
549:72 columns
515:
503:
497:
484:
482:Data processing
470:, wherein five
460:
458:Pulse extenders
429:
417:
409:
401:
395:
379:
352:
318:
126:
121:
116:
111:
106:
96:
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37:computer memory
25:digital circuit
17:
12:
11:
5:
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1186:
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1143:shift register
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1128:
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1125:
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1101:
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1013:
1008:
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993:
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983:
977:
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966:
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953:
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927:
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916:
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907:
900:
899:
897:
896:
891:
886:
881:
876:
871:
865:
863:
859:
858:
855:Stream ciphers
851:
850:
843:
836:
828:
820:
819:
805:
791:
750:
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699:
669:
649:
648:
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642:
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499:Main article:
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333:edge triggered
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21:shift register
15:
9:
6:
4:
3:
2:
1227:
1216:
1213:
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1205:
1190:
1187:
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1177:
1176:
1174:
1170:
1164:
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1024:
1022:
1019:
1017:
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1007:
1004:
1002:
999:
997:
994:
992:
989:
987:
984:
982:
979:
978:
976:
974:Other ciphers
972:
962:
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957:
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952:
949:
948:
946:
942:
936:
933:
931:
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826:
815:
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801:
795:
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784:
780:
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768:
764:
760:
754:
739:
735:
731:
724:
716:
715:bitsavers.org
709:
703:
688:
684:
680:
673:
660:
654:
650:
640:
637:
634:
631:
629:
626:
623:
620:
618:
615:
612:
609:
607:
604:
603:
597:
595:
591:
590:Frank Wanlass
587:
583:
579:
575:
571:
567:
557:
556:'s terminal.
555:
550:
546:
542:
538:
536:
532:
528:
524:
520:
510:
508:
502:
492:
489:
479:
477:
473:
469:
468:Ronja Twister
465:
455:
453:
448:
444:
442:
438:
434:
427:More I/O pins
424:
422:
412:
404:
400:
387:
383:
371:
367:
360:
356:
347:
345:
341:
336:
334:
329:
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313:
311:
306:
304:
298:
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288:
278:
275:
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269:
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210:
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118:
113:
108:
103:
102:
86:
83:
79:
76:
72:
68:
64:
60:
55:
53:
52:computer word
49:
44:
42:
39:, displacing
38:
34:
30:
26:
23:is a type of
22:
1142:
808:
794:
770:
766:
753:
742:. Retrieved
733:
723:
714:
702:
691:. Retrieved
682:
672:
653:
617:Ring counter
570:vacuum tubes
563:
539:
534:
530:
516:
504:
485:
461:
449:
445:
430:
418:
410:
402:
365:
353:
337:
330:
326:
309:
307:
299:
295:
284:
81:
56:
45:
33:clock signal
20:
18:
580:, built by
578:IAS machine
517:Very large
1204:Categories
1158:T-function
1105:Generators
981:Achterbahn
773:(3): 246,
744:2023-08-04
693:2023-08-06
659:US4530107A
645:References
574:thyratrons
435:when more
397:See also:
29:flip-flops
1071:SOBER-128
1001:KCipher-2
935:SOSEMANUK
906:Portfolio
501:Bitshifts
476:schematic
291:flip-flop
48:bit array
944:Hardware
913:Software
884:Crypto-1
787:39816473
761:(1983),
738:Archived
687:Archived
600:See also
566:Colossus
545:terminal
340:buffered
125:Output 4
120:Output 3
115:Output 2
110:Output 1
78:register
59:parallel
1172:Attacks
961:Trivium
930:Salsa20
904:eSTREAM
560:History
554:Apple I
386:Toshiba
80:and is
1131:Theory
1081:Turing
1076:Spritz
1051:Scream
1021:Phelix
1016:Panama
986:F-FCSR
956:MICKEY
925:Rabbit
920:HC-128
879:ChaCha
785:
665:
622:SerDes
613:(LFSR)
452:button
399:SerDes
75:D-type
69:or as
63:serial
1153:NLFSR
1066:SOBER
996:ISAAC
951:Grain
783:S2CID
711:(PDF)
635:(SRL)
421:stack
415:Stack
407:Delay
344:74595
303:queue
1148:LFSR
1096:WAKE
1091:VMPC
1086:VEST
1061:SNOW
1056:SEAL
1046:RC4A
1041:RC4+
1036:QUAD
1026:Pike
1011:ORYX
1006:MUGI
991:FISH
874:A5/2
869:A5/1
572:and
377:Uses
287:high
105:Time
61:and
894:RC4
775:doi
478:).
82:not
1206::
1163:IV
1031:Py
889:E0
781:,
769:,
765:,
736:.
732:.
713:.
685:.
681:.
596:.
537:.
423:.
279:0
267:8
262:1
250:7
245:1
233:6
228:0
216:5
211:1
199:4
194:0
182:3
177:0
165:2
160:0
148:1
143:0
131:0
19:A
847:e
840:t
833:v
816:.
802:.
777::
771:5
747:.
696:.
276:0
273:0
270:0
259:0
256:0
253:0
242:1
239:0
236:0
225:1
222:1
219:0
208:0
205:1
202:1
191:1
188:0
185:1
174:0
171:1
168:0
157:0
154:0
151:1
140:0
137:0
134:0
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