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packet contains a header with address command and status information, payload (from 0 through optional lengths of data) and a CRC check symbol. The first symbol in the packet header contains the destination node address. If the address is not within the domain handled by the receiving node, the packet is passed to the output through the bypass FIFO. In the other case, the packet is fed to a receive queue and may be transferred to a ring in another dimension. All packets are marked when they pass the scrubber (a node is established as scrubber when the ring is initialized). Packets without a valid destination address will be removed when passing the scrubber for the second time to avoid filling the ring with packets that would otherwise circulate indefinitely.
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states – home, fresh, gone). Associated with each node is also a cache for holding remote data with a directory containing forward and backward pointers to nodes in the linked list sharing the cache line. The tag for the cache has seven states (invalid, only fresh, head fresh, only dirty, head dirty, mid valid, tail valid).
316:
Gustavson led a group called the
Scalable Coherent Interface and Serial Express Users, Developers, and Manufacturers Association and maintained a web site for the technology starting in 1996. A series of workshops were held through 1999. After the first 1992 edition, follow-on projects defined shared
283:
and disabling the cache for data that were shared between two or more processors. These methods were feasible when the performance difference between the cache and memory were less than one order of magnitude. Modern processors with caches that are more than two orders of magnitude faster than main
157:
David V. James was a major contributor for writing the specifications including the executable C-code. Stein
Gjessing’s group at the University of Oslo used formal methods to verify the coherence protocol and Dolphin Server Technology implemented a node controller chip including the cache coherence
295:
of nodes containing processors that share a particular cache line. Each node holds a directory for the main memory of the node with a tag for each line of memory (same line length as the cache line). The memory tag holds a pointer to the head of the linked list and a state code for the line (three
312:
family for connecting different systems. Different system vendors implemented different variants of SCI for their internal system infrastructure. These different implementations interface to very intricate mechanisms in processors and memory systems and each vendor has to preserve some degrees of
267:
SCI sends information in packets. Each packet consists of an unbroken sequence of 16-bit symbols. The symbol is accompanied by a flag bit. A transition of the flag bit from 0 to 1 indicates the start of a packet. A transition from 1 to 0 occurs 1 (for echoes) or 4 symbols before the packet end. A
153:
The original intent was a single standard for all buses in the computer. The working group soon came up with the idea of using point-to-point communication in the form of insertion rings. This avoided the lumped capacitance, limited physical length/speed of light problems and stub reflections in
258:
is a combination of rings in two dimensions. Switching between the two dimensions requires a small switching capability in the node. This can be expanded to three or more dimensions. The concept of folding rings can also be applied to the Torus topologies to avoid any long connection segments.
223:
model. (The other popular models for cache coherency are based on system-wide eavesdropping (snooping) of memory transactions – a scheme which is not very scalable.) In SCI each node contains a directory with a pointer to the next node in a linked list that shares a particular cache line.
154:
addition to allowing parallel transactions. The use of insertion rings is credited to
Manolis Katevenis who suggested it at one of the early meetings of the working group. The working group for developing the standard was led by David B. Gustavson (chair) and David V. James (Vice Chair).
177:(using cache controller and link controller chips from Dolphin), Sequent and Cray Research. Dolphin Interconnect Solutions implemented a PCI and PCI-Express connected derivative of SCI that provides non-coherent shared memory access. This implementation was used by
97:
The IEEE Std 1596-1992, IEEE Standard for
Scalable Coherent Interface (SCI) was approved by the IEEE standards board on March 19, 1992. It saw some use during the 1990s, but never became widely used and has been replaced by other systems from the early 2000s.
126:(IEEE) spun off to form a standard targeted at this market in July 1988. It was essentially a subset of Futurebus features that could be easily implemented at high speed, along with minor additions to make it easier to connect to other systems, such as
288:) methods since buses are inherently broadcast. Modern systems with point-to point links use broadcast methods with snoop filter options to improve performance. Since broadcast and eavesdropping are inherently non-scalable, these are not used in SCI.
227:
SCI defines a 64-bit flat address space (16 exabytes) where 16 bits are used for identifying a node (65,536 nodes) and 48 bits for address within the node (256 terabytes). A node can contain many processors and/or memory. The SCI standard defines a
325:
corporation was formed to hold patents on an attempt to define a new memory interface that was related to another working group called SerialExpress or Local Area Memory Port. However, by early 1999 the new memory standard was abandoned.
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The distributed directory is scalable. The overhead for the directory based cache coherence is a constant percentage of the node’s memory and cache. This percentage is in the order of 4% for the memory and 7% for the cache.
212:
The logical level that describes the address space, data transfer protocols, cache coherence mechanisms, synchronization primitives, control and status registers, and initialization and error recovery facilities.
146:, Sequent, AT&T, Digital Equipment Corporation, McDonnell Douglas, National Semiconductor, Stanford Linear Accelerator Center, Tektronix, Texas Instruments, Unisys, University of Oslo,
1764:
251:
The most common way to describe these multi-dimensional topologies is k-ary n-cubes (or tori). The SCI standard specification mentions several such topologies as examples.
27:
247:
In distributed switching systems, each node can be connected to a ring of arbitrary length and either all or some of the nodes can be connected to two or more rings.
308:
SCI is a standard for connecting the different resources within a multiprocessor computer system, and it is not as widely known to the public as for example the
118:
marketplace by the time it would be released in the early 1990s. In response, a "Superbus" study group was formed in
November 1987. Another working group of the
94:
and a simple interface; i.e. a standard to replace existing buses in multiprocessor systems with one with no inherent scalability and performance limitations.
123:
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ensures data consistency in multiprocessor systems. The simplest form applied in earlier systems was based on clearing the cache contents between
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and several others including volume applications for message passing within HPC clustering and medical imaging. SCI was often used to implement
90:), is a high-speed interconnect standard for shared memory multiprocessing and message passing. The goal was to scale well, provide system-wide
334:
1928:
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memory would not perform anywhere near optimal without more sophisticated methods for data consistency. Bus based systems use eavesdropping (
1971:
1465:
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.
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This structure allowed new developments in physical interface technology to be easily adapted without any redesign on the logical level.
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SCI can be used to build systems with different types of switching topologies from centralized to fully distributed switching:
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David V. James; David B. Gustavson; B. Fleischer (May–Jun 1998). "SerialExpress-a high performance workstation interconnect".
1118:
789:
591:
EEE Standard for High-Bandwidth Memory
Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)
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In 1999 a series of papers was published as a book on SCI. An updated specification was published in July 2000 by the
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134:. Representatives from companies in the computer industry and research community included Amdahl, Apple Computer,
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1996:
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With a central switch, each node is connected to the switch with a ringlet (in this case a two-node ring).
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as the processor memory bus in their NUMA-Q systems. Numascale developed a derivative to connect with
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The physical level that deals with electrical signals, connectors, mechanical and thermal conditions
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SCI: Scalable
Coherent Interface: Architecture and Software for High-Performance Compute Clusters
483:"Scalable Coherent Interface and Serial Express Users, Developers, and Manufacturers Association"
447:
229:
147:
539:
IEEE Standard for Shared-Data
Formats Optimized for Scalable Coherent Interface (SCI) Processors
1986:
1547:
1030:
565:
IEEE Standard for Low-Voltage
Differential Signals (LVDS) for Scalable Coherent Interface (SCI)
20:
Scalable
Coherent Interface and Serial Express Users, Developers, and Manufacturers Association
322:
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1903:
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1294:
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1103:
875:
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114:(IEEE 896) project in 1987, some engineers predicted it would already be too slow for the
8:
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High-speed interconnect standard for shared memory multiprocessing and message passing
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2016:
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in 1996, and a memory interface known as Ramlink later in 1996. In January 1998, the
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Instead, SCI uses a distributed directory-based cache coherence protocol with a
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Different versions and derivatives of SCI were implemented by companies like
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709:. International Standard ISO/IEC 13961 IEEE Std 1596. July 10, 2000.
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448:"The Scalable Coherent Interface and Related Standards Projects"
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Scalability for large systems is achieved through a distributed
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130:. Most of the developers had their background from high-speed
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508:"1596 WG - Working Group for Scalable Coherent Interface"
482:
65:
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Hermann Hellwagner; Alexander Reinefeld, eds. (1999).
422:
IEEE Standard for Scalable Coherent Interface (SCI)
614:
445:
124:Institute of Electrical and Electronics Engineers
2826:
1068:Coherent Accelerator Processor Interface (CAPI)
680:. Lecture Notes in Computer Science. Springer.
335:International Organization for Standardization
313:compatibility for both hardware and software.
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731:
656:
594:. IEEE Standards Board. September 16, 1996.
205:The standard defined two interface levels:
1505:
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738:
724:
25:
331:International Electrotechnical Commission
615:David B. Gustavson (February 10, 1999).
542:. IEEE Standards Board. April 25, 1994.
160:
568:. IEEE Standards Board. July 31, 1996.
415:
413:
2827:
659:"ISSCC: SLDRAM group morphs to DDR II"
477:
475:
317:data formats in 1993, a version using
1486:
719:
446:David B. Gustavson (September 1991).
410:
657:David Lammers (February 19, 1999).
472:
189:architectures. It was also used by
142:, CERN, Dolphin Server Technology,
13:
1512:
459:Stanford Linear Accelerator Center
319:low-voltage differential signaling
271:
14:
2851:
703:Scalable Coherent Interface (SCI)
1469:
1468:
31:Group that supports the standard
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669:
650:
262:
221:directory-based cache coherence
200:
623:
608:
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530:
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425:. IEEE Standards Board. 1992.
348:Dolphin Interconnect Solutions
171:Dolphin Interconnect Solutions
84:Scalable Coherent Interconnect
1:
1063:Intel Ultra Path Interconnect
617:"Organizing for Alternatives"
404:
235:
1041:Intel QuickPath Interconnect
1031:Direct Media Interface (DMI)
165:Block diagram of one example
7:
340:
181:for its high-end clusters,
80:Scalable Coherent Interface
10:
2856:
2809:IEEE Standards Association
1026:Compute Express Link (CXL)
116:high performance computing
101:
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2717:
2615:
2355:
2055:
1937:
1832:
1823:
1520:
1462:
1421:
1400:
1349:
1263:IEEE-1284 (parallel port)
1185:
1178:logical device interface)
1081:
833:
767:
353:List of device bandwidths
303:
187:non-uniform memory access
60:
52:
44:
36:
24:
337:(ISO) as ISO/IEC 13961.
191:Sequent Computer Systems
2814:Category:IEEE standards
230:packet switched network
195:coherent HyperTransport
148:University of Wisconsin
825:List of bus bandwidths
512:Working group web site
166:
455:SLAC Publication 5656
164:
120:standards association
110:(IEEE 960) follow-on
1268:IEEE-1394 (FireWire)
1006:PCI Extended (PCI-X)
1109:Parallel ATA (PATA)
175:Data General AViiON
21:
1016:PCI Express (PCIe)
638:(3). IEEE: 54–65.
167:
19:
2840:Computer networks
2822:
2821:
2713:
2712:
1480:
1479:
1466:
1193:Apple Desktop Bus
1170:PCI Express (via
1129:Serial ATA (SATA)
815:Network on a chip
644:10.1109/40.683105
76:
75:
2847:
1830:
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1507:
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926:HP Precision Bus
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518:on March 4, 2016
514:. Archived from
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281:context switches
179:Sun Microsystems
92:memory coherence
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1258:IEEE-488 (GPIB)
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886:Europe Card Bus
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277:Cache coherence
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140:Hewlett-Packard
106:Soon after the
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1208:Commodore bus
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1156:Fibre Channel
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820:Plug and play
818:
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811:
810:Bus mastering
808:
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333:(IEC) of the
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144:Cray Research
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28:
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961:TURBOchannel
751:
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671:
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635:
631:
625:
610:
590:
584:
564:
558:
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532:
520:. Retrieved
516:the original
511:
502:
490:. Retrieved
486:
462:. Retrieved
454:
441:
421:
328:
315:
307:
298:
290:
275:
266:
263:Transactions
253:
250:
239:
226:
218:
215:
204:
201:The standard
183:Thales Group
168:
156:
152:
105:
96:
87:
83:
79:
77:
37:Abbreviation
2376:legacy mode
1434:CoreConnect
1413:ExpressCard
1341:Thunderbolt
1331:Camera Link
1114:Bus and Tag
800:Address bus
795:Control bus
790:Daisy chain
293:linked list
2829:Categories
2754:Superseded
1825:802 series
1287:ACCESS.bus
1186:Peripheral
986:InfiniBand
981:HP GSC bus
775:System bus
632:IEEE Micro
522:August 31,
492:August 31,
464:August 31,
405:References
398:InfiniBand
236:Topologies
173:, Convex,
56:Non-profit
2629:Bluetooth
1248:Lightning
1198:Atari SIO
1073:SpaceWire
906:Zorro III
846:S-100 bus
841:SS-50 bus
834:Standards
754:standards
747:Technical
393:Futurebus
373:IEEE 1355
363:QuickRing
112:Futurebus
45:Formation
2804:See also
2761:754-1985
2718:Proposed
2062:Ethernet
1548:Revision
1474:Category
1449:Wishbone
1422:Embedded
1401:Portable
1321:Profibus
1253:DMX512-A
1139:Parallel
991:Ethernet
901:Zorro II
851:Multibus
752:de facto
663:EE Times
358:NUMAlink
341:See also
310:Ethernet
286:snooping
254:The 2-D
136:BB&N
2745:P1906.1
2606:Wi-Fi 8
2582:Wi-Fi 7
2548:Wi-Fi 6
2497:Wi-Fi 5
2442:Wi-Fi 4
1521:Current
1454:SLIMbus
1408:PC Card
1392:TOSLINK
1082:Storage
1036:RapidIO
916:FASTBUS
871:STD Bus
768:General
383:Myrinet
378:RapidIO
158:logic.
122:of the
108:Fastbus
102:History
68:.scizzl
61:Website
2649:Zigbee
2617:802.15
2357:802.11
1595:1149.1
1387:S/PDIF
1278:1-Wire
1243:RS-485
1238:RS-423
1233:RS-422
1228:RS-232
1089:ST-506
1046:NVLink
896:STEbus
856:Unibus
684:
598:
572:
546:
429:
323:SLDRAM
304:Legacy
128:VMEbus
40:SCIzzL
2740:P1823
2735:P1699
2730:P1619
2725:P1363
2507:WiGig
2371:-1997
2362:Wi-Fi
2071:-1983
2057:802.3
1939:802.1
1815:42010
1810:29148
1805:16326
1800:16085
1795:14764
1790:12207
1785:11073
1382:McASP
1350:Audio
1295:SMBus
1291:PMBus
1273:UNI/O
1213:HP-IL
1166:SATAe
1151:ESCON
1124:HIPPI
956:NuBus
911:CAMAC
881:Q-Bus
876:SMBus
861:VAXBI
758:wired
707:(PDF)
451:(PDF)
388:QsNet
368:HIPPI
256:torus
2791:1471
2786:1364
2781:1362
2776:1233
2771:1219
2041:LACP
1780:2050
1775:2030
1770:1905
1765:1904
1760:1902
1755:1901
1750:1900
1745:1855
1740:1850
1735:1849
1730:1815
1725:1801
1720:1800
1715:1733
1710:1722
1705:1685
1700:1675
1695:1667
1690:1666
1685:1619
1680:1613
1675:1603
1670:1596
1665:1588
1660:1584
1655:1547
1650:1541
1645:1516
1640:1497
1635:1451
1630:1394
1625:1355
1620:1284
1615:1278
1610:1275
1605:1164
1600:1154
1590:1076
1585:1016
1580:1014
1575:1003
1439:AMBA
1377:MADI
1362:AES3
1223:MIDI
1176:NVMe
1172:AHCI
1134:SCSI
1119:DSSI
1094:ESDI
971:SBus
931:EISA
866:MBus
756:for
749:and
682:ISBN
596:ISBN
570:ISBN
544:ISBN
524:2013
494:2013
466:2013
427:ISBN
78:The
70:.com
53:Type
48:1996
2766:830
2690:.4z
2685:.4g
2680:.4f
2675:.4e
2670:.4d
2665:.4c
2660:.4b
2655:.4a
1982:Qbb
1977:Qaz
1972:Qay
1967:Qat
1962:Qav
1929:.24
1924:.22
1919:.21
1914:.20
1909:.18
1904:.17
1892:.16
1887:.14
1882:.12
1877:.10
1834:802
1570:896
1565:829
1560:828
1555:854
1543:754
1538:730
1533:693
1528:488
1443:AXI
1372:I²S
1326:USB
1311:D²B
1306:SPI
1301:I3C
1283:I²C
1218:HIL
1203:DCB
1174:or
1161:SSA
1144:SAS
1104:SMD
1099:IPI
1021:AGP
1011:PXI
1001:PCI
996:UPA
976:VLB
966:MCA
951:VPX
946:VXS
941:VXI
936:VME
921:LPC
891:ISA
640:doi
88:SCI
82:or
66:www
2831::
2705:.7
2700:.6
2695:.5
2645:.4
2640:.3
2635:.2
2625:.1
2601:bn
2596:bk
2593:bi
2590:bh
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2577:be
2572:bd
2569:bc
2565:bb
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2558:az
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2503:ad
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2347:df
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2337:dd
2332:db
2327:da
2322:cz
2317:cy
2312:cx
2307:cw
2302:cv
2297:cu
2292:ct
2287:cs
2282:cr
2277:cq
2272:cp
2267:cn
2262:cm
2257:ck
2252:ch
2247:cg
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2237:cd
2232:cc
2227:cb
2222:ca
2217:bz
2212:by
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2201:bt
2195:ba
2190:az
2185:av
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2174:at
2168:aq
2163:an
2158:ak
2153:ah
2147:af
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2136:ad
2131:ac
2126:ab
2047:BA
2037:AX
2032:AS
2027:aq
2022:ak
2017:ah
2012:ag
2007:AE
2002:ad
1997:AB
1872:.9
1867:.8
1862:.7
1857:.6
1852:.5
1847:.4
1842:.2
1293:,
1289:,
661:.
636:18
634:.
510:.
485:.
474:^
457:.
453:.
412:^
232:.
197:.
150:.
138:,
2651:)
2647:(
2631:)
2627:(
2608:)
2604:(
2584:)
2580:(
2550:)
2546:(
2509:)
2505:(
2499:)
2495:(
2483:z
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