Synchronous dynamic random-access memory

2625:

datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock

3227:

command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.

2300: 3655: 2632:), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus, a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth. 2485:, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an 2478:

option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified.

2827: 1525: 2950: 1798:

cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.

1601: 3432:

SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.)

1778:

standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).

2474:. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line. 3436:

DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array.

3548:(GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2023, there are eight successive generations of GDDR: 3444:

cells.) The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads.

3439:

Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a

3435:

To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the

3357:

Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address

3124:

in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012, and later (during 2010) expected to be released in 2015, before samples were announced in early 2011 and manufacturers

2569:

Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh

2446:

Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data

2435:

A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command

2382:

When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at

1773:

In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally

1591:

means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a

2860:

Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is

2620:

The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result

2573:

SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits

2378:

command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be

3450:

A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits

3226:

SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the

3101:

DDR3 memory chips are being made commercially, and computer systems using them were available from the second half of 2007, with significant usage from 2008 onwards. Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667

3068:

Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is

2597:

precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as

2541:

It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains

3431:

VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of

3038:

interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR

1816:

appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from

3209:

SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its

2986:

A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz. The PC100 standard specifies the capabilities of the memory module as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.

2532:

Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit

2520:

M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the

3443:

Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM

3064:

DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be

2450:

Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient

1797:

clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock

3049:

Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.

2624:

In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent

2477:

Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type

3086:

DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a

2506:

Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode

1777:

SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100

2527:

M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will

2320:

command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of

2554:

As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is

2489:

operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2. Although more confusing to humans, this can be easier to implement in hardware, and is preferred by

3395:

Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same

2447:

are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect).

2370:

command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.

2616:

Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur.

1763: Hz) to 5 ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly. 2407:

The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time

2497:

If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order.

3214:

and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like

3180:

In March 2017, JEDEC announced a DDR5 standard is under development, but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.

3200:

was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR SDRAM.

2307:

As an example, a 512 MB SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM

3125:

began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.

1574:

that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called

2561:

If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval

3033:

While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a

3065:

doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.

3069:

now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.

2864:

Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V.

2470:. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word 5997:

Kalter, H. L.; Stapper, C. H.; Barth, J. E.; Dilorenzo, J.; Drake, C. E.; Fifield, J. A.; Kelley, G. A.; Lewis, S. C.; van der Hoeven, W. B.; Jankosky, J. A. (1990). "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC".

2442:

Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst.

2542:

an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 8192 in the example we have been using) every refresh interval (t

1616:

The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.

2849:, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin 3014:

form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second (=1.066 GB/s). (1 GB/s = one billion bytes per second) PC133 is

3415:

because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the

1774:

increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.

1735:

There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM (1 MHz =

3396:

multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time.

1885:

SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.

7765: 3094:. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a 2398:

command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance.

2312:

internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.

2578:(LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE. 3154:

validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process. In January 2011,

6334: 7640: 7264: 3072:

Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz).

6051:

The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.

2363:

commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).

3358:

were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.)

1770:, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM. 2427:

When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands.

2868:

This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors

1894:

Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.

1681:

to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for

3411:, but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of 1666:

due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective

3136:

per second. They were expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz and lowered voltage of 1.05 V by 2013.

7088: 3440:

17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.

7733: 7489: 7675: 3627:. It is designed to be used in conjunction with high-performance graphics accelerators and network devices. The first HBM memory chip was produced by SK Hynix in 2013. 3102:

and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common. Performance up to DDR3-2800 (PC3 22400 modules) are available.

7776: 3039:

interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.

7891: 1761: 2968:. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin 2570:

mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference.

2340:

before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an

2628:

The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as

2390:

Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t

7989: 7296: 7201: 3447:

The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge.

1562:

interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a

6695: 6818: 6436: 2593:

The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases:

7994: 7984: 6338: 2895:. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin 7515: 2574:

self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in

7338: 6943: 1662:

SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous

6642: 6519: 2907: 2439:

If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5.

6109: 7707: 7614: 7585: 7058: 6726: 3475:(writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike 3459:

Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as

2387:, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank. 3158:

announced the completion and release for testing of a 30 nm 2048 MB DDR4 DRAM module. It has a maximum bandwidth of 2.13

2352:

command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.

7918: 8309: 2436:

will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5.

1786:

All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly

1566:

interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by

5082: 2999: 2965: 2892: 2609:

wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50

2594: 7378: 1806:

chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.

637: 5748: 4916: 7560: 6384: 3006:

operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin

6600: 6567: 6482: 4532: 4345: 4191: 1511: 6359: 1052: 6410: 6500: 3816: 3612: 2705: 6207: 1585:

fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.

7432: 3399:

There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters.

2566:, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings. 2514:

M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).

6852: 6298: 1261: 213: 6669: 258: 6792: 5981: 5954: 5927: 2336:

commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t

1000: 943: 263: 7833: 6316: 6268: 3046:

for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.

2558:

If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again.

2420:.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, t 8340: 5113: 3715: 111: 7190: 1581:, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an 1326: 986: 930: 6440: 2379:

done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line.

8021: 6255: 3425: 3147:

prefetch as DDR3. Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.

1012: 681: 493: 89: 6225: 2454:

If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command.

7802: 7324: 1876:, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands. 1592:

fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.

1361: 6461: 8170: 8030: 7940: 6782: 5895: 3476: 2841:

48LC32M8A2 SDRAM chips. They run at 133 MHz (7.5 ns clock period) and have 8-bit wide data buses.

2793: 2777: 2747: 712: 607: 508: 7490:"Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications" 669: 7525: 7125: 2510:

The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle.

2276:

DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer

6970: 6280: 3384:

A notable omission from the specification was per-byte write enables; it was designed for systems with

2903:

form factors. The theoretical bandwidth is 533 MB/s. (1 MB/s = one million bytes per second)

2383:

the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t

1628:

RAM and presented their results at the International Solid-State Circuits Convention in 1990. In 1998,

1504: 1301: 1200: 1072: 702: 691: 7892:"Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems" 7641:"Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications" 6932: 3098:

of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).

800: 7265:"Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications" 6994: 6152: 5877: 2546:= 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued. 2251:

The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)

2226:

Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged.

563: 498: 393: 17: 6633: 3636: 2524:

M3: Burst type. 0 - requests sequential burst ordering, while 1 requests interleaved burst ordering.

1655:) the same year and mass-produced in 1993. By 2000, SDRAM had replaced virtually all other types of 5894:

A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in

3545: 2613:, depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns. 2286:

controls it, during which the other control lines are used as row address bits 16, 15 and 14. When

1373: 1356: 845: 131: 5919:

Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer

3087:

400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second.

7555: 3421: 1368: 1185: 908: 313: 148: 126: 106: 59: 8299: 3189:

In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM.

2257:

All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being:

6903: 5882: 3620: 2869: 2482: 2471: 1241: 458: 328: 268: 7047: 6192: 2528:

continue until interrupted. Full-row bursts are only permitted with the sequential burst type.

590: 8122: 7865: 7738: 7645: 7463: 7458: 7406: 7401: 7343: 7269: 6939: 5682: 5086: 4561: 3794: 3608: 3603: 3507: 3502:μPD481850, introduced in December 1994. The earliest known commercial device to use SGRAM is 3483:, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the 3121: 3091: 1667: 1497: 744: 662: 448: 253: 233: 223: 79: 44: 7978: 1739: 8283: 7156: 6544: 6007: 3918: 2976: 2961: 2888: 1588: 1571: 1547:

where the operation of its external pin interface is coordinated by an externally supplied

1440: 1308: 1087: 1047: 970: 583: 488: 378: 273: 136: 116: 99: 94: 8314: 7370: 3644: 8: 7772: 7711: 7680: 7191:"EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP" 7161: 7093: 6823: 5262: 3906: 3866: 3752: 3616: 3591: 3219:, SLDRAM uses a double-pumped bus, giving it an effective speed of 400, 600, or 800 3016: 2980: 2873: 1712: 1648: 1605: 1346: 1037: 975: 960: 827: 779: 632: 443: 141: 6011: 3668:

Please help update this article to reflect recent events or newly available information.

8154: 8014: 7318: 3515: 3511: 2831: 1701: 1673:

Today, virtually all SDRAM is manufactured in compliance with standards established by

1582: 1555: 1446: 1411: 1057: 483: 468: 413: 408: 398: 373: 298: 7999: 2533:

extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2).

7547: 7520: 6177: 6041: 5977: 5950: 5923: 5707: 3417: 3163: 2838: 1852:, column address strobe. This is also not a strobe, rather a command bit. Along with 1720: 1697: 1123: 1118: 1042: 1007: 861: 839: 738: 697: 600: 438: 163: 6609: 6576: 6240: 3640: 6363: 6015: 3533: 3132:

or less, compared to the 1.5 V of DDR3 chips, and have in excess of 2 billion

3035: 2726: 2586:

DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple

1724: 1633: 1625: 1458: 1452: 1378: 1341: 1331: 1296: 1108: 1062: 1030: 805: 788: 473: 433: 193: 178: 74: 64: 7089:"Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option" 3230:

The basic read/write command consisted of (beginning with CA9 of the first word):

8106: 7970:

Everything you always wanted to know about SDRAM (memory), but were afraid to ask

6856: 6414: 6036: 5971: 5944: 5917: 3484: 3368:

CMD4=1 to open (activate) the specified row; CMD4=0 to use the currently open row

2876:(FPM-RAM) which took typically two or three clocks to transfer one word of data. 1351: 1178: 1165: 856: 851: 707: 574: 553: 528: 388: 308: 238: 208: 183: 69: 40: 6520:"DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond" 8335: 7834:"Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand" 3460: 2931: 2322: 2273:

DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"

1678: 1663: 1470: 1388: 1231: 888: 750: 686: 558: 543: 523: 518: 463: 428: 383: 333: 323: 318: 303: 198: 188: 121: 7734:"Samsung Electronics Develops Industry's First Ultra-Fast GDDR4 Graphics DRAM" 2299: 8329: 8260: 8175: 8007: 6975: 6096: 5824: 5028: 4444: 4439: 4169: 3871: 3583:

GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16

3480: 3211: 3133: 2927: 1476: 1103: 1098: 1067: 822: 732: 548: 538: 533: 513: 348: 338: 218: 203: 6849: 2279: 7860: 7676:"Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics" 7301: 6660: 5584: 5558: 4872: 4818: 4790: 2923: 2915: 2486: 1705: 1548: 1423: 1417: 1383: 1251: 1206: 1190: 1082: 878: 873: 833: 795: 478: 453: 353: 288: 243: 228: 7239: 7022: 6878: 6462:"Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology" 8220: 8215: 8210: 8205: 8200: 8195: 3464: 3095: 2125:

Write with auto precharge: as above, and precharge (close row) when done

1787: 1767: 1577: 1544: 1482: 1434: 868: 403: 343: 248: 6754: 2249:

Load mode register: A0 through A9 are loaded to configure the DRAM chip.

2073:

Read with auto precharge: as above, and precharge (close row) when done

1817:

the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.

8190: 8093: 8088: 8083: 8078: 4275: 3537: 3527: 3468: 3389: 3175: 3117: 3111: 3081: 3059: 2943: 2854: 2834: 2826: 2803: 2785: 2758: 2663: 2657: 2651: 2645: 2610: 2575: 2555:

permissible to change the clock rate, or even stop the clock entirely.

2467: 1690: 1686: 1077: 903: 657: 423: 418: 293: 158: 84: 31: 7969: 2598:

the sense amplifiers also act as latches. For reference, a row of a 1

2412:

to return the chip to the idle state. (This time is usually equal to t

2270:

Additional extended mode registers (selected by the bank address bits)

1524: 8250: 8073: 7973: 7838: 7807: 5148: 5020: 4021: 3747: 3541: 3385: 3216: 3028: 3003: 2949: 2715: 2639: 2587: 2463: 2424:

before the row is fully open and can accept read and write commands.

1682: 1637: 1464: 1429: 1266: 1195: 1093: 964: 955: 652: 595: 363: 283: 7919:"Samsung fires up its foundries for mass production of GDDR6 memory" 6019: 3166:

technology and draws 40% less power than an equivalent DDR3 module.

8245: 8050: 8045: 7130: 5888: 5639: 3624: 3472: 1716: 1652: 1393: 1336: 1271: 1226: 1211: 981: 950: 923: 898: 756: 642: 368: 278: 173: 168: 5896:

High-Performance DRAM System Design Constraints and Considerations

3377:

CMD1=1 to close the row after this access; CMD1=0 to leave it open

8278: 8142: 7895: 7870: 7743: 7685: 7650: 7493: 7468: 7411: 7348: 7274: 7166: 7098: 6907: 6828: 6701: 6136:

Micron, General DDR SDRAM Functionality, Technical Note, TN-46-05

5154: 4208: 3742: 3587: 3495: 3155: 3151: 3011: 2973: 2900: 2666:'s prefetch buffer size is 8n; there is an additional mode of 16n 2660:'s prefetch buffer size is 8n (eight datawords per memory access) 2654:'s prefetch buffer size is 8n (eight datawords per memory access) 2599: 1644: 1629: 1291: 1281: 1276: 1236: 1138: 1133: 1113: 918: 893: 883: 674: 7941:"Samsung Begins Producing The Fastest GDDR6 Memory In The World" 2648:'s prefetch buffer size is 4n (four datawords per memory access) 1700:

varieties, for systems that require greater scalability such as

8232: 8117: 7803:"Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips" 7054: 5829: 5701: 5159: 5118: 5033: 4908: 4678: 4283: 4213: 3980: 3720: 3577: 3573: 3565: 3521: 3518:

model released in December 1995, using the NEC μPD481850 chip.

3159: 2911: 2642:'s prefetch buffer size is 2n (two datawords per memory access) 2635:

Each generation of SDRAM has a different prefetch buffer size:

2200:

Precharge all: deactivate (close) the current row of all banks

2174:

Precharge: deactivate (close) the current row of selected bank

1558:(ICs) produced from the early 1970s to the early 1990s used an 1286: 1246: 1128: 1017: 815: 358: 7305:. 4 November 2003. Archived from the original on July 10, 2019 6819:"Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs" 2021:

Burst terminate: stop a burst read or burst write in progress

1600: 8240: 8185: 8180: 8147: 8132: 8112: 8100: 7995:

PC SDRAM Serial Presence Detect (SPD) Specification, Rev 1.2B

6504: 6388: 5872: 5868: 5864: 5860: 5856: 5852: 5815: 5549: 5509: 5463: 5405: 5334: 5144: 4546: 4359: 4199: 3789: 3569: 3561: 3557: 3553: 3549: 3412: 3371:

CMD3=1 to transfer an 8-word burst; CMD3=0 for a 4-word burst

3197: 3143:

double the internal prefetch width again, but uses the same 8

2919: 2491: 1674: 1567: 1221: 1158: 1153: 1148: 810: 767: 761: 647: 627: 612: 6411:"Samsung hints to DDR4 with first validated 40 nm DRAM" 3666:. The reason given is: Advances in DDR5 need to be included. 30:"PC100" redirects here. For the Japanese home computer, see 8273: 8268: 8137: 8127: 7197: 7126:"Samsung Demonstrates World's First DDR 3 Memory Prototype" 5996: 5848: 5740: 5256: 5164: 4864: 4384: 4204: 3764: 3503: 3220: 3210:

name to Advanced Memory International, Inc.) SLDRAM was an

3129: 3007: 2969: 2896: 2850: 2629: 2602: 2325:

the dynamic (capacitive) memory storage cells of that row.

1656: 1609: 1216: 503: 153: 6385:"JEDEC Announces Key Attributes of Upcoming DDR4 Standard" 5942: 3090:

Again, with every doubling, the downside is the increased

2148:

Active (activate): open a row for read and write commands

1711:

Today, the world's largest manufacturers of SDRAM include

7591: 6788: 6732: 5190: 5101: 3827: 3703: 3499: 3408: 3407:

VCM was a proprietary type of SDRAM that was designed by

2606: 2099:

Write: write a burst of data to the currently active row

2047:

Read: read a burst of data from the currently active row

1659:

in modern computers, because of its greater performance.

1621: 1256: 1143: 913: 6483:"Samsung develops DDR4 memory, up to 40% more efficient" 6335:"Next-Generation DDR4 Memory to Reach 4.266GHz - Report" 2861:

never required for a read and a write at the same time.

1570:, the clock signal controls the stepping of an internal 8029: 6631: 6501:"JEDEC DDR5 & NVDIMM-P Standards Under Development" 6317:"heise online - IT-News, Nachrichten und Hintergründe" 2934:. It was superseded by the PC100 and PC133 standards. 2267:

Wider mode registers (DDR2 and up use 13 bits, A0–A12)

1836:

a strobe, but rather simply a command bit. Along with

7433:"Samsung 50nm 2GB DDR3 chips are industry's smallest" 7339:"Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM" 5891:- Flash website built by Tel-Aviv University students 3402: 1790:, which are sampled on the rising edge of the clock: 1742: 622: 2983:

with PC66 and was superseded by the PC133 standard.

2521:

clock frequency to translate that limit into cycles.

6662:

128M-BIT VirtualChannel SDRAM preliminary datasheet

6565: 6031: 6029: 3454: 3392:, which always write in multiples of a cache line. 7151: 7149: 6299:"IDF: "DDR3 won't catch up with DDR2 during 2009"" 6256:"G.SKILL Announces DDR3 Memory Kit For Ivy Bridge" 6146: 6144: 6142: 5898:, a master thesis from the University of Maryland. 3380:CMD0 selects the DCLK pair to use (DCLK1 or DCLK0) 2581: 1755: 1677:, an electronics industry association that adopts 6208:"Pipe Dreams: Six P35-DDR3 Motherboards Compared" 6205: 3691:Synchronous dynamic random-access memory (SDRAM) 3204: 2517:M8, M7: Operating mode. Reserved, and must be 00. 2261:Additional address bits to support larger devices 8327: 7391:ATI engineers by way of Beyond 3D's Dave Baumann 6253: 6026: 3498:HM5283206, introduced in November 1994, and the 2590:located on a common physical row in the memory. 1832:, row address strobe. Despite the name, this is 7146: 6377: 6362:(in German). hardware-infos.com. Archived from 6337:. Xbitlabs.com. August 16, 2010. Archived from 6153:"The outlook for DRAMs in consumer electronics" 6139: 1902:The SDR SDRAM commands are defined as follows: 7990:133 MHz PC133 SDRAM SO-DIMM Specification 7670: 7668: 7615:"16M-BIT SYNCHRONOUS GRAPHICS RAM: μPD4811650" 6511: 3611:(HBM) is a high-performance RAM interface for 3597: 2960:is a standard for internal removable computer 2774:Internal operations are at 1/2 the clock rate. 2290:is high, other commands are the same as above. 8015: 7827: 7825: 7234: 7232: 7230: 7228: 7226: 7224: 7222: 6873: 6871: 6869: 6867: 6865: 6241:"Super Talent & TEAM: DDR3-1600 Is Here!" 5803: 5725: 5689: 5447: 5413: 5240: 5176: 5133: 4695: 4006: 3966: 3350:5 or 4 bits spare for row or column expansion 2998:is a computer memory standard defined by the 2328:Once the row has been activated or "opened", 2294: 1505: 7394: 7083: 7081: 7079: 6927: 6925: 6813: 6811: 6809: 6690: 6688: 6608:(data sheet), pp. 32–33, archived from 3522:Graphics double data rate SDRAM (GDDR SDRAM) 3234:SLDRAM Read, write or row op request packet 2430: 7665: 7331: 7185: 7183: 7017: 7015: 6598: 5969: 3330: 3310: 3302: 3299: 3293: 3279: 2815:point-to-point (single module per channel) 8022: 8008: 7822: 7516:"Samsung Unleashes a Roomy DDR4 256GB RAM" 7219: 6896: 6862: 6777: 6775: 6721: 6719: 6238: 6049:(15–21). Hayden Publishing Company. 1993. 5970:Jacob, B.; Ng, S. W.; Wang, D. T. (2008). 5885:- EEPROM with timing data on SDRAM modules 3544:designed to be used as the main memory of 3361:A read/write command had the msbit clear: 2914:-based PCs. It also features in the Beige 1512: 1498: 7076: 6922: 6806: 6685: 6635:HYB39V64x0yT 64MBit Virtual Channel SDRAM 6569:HYSL8M18D600A 600 Mb/s/pin 8M x 18 SLDRAM 6542: 5915: 5083:Synchronous graphics random-access memory 3223:. (1 MT/s = 1000^2 transfers per second) 2466:will generally access memory in units of 7910: 7612: 7180: 7012: 6602:SLD4M18DR400 400 Mb/s/pin 4M x 18 SLDRAM 6075: 6073: 6071: 6069: 6067: 6065: 6063: 6061: 6059: 3487:nature of other video RAM technologies. 2948: 2825: 2298: 1599: 1533:Synchronous dynamic random-access memory 1523: 7916: 7363: 7120: 7118: 7116: 6989: 6987: 6985: 6772: 6716: 6408: 6110:"Nanya 256 Mb DDR SDRAM Datasheet" 5943:B. Jacob; S. W. Ng; D. T. Wang (2008). 2853:that read or write 64 (non-ECC) or 72 ( 2402: 1880: 14: 8328: 7831: 7800: 7402:"Our Proud Heritage from 2000 to 2009" 6999:STOL (Semiconductor Technology Online) 6437:"DDR3 Will be Cheaper, Faster in 2009" 6434: 6409:Gruener, Wolfgang (February 4, 2009). 6150: 3192: 2887:refers to internal removable computer 2830:The 64 MB of sound memory on the 2282:of the activate command. A new signal 1889: 8003: 7459:"Our Proud Heritage from 2010 to Now" 6517: 6056: 5122: 5112: 3724: 3714: 3490:The earliest known SGRAM memory are 8 3374:CMD2=1 for a write, CMD2=0 for a read 1860:, this selects one of eight commands. 1844:, this selects one of eight commands. 1053:Vision Electronic Recording Apparatus 7371:"ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資" 7113: 6982: 6360:"IDF: DDR4 memory targeted for 2012" 6000:IEEE Journal of Solid-State Circuits 5126: 3728: 3648: 3637:Random-access memory § Timeline 3494:Mbit chips dating back to 1994: the 3420:. In the late 1990s, a number of PC 3184: 2942:For the Japanese home computer, see 2451:time, three cycles may be required. 7619:NEC Device Technology International 7548:"Hitachi HM5283206FP10 8Mbit SGRAM" 6859:page 118 "High-Bandwidth DRAM" 6658: 24: 7524:. 6 September 2018. Archived from 6566:Hyundai Electronics (1997-12-20), 6254:Jennifer Johnson (24 April 2012). 6226:"AMD to Adopt DDR3 in Three Years" 6206:Thomas Soderstrom (June 5, 2007). 3403:Virtual channel memory (VCM) SDRAM 2549: 1821: 1781: 214:Data validation and reconciliation 25: 8352: 7963: 5973:Memory Systems: Cache, DRAM, Disk 5946:Memory Systems: Cache, DRAM, Disk 3327: 3324: 3321: 3313: 2457: 2222: 2219: 2216: 2196: 2190: 2170: 2017: 2014: 2011: 1991: 1988: 1985: 1965: 1962: 1959: 1956: 1953: 1950: 1624:invented DDR SDRAM, they built a 264:Distributed file system for cloud 7917:Killian, Zak (18 January 2018). 7801:Shilov, Anton (March 29, 2016). 7381:from the original on 2016-08-13. 5976:. Morgan Kaufmann. p. 333. 5949:. Morgan Kaufmann. p. 324. 5851:(graphics DDR) and its subtypes 5076: 3653: 3455:Synchronous Graphics RAM (SGRAM) 2926:. It is also used in many early 2501: 112:Areal density (computer storage) 7985:PC SDRAM Specification, Rev 1.7 7933: 7884: 7853: 7832:Shilov, Anton (July 19, 2017). 7794: 7782:from the original on 2022-01-24 7758: 7726: 7700: 7633: 7606: 7578: 7566:from the original on 2003-07-16 7540: 7508: 7482: 7451: 7425: 7385: 7297:"Elpida ships 2GB DDR2 modules" 7289: 7257: 7207:from the original on 2017-02-27 7064:from the original on 2019-06-21 7040: 6961: 6949:from the original on 2019-06-21 6843: 6784:NEC Application Specific Memory 6747: 6675:from the original on 2013-12-03 6652: 6648:from the original on 2018-11-12 6625: 6592: 6559: 6536: 6493: 6475: 6454: 6439:. dailytech.com. Archived from 6435:Jansen, Ng (January 20, 2009). 6428: 6402: 6352: 6327: 6309: 6291: 6273: 6262: 6247: 6232: 6218: 6199: 6185: 6170: 3296: 3285: 3282: 3276: 3128:The DDR4 chips run at 1.2 3116:DDR4 SDRAM is the successor to 2832:Sound Blaster X-Fi Fatality Pro 2582:DDR SDRAM prefetch architecture 2536: 2462:A modern microprocessor with a 2239: 2236: 2233: 2230: 2213: 2210: 2207: 2204: 2193: 2187: 2184: 2181: 2178: 2167: 2161: 2158: 2155: 2152: 2138: 2135: 2132: 2129: 2118: 2112: 2109: 2106: 2103: 2092: 2086: 2083: 2080: 2077: 2066: 2060: 2057: 2054: 2051: 2040: 2034: 2031: 2028: 2025: 2008: 2005: 2002: 1999: 1982: 1979: 1976: 1973: 1969:Command inhibit (no operation) 1947: 931:Programmable metallization cell 6281:"DDR4 not expected until 2015" 6130: 6102: 5990: 5963: 5936: 5909: 3645:Transistor count § Memory 3424:chipsets (such as the popular 3205:Synchronous-link DRAM (SLDRAM) 2953:DIMM: 168 pins and two notches 2670: 494:Persistence (computer science) 13: 1: 8304: 6632:Siemens Semiconductor Group, 6413:. tgdaily.com. Archived from 5902: 3514:, starting with the Japanese 1362:Electronic quantum holography 8031:Dynamic random-access memory 7981:, May 2011, Hardware Secrets 6978:. February 1996. p. 40. 6575:(data sheet), archived from 6239:Wesly Fink (July 20, 2007). 6151:Graham, Allan (2007-01-12). 3641:Flash memory § Timeline 3471:. It adds functions such as 3428:) included VCSDRAM support. 3347:10 or 11 bits of row address 3042:DDR SDRAM (sometimes called 713:Video RAM (dual-ported DRAM) 509:Non-RAID drive architectures 7: 7766:"K4W1G1646G-BC08 Datasheet" 5842: 3630: 3598:High Bandwidth Memory (HBM) 3540:) is a type of specialized 2930:systems with a 66 MHz 2845:Originally simply known as 2303:SDRAM memory module, zoomed 2264:Additional bank select bits 1897: 1868:, write enable. Along with 1696:SDRAM is also available in 10: 8357: 6599:SLDRAM Inc. (1998-07-09), 6518:Smith, Ryan (2020-07-14). 3634: 3601: 3525: 3451:(256 bytes) in a segment. 3173: 3109: 3079: 3057: 3026: 2941: 2906:This standard was used by 2798:Much longer CAS latencies 2295:Construction and operation 2248: 2225: 2199: 2173: 2147: 2124: 2098: 2072: 2046: 2020: 1994: 1968: 1595: 1302:Holographic Versatile Disc 1201:Compact Disc Digital Audio 1073:Magnetic-tape data storage 692:Content-addressable memory 29: 8292: 8259: 8231: 8163: 8059: 8038: 7979:Understanding RAM Timings 7323:: CS1 maint: unfit URL ( 5878:List of device bandwidths 5660: 5653: 5650: 5643: 5638: 5530: 5523: 5520: 5399: 5392: 5389: 5382: 5379: 5373: 5366: 5363: 5009: 5006: 4827: 4824: 4804: 4797: 4794: 4769: 4766: 4728: 4656: 4649: 4646: 4528: 4411: 4408: 4373: 4341: 4230: 4227: 4122: 4119: 4052: 4049: 3779: 3662:This section needs to be 3546:graphics processing units 3120:. It was revealed at the 2802: 2784: 2765:"Burst terminate" removed 2757: 2714: 2688: 2683: 2680: 2494:for its microprocessors. 2431:Interrupting a read burst 2280:DDR4 changes the encoding 2245: 2144: 1730: 1647:) followed soon after by 499:Persistent data structure 394:Digital rights management 6904:"KM48SL2000-7 Datasheet" 6543:Dean Kent (1998-10-24), 6099:based on powers of 1024. 3685: 3353:7 bits of column address 2990: 2937: 2891:standard defined by the 2767:4 units used in parallel 2621:in multiple data words. 1374:DNA digital data storage 1357:Holographic data storage 846:Solid-state hybrid drive 132:Network-attached storage 8341:South Korean inventions 7556:Smithsonian Institution 6968:"Ultra 64 Tech Specs". 3169: 3105: 3075: 3053: 2879: 1812:data mask. (The letter 1537:synchronous dynamic RAM 1369:5D optical data storage 1186:3D optical data storage 909:Universal Flash Storage 314:Replication (computing) 259:Distributed file system 149:Single-instance storage 127:Direct-attached storage 107:Continuous availability 27:Type of computer memory 7708:"K4D553238F Datasheet" 7613:Takeuchi, Kei (1998). 7375:pc.watch.impress.co.jp 6933:"MSM5718C50/MD5764802" 5883:Serial presence detect 3344:3 bits of bank address 3022: 2954: 2870:extended data out DRAM 2842: 2821: 2304: 1757: 1756:{\displaystyle 10^{6}} 1613: 1529: 1242:Nintendo optical discs 459:Storage virtualization 329:Information repository 269:Distributed data store 7866:Samsung Semiconductor 7739:Samsung Semiconductor 7646:Samsung Semiconductor 7464:Samsung Semiconductor 7407:Samsung Semiconductor 7344:Samsung Semiconductor 7270:Samsung Semiconductor 6791:. Fall 1995. p. 6464:. Samsung. 2011-01-04 6193:"What is DDR memory?" 5094:Date of introduction 5087:High Bandwidth Memory 3696:Date of introduction 3609:High Bandwidth Memory 3604:High Bandwidth Memory 3122:Intel Developer Forum 3019:with PC100 and PC66. 2952: 2829: 2302: 1766:Another limit is the 1758: 1608:SDRAM ICs on a PC100 1603: 1527: 745:Mellon optical memory 733:Williams–Kilburn tube 449:Locality of reference 254:Clustered file system 80:Memory access pattern 45:computer data storage 7587:UPD4811650 Datasheet 6341:on December 19, 2010 6178:"SDRAM Part Catalog" 3162:at 1.2 V, uses 2962:random-access memory 2403:Command interactions 1881:Bank selection (BAn) 1740: 1572:finite-state machine 1441:Magnetic-core memory 1088:Digital Data Storage 1048:Quadruplex videotape 489:In-memory processing 379:Information transfer 274:Distributed database 137:Storage area network 117:Block (data storage) 7773:Samsung Electronics 7712:Samsung Electronics 7681:Samsung Electronics 7439:. 29 September 2008 7351:. 20 September 2004 7162:Samsung Electronics 7094:Samsung Electronics 6831:. 17 September 1998 6824:Samsung Electronics 6728:μPD481850 Datasheet 6697:HM5283206 Datasheet 6228:. 28 November 2005. 6037:"Electronic Design" 6012:1990IJSSC..25.1118K 5090: 3692: 3592:Samsung Electronics 3426:VIA KX133 and KT133 3338:9 bits of device ID 3235: 3193:Rambus DRAM (RDRAM) 3017:backward compatible 2981:backward compatible 2874:fast page mode DRAM 2677: 2481:For the sequential 1890:Addressing (A10/An) 1713:Samsung Electronics 1649:Hyundai Electronics 1556:integrated circuits 1528:SDRAM memory module 1038:Phonograph cylinder 976:Electrochemical RAM 828:Solid-state storage 444:Memory segmentation 142:Block-level storage 8155:Hybrid Memory Cube 7898:. January 18, 2018 7746:. October 26, 2005 7200:. April 21, 2003. 7134:. 17 February 2005 7101:. 10 February 1999 6855:2015-02-06 at the 6704:. 11 November 1994 5916:P. Darche (2020). 5081: 3690: 3512:video game console 3233: 3150:In February 2009, 3002:. PC133 refers to 2955: 2857:) bits at a time. 2843: 2837:is built from two 2790:Access is ≥8 words 2763:Access is ≥4 words 2723:Access is ≥2 words 2676:SDRAM feature map 2675: 2305: 1753: 1626:dual-edge clocking 1620:In the late 1980s 1614: 1530: 1447:Plated-wire memory 1412:Paper data storage 1058:Magnetic recording 484:In-memory database 469:Memory-mapped file 414:Volume boot record 409:Master boot record 399:Volume (computing) 374:Data communication 299:Data deduplication 8323: 8322: 7947:. 18 January 2018 7775:. November 2010. 7277:. 29 January 2003 7057:. 12 March 1998. 6942:. February 1999. 6940:Oki Semiconductor 6850:ISSCC 2014 Trends 6735:. 6 December 1994 6546:RAM Guide: SLDRAM 6503:(Press release). 6387:(Press release). 6287:. 16 August 2010. 6182:070928 micron.com 6159:. AspenCore Media 6042:Electronic Design 5840: 5839: 5074: 5073: 3683: 3682: 3418:memory controller 3341:6 bits of command 3335: 3334: 3185:Failed successors 3164:pseudo open drain 2964:, defined by the 2819: 2818: 2394:delay between an 2255: 2254: 1721:Micron Technology 1522: 1521: 1119:8 mm video format 1043:Phonograph record 862:Flash Core Module 840:Solid-state drive 739:Delay-line memory 698:Computational RAM 601:Scratchpad memory 439:Disk partitioning 164:Unstructured data 90:Secondary storage 16:(Redirected from 8348: 8315:Transistor count 8024: 8017: 8010: 8001: 8000: 7957: 7956: 7954: 7952: 7937: 7931: 7930: 7928: 7926: 7914: 7908: 7907: 7905: 7903: 7888: 7882: 7881: 7879: 7877: 7857: 7851: 7850: 7848: 7846: 7829: 7820: 7819: 7817: 7815: 7798: 7792: 7791: 7789: 7787: 7781: 7770: 7762: 7756: 7755: 7753: 7751: 7730: 7724: 7723: 7721: 7719: 7704: 7698: 7697: 7695: 7693: 7688:. 28 August 2003 7672: 7663: 7662: 7660: 7658: 7637: 7631: 7630: 7628: 7626: 7610: 7604: 7603: 7601: 7599: 7582: 7576: 7575: 7573: 7571: 7565: 7552: 7544: 7538: 7537: 7535: 7533: 7528:on June 21, 2019 7512: 7506: 7505: 7503: 7501: 7486: 7480: 7479: 7477: 7475: 7455: 7449: 7448: 7446: 7444: 7429: 7423: 7422: 7420: 7418: 7398: 7392: 7389: 7383: 7382: 7367: 7361: 7360: 7358: 7356: 7335: 7329: 7328: 7322: 7314: 7312: 7310: 7293: 7287: 7286: 7284: 7282: 7261: 7255: 7254: 7252: 7250: 7240:"History: 2000s" 7236: 7217: 7216: 7214: 7212: 7206: 7195: 7187: 7178: 7177: 7175: 7173: 7153: 7144: 7143: 7141: 7139: 7122: 7111: 7110: 7108: 7106: 7085: 7074: 7073: 7071: 7069: 7063: 7052: 7044: 7038: 7037: 7035: 7033: 7023:"History: 1990s" 7019: 7010: 7009: 7007: 7005: 6991: 6980: 6979: 6965: 6959: 6958: 6956: 6954: 6948: 6937: 6929: 6920: 6919: 6917: 6915: 6900: 6894: 6893: 6891: 6889: 6879:"History: 2010s" 6875: 6860: 6847: 6841: 6840: 6838: 6836: 6815: 6804: 6803: 6801: 6799: 6779: 6770: 6769: 6767: 6765: 6751: 6745: 6744: 6742: 6740: 6723: 6714: 6713: 6711: 6709: 6692: 6683: 6682: 6681: 6680: 6674: 6667: 6656: 6650: 6649: 6647: 6640: 6629: 6623: 6622: 6621: 6620: 6614: 6607: 6596: 6590: 6589: 6588: 6587: 6581: 6574: 6563: 6557: 6556: 6555: 6554: 6549:, Tom's Hardware 6540: 6534: 6533: 6531: 6530: 6515: 6509: 6508: 6507:. 30 March 2017. 6497: 6491: 6490: 6479: 6473: 6472: 6470: 6469: 6458: 6452: 6451: 6449: 6448: 6443:on June 22, 2009 6432: 6426: 6425: 6423: 6422: 6406: 6400: 6399: 6397: 6396: 6381: 6375: 6374: 6372: 6371: 6356: 6350: 6349: 6347: 6346: 6331: 6325: 6324: 6313: 6307: 6306: 6295: 6289: 6288: 6285:semiaccurate.com 6277: 6271: 6269:DDR4 PDF page 23 6266: 6260: 6259: 6251: 6245: 6244: 6236: 6230: 6229: 6222: 6216: 6215: 6203: 6197: 6196: 6189: 6183: 6181: 6174: 6168: 6167: 6165: 6164: 6148: 6137: 6134: 6128: 6127: 6125: 6124: 6114: 6106: 6100: 6077: 6054: 6053: 6033: 6024: 6023: 5994: 5988: 5987: 5967: 5961: 5960: 5940: 5934: 5933: 5913: 5805: 5727: 5691: 5449: 5415: 5242: 5178: 5135: 5128: 5110:Manufacturer(s) 5091: 5080: 4697: 4008: 3968: 3730: 3712:Manufacturer(s) 3693: 3689: 3678: 3675: 3669: 3657: 3656: 3649: 3586: 3534:double data rate 3493: 3236: 3232: 3036:double data rate 2814: 2771: 2742: 2737: 2701: 2684:Feature changes 2678: 2674: 2605:device is 2,048 2507:register write. 2289: 2285: 1925: 1920: 1915: 1910: 1905: 1904: 1875: 1871: 1866: 1859: 1855: 1850: 1843: 1839: 1830: 1804: 1762: 1760: 1759: 1754: 1752: 1751: 1725:Nanya Technology 1643: 1636:SDRAM, known as 1634:double data rate 1514: 1507: 1500: 1459:Thin-film memory 1453:Core rope memory 1379:Universal memory 1342:Millipede memory 1332:Racetrack memory 1297:Ultra HD Blu-ray 1109:Linear Tape-Open 1063:Magnetic storage 1031:Analog recording 474:Software entropy 434:Disk aggregation 194:Data degradation 179:Data compression 75:Memory hierarchy 65:Memory coherence 37: 36: 21: 8356: 8355: 8351: 8350: 8349: 8347: 8346: 8345: 8326: 8325: 8324: 8319: 8288: 8255: 8227: 8159: 8107:Fast Cycle DRAM 8055: 8034: 8028: 7972:, August 2010, 7966: 7961: 7960: 7950: 7948: 7939: 7938: 7934: 7924: 7922: 7915: 7911: 7901: 7899: 7890: 7889: 7885: 7875: 7873: 7859: 7858: 7854: 7844: 7842: 7830: 7823: 7813: 7811: 7799: 7795: 7785: 7783: 7779: 7768: 7764: 7763: 7759: 7749: 7747: 7732: 7731: 7727: 7717: 7715: 7706: 7705: 7701: 7691: 7689: 7674: 7673: 7666: 7656: 7654: 7639: 7638: 7634: 7624: 7622: 7611: 7607: 7597: 7595: 7594:. December 1997 7584: 7583: 7579: 7569: 7567: 7563: 7550: 7546: 7545: 7541: 7531: 7529: 7514: 7513: 7509: 7499: 7497: 7496:. July 17, 2018 7488: 7487: 7483: 7473: 7471: 7457: 7456: 7452: 7442: 7440: 7431: 7430: 7426: 7416: 7414: 7400: 7399: 7395: 7390: 7386: 7369: 7368: 7364: 7354: 7352: 7337: 7336: 7332: 7316: 7315: 7308: 7306: 7295: 7294: 7290: 7280: 7278: 7263: 7262: 7258: 7248: 7246: 7238: 7237: 7220: 7210: 7208: 7204: 7193: 7189: 7188: 7181: 7171: 7169: 7155: 7154: 7147: 7137: 7135: 7124: 7123: 7114: 7104: 7102: 7087: 7086: 7077: 7067: 7065: 7061: 7050: 7046: 7045: 7041: 7031: 7029: 7021: 7020: 7013: 7003: 7001: 6993: 6992: 6983: 6974:. No. 14. 6971:Next Generation 6967: 6966: 6962: 6952: 6950: 6946: 6935: 6931: 6930: 6923: 6913: 6911: 6902: 6901: 6897: 6887: 6885: 6877: 6876: 6863: 6857:Wayback Machine 6848: 6844: 6834: 6832: 6817: 6816: 6807: 6797: 6795: 6781: 6780: 6773: 6763: 6761: 6753: 6752: 6748: 6738: 6736: 6725: 6724: 6717: 6707: 6705: 6694: 6693: 6686: 6678: 6676: 6672: 6665: 6657: 6653: 6645: 6638: 6630: 6626: 6618: 6616: 6612: 6605: 6597: 6593: 6585: 6583: 6579: 6572: 6564: 6560: 6552: 6550: 6541: 6537: 6528: 6526: 6516: 6512: 6499: 6498: 6494: 6481: 6480: 6476: 6467: 6465: 6460: 6459: 6455: 6446: 6444: 6433: 6429: 6420: 6418: 6417:on May 24, 2009 6407: 6403: 6394: 6392: 6383: 6382: 6378: 6369: 6367: 6358: 6357: 6353: 6344: 6342: 6333: 6332: 6328: 6315: 6314: 6310: 6297: 6296: 6292: 6279: 6278: 6274: 6267: 6263: 6252: 6248: 6237: 6233: 6224: 6223: 6219: 6204: 6200: 6191: 6190: 6186: 6176: 6175: 6171: 6162: 6160: 6149: 6140: 6135: 6131: 6122: 6120: 6112: 6108: 6107: 6103: 6097:binary prefixes 6078: 6057: 6035: 6034: 6027: 6020:10.1109/4.62132 5995: 5991: 5984: 5968: 5964: 5957: 5941: 5937: 5930: 5914: 5910: 5905: 5845: 5079: 3688: 3679: 3673: 3670: 3667: 3658: 3654: 3647: 3633: 3606: 3600: 3590:memory chip by 3584: 3530: 3524: 3491: 3457: 3405: 3311:Row (continued) 3207: 3195: 3187: 3178: 3172: 3114: 3108: 3084: 3078: 3062: 3056: 3031: 3025: 2993: 2947: 2940: 2882: 2824: 2812: 2808: 2797: 2791: 2775: 2773: 2769: 2768: 2766: 2764: 2753: 2740: 2735: 2731: 2710: 2699: 2695: 2673: 2584: 2565: 2552: 2550:Low power modes 2545: 2539: 2504: 2460: 2433: 2423: 2419: 2415: 2411: 2405: 2393: 2386: 2344:command, and a 2339: 2297: 2287: 2283: 2250: 1923: 1918: 1913: 1908: 1900: 1892: 1883: 1873: 1869: 1864: 1857: 1853: 1848: 1841: 1837: 1828: 1824: 1822:Command signals 1802: 1784: 1782:Control signals 1747: 1743: 1741: 1738: 1737: 1733: 1641: 1598: 1518: 1489: 1488: 1407: 1399: 1398: 1352:Patterned media 1322: 1314: 1313: 1181: 1171: 1170: 1166:Hard disk drive 1033: 1023: 1022: 1003: 992: 991: 946: 936: 935: 857:IBM FlashSystem 852:USB flash drive 791: 774: 773: 728: 720: 719: 708:Dual-ported RAM 586: 569: 568: 529:Cloud computing 389:Copy protection 309:Data redundancy 239:Shared resource 209:Data validation 184:Data corruption 159:Structured data 70:Cache coherence 55: 41:Computer memory 35: 28: 23: 22: 15: 12: 11: 5: 8354: 8344: 8343: 8338: 8321: 8320: 8318: 8317: 8312: 8307: 8305:SDRAM timeline 8302: 8296: 8294: 8290: 8289: 8287: 8286: 8281: 8276: 8271: 8265: 8263: 8261:Memory modules 8257: 8256: 8254: 8253: 8248: 8243: 8237: 8235: 8229: 8228: 8226: 8225: 8224: 8223: 8218: 8213: 8208: 8203: 8198: 8193: 8183: 8178: 8173: 8167: 8165: 8161: 8160: 8158: 8157: 8152: 8151: 8150: 8145: 8140: 8135: 8130: 8120: 8115: 8110: 8104: 8098: 8097: 8096: 8091: 8086: 8081: 8071: 8065: 8063: 8057: 8056: 8054: 8053: 8048: 8042: 8040: 8036: 8035: 8027: 8026: 8019: 8012: 8004: 7998: 7997: 7992: 7987: 7982: 7976: 7965: 7964:External links 7962: 7959: 7958: 7932: 7909: 7883: 7852: 7821: 7793: 7757: 7725: 7699: 7664: 7653:. 12 July 1999 7632: 7605: 7577: 7539: 7521:Tom's Hardware 7507: 7481: 7450: 7424: 7393: 7384: 7362: 7330: 7288: 7256: 7218: 7179: 7145: 7112: 7075: 7048:"Direct RDRAM" 7039: 7011: 6981: 6960: 6921: 6895: 6861: 6842: 6805: 6771: 6746: 6715: 6684: 6651: 6624: 6591: 6558: 6535: 6510: 6492: 6474: 6453: 6427: 6401: 6376: 6351: 6326: 6308: 6290: 6272: 6261: 6246: 6231: 6217: 6212:Tom's Hardware 6198: 6184: 6169: 6138: 6129: 6101: 6055: 6025: 5989: 5982: 5962: 5955: 5935: 5928: 5922:. p. 59. 5907: 5906: 5904: 5901: 5900: 5899: 5892: 5889:SDRAM Tutorial 5886: 5880: 5875: 5844: 5841: 5838: 5837: 5835: 5832: 5827: 5822: 5819: 5812: 5809: 5806: 5800: 5799: 5797: 5790: 5787: 5784: 5781: 5778: 5775: 5768: 5764: 5763: 5761: 5754: 5751: 5746: 5743: 5738: 5735: 5728: 5722: 5721: 5719: 5716: 5713: 5710: 5705: 5698: 5695: 5694:MT58K256M32JA 5692: 5686: 5685: 5680: 5673: 5666: 5662: 5661: 5659: 5652: 5649: 5642: 5637: 5636:SGRAM (GDDR3) 5634: 5631: 5624: 5620: 5619: 5617: 5614: 5611: 5604: 5601: 5600:SGRAM (GDDR3) 5598: 5595: 5592: 5588: 5587: 5582: 5579: 5578:SGRAM (GDDR5) 5576: 5573: 5566: 5562: 5561: 5556: 5553: 5546: 5543: 5536: 5532: 5531: 5529: 5522: 5519: 5512: 5507: 5506:SGRAM (GDDR4) 5504: 5501: 5494: 5490: 5489: 5487: 5480: 5477: 5470: 5467: 5460: 5457: 5450: 5444: 5443: 5441: 5438: 5435: 5428: 5425: 5422: 5419: 5416: 5410: 5409: 5401: 5400: 5398: 5391: 5388: 5381: 5378: 5377:SGRAM (GDDR2) 5375: 5372: 5365: 5361: 5360: 5358: 5351: 5348: 5341: 5338: 5331: 5328: 5321: 5317: 5316: 5314: 5311: 5308: 5301: 5298: 5295: 5292: 5289: 5285: 5284: 5282: 5275: 5272: 5265: 5260: 5253: 5250: 5243: 5241:September 1998 5237: 5236: 5234: 5231: 5228: 5225: 5222: 5219: 5216: 5213: 5209: 5208: 5206: 5203: 5200: 5193: 5188: 5185: 5182: 5179: 5173: 5172: 5170: 5167: 5162: 5157: 5152: 5142: 5139: 5136: 5130: 5129: 5124: 5121: 5116: 5111: 5108: 5105: 5098: 5095: 5078: 5075: 5072: 5071: 5069: 5062: 5059: 5056: 5053: 5050: 5046: 5045: 5043: 5036: 5031: 5026: 5023: 5018: 5015: 5008: 5004: 5003: 5001: 4994: 4991: 4988: 4985: 4982: 4979: 4972: 4968: 4967: 4965: 4958: 4955: 4952: 4949: 4946: 4943: 4936: 4932: 4931: 4929: 4922: 4919: 4914: 4911: 4906: 4899: 4892: 4888: 4887: 4885: 4878: 4875: 4870: 4867: 4862: 4858: 4857: 4855: 4848: 4845: 4842: 4839: 4836: 4833: 4826: 4822: 4821: 4816: 4813: 4810: 4806: 4805: 4803: 4796: 4793: 4788: 4785: 4782: 4775: 4768: 4764: 4763: 4756: 4753: 4750: 4747: 4744: 4741: 4734: 4730: 4729: 4727: 4720: 4717: 4714: 4711: 4708: 4705: 4698: 4692: 4691: 4684: 4681: 4676: 4669: 4662: 4658: 4657: 4655: 4648: 4645: 4642: 4639: 4636: 4633: 4626: 4622: 4621: 4619: 4612: 4609: 4606: 4603: 4600: 4597: 4589: 4588: 4586: 4579: 4576: 4573: 4570: 4567: 4564: 4558: 4557: 4555: 4552: 4549: 4544: 4543:Sony, Toshiba 4541: 4538: 4535: 4530: 4526: 4525: 4523: 4516: 4513: 4510: 4507: 4504: 4501: 4494: 4490: 4489: 4487: 4480: 4477: 4470: 4467: 4464: 4460: 4459: 4457: 4450: 4447: 4442: 4436: 4435: 4433: 4426: 4423: 4416: 4413: 4410: 4406: 4405: 4403: 4396: 4393: 4390: 4387: 4382: 4379: 4371: 4370: 4368: 4365: 4362: 4357: 4356:Sony, Toshiba 4354: 4351: 4348: 4343: 4339: 4338: 4336: 4329: 4326: 4319: 4316: 4313: 4310: 4303: 4299: 4298: 4296: 4289: 4286: 4281: 4278: 4273: 4265: 4264: 4262: 4255: 4252: 4245: 4242: 4239: 4236: 4229: 4225: 4224: 4222: 4219: 4216: 4211: 4202: 4197: 4194: 4189: 4185: 4184: 4182: 4175: 4172: 4167: 4164: 4161: 4157: 4156: 4154: 4147: 4144: 4137: 4134: 4131: 4128: 4121: 4117: 4116: 4114: 4107: 4104: 4097: 4094: 4091: 4087: 4086: 4084: 4077: 4074: 4067: 4064: 4061: 4058: 4051: 4047: 4046: 4044: 4037: 4034: 4027: 4024: 4019: 4016: 4009: 4003: 4002: 4000: 3993: 3990: 3983: 3978: 3975: 3972: 3969: 3963: 3962: 3960: 3957: 3954: 3947: 3944: 3941: 3938: 3935: 3931: 3930: 3928: 3921: 3916: 3909: 3904: 3901: 3898: 3891: 3887: 3886: 3884: 3877: 3874: 3869: 3864: 3861: 3858: 3850: 3849: 3847: 3840: 3837: 3830: 3825: 3822: 3819: 3813: 3812: 3810: 3807: 3804: 3797: 3792: 3787: 3784: 3781: 3777: 3776: 3774: 3767: 3762: 3755: 3750: 3745: 3739: 3736: 3732: 3731: 3726: 3723: 3718: 3713: 3710: 3707: 3700: 3697: 3687: 3684: 3681: 3680: 3661: 3659: 3652: 3632: 3629: 3602:Main article: 3599: 3596: 3526:Main article: 3523: 3520: 3461:texture memory 3456: 3453: 3404: 3401: 3382: 3381: 3378: 3375: 3372: 3369: 3366: 3355: 3354: 3351: 3348: 3345: 3342: 3339: 3333: 3332: 3329: 3326: 3323: 3320: 3316: 3315: 3312: 3309: 3305: 3304: 3301: 3298: 3295: 3292: 3288: 3287: 3284: 3281: 3278: 3275: 3271: 3270: 3267: 3264: 3261: 3258: 3255: 3252: 3249: 3246: 3243: 3240: 3206: 3203: 3194: 3191: 3186: 3183: 3174:Main article: 3171: 3168: 3134:data transfers 3110:Main article: 3107: 3104: 3080:Main article: 3077: 3074: 3058:Main article: 3055: 3052: 3027:Main article: 3024: 3021: 2992: 2989: 2939: 2936: 2881: 2878: 2872:(EDO-RAM) and 2823: 2820: 2817: 2816: 2810: 2806: 2800: 2799: 2788: 2782: 2781: 2761: 2755: 2754: 2752: 2751: 2744: 2738: 2733: 2729: 2727:Double clocked 2724: 2720: 2718: 2712: 2711: 2709: 2708: 2702: 2697: 2692: 2690: 2686: 2685: 2682: 2672: 2669: 2668: 2667: 2661: 2655: 2649: 2643: 2583: 2580: 2563: 2551: 2548: 2543: 2538: 2535: 2530: 2529: 2525: 2522: 2518: 2515: 2503: 2500: 2459: 2458:Burst ordering 2456: 2432: 2429: 2421: 2417: 2413: 2409: 2404: 2401: 2391: 2384: 2337: 2296: 2293: 2292: 2291: 2277: 2274: 2271: 2268: 2265: 2262: 2253: 2252: 2247: 2244: 2241: 2238: 2235: 2232: 2228: 2227: 2224: 2221: 2218: 2215: 2212: 2209: 2206: 2202: 2201: 2198: 2195: 2192: 2189: 2186: 2183: 2180: 2176: 2175: 2172: 2169: 2166: 2163: 2160: 2157: 2154: 2150: 2149: 2146: 2143: 2140: 2137: 2134: 2131: 2127: 2126: 2123: 2120: 2117: 2114: 2111: 2108: 2105: 2101: 2100: 2097: 2094: 2091: 2088: 2085: 2082: 2079: 2075: 2074: 2071: 2068: 2065: 2062: 2059: 2056: 2053: 2049: 2048: 2045: 2042: 2039: 2036: 2033: 2030: 2027: 2023: 2022: 2019: 2016: 2013: 2010: 2007: 2004: 2001: 1997: 1996: 1993: 1990: 1987: 1984: 1981: 1978: 1975: 1971: 1970: 1967: 1964: 1961: 1958: 1955: 1952: 1949: 1945: 1944: 1941: 1935: 1932: 1926: 1921: 1916: 1911: 1899: 1896: 1891: 1888: 1882: 1879: 1878: 1877: 1861: 1845: 1823: 1820: 1819: 1818: 1807: 1799: 1783: 1780: 1750: 1746: 1732: 1729: 1679:open standards 1664:burst EDO DRAM 1597: 1594: 1520: 1519: 1517: 1516: 1509: 1502: 1494: 1491: 1490: 1487: 1486: 1480: 1474: 1471:Twistor memory 1468: 1462: 1456: 1450: 1444: 1438: 1432: 1427: 1421: 1415: 1408: 1405: 1404: 1401: 1400: 1397: 1396: 1391: 1389:Quantum memory 1386: 1381: 1376: 1371: 1366: 1365: 1364: 1354: 1349: 1344: 1339: 1334: 1329: 1323: 1321:In development 1320: 1319: 1316: 1315: 1312: 1311: 1306: 1305: 1304: 1299: 1294: 1289: 1284: 1279: 1274: 1269: 1264: 1259: 1254: 1249: 1244: 1239: 1234: 1232:Super Video CD 1229: 1224: 1219: 1214: 1209: 1204: 1198: 1193: 1182: 1177: 1176: 1173: 1172: 1169: 1168: 1163: 1162: 1161: 1156: 1151: 1146: 1141: 1136: 1131: 1126: 1121: 1116: 1111: 1106: 1101: 1096: 1091: 1085: 1080: 1075: 1070: 1065: 1055: 1050: 1045: 1040: 1034: 1029: 1028: 1025: 1024: 1021: 1020: 1015: 1010: 1004: 998: 997: 994: 993: 990: 989: 984: 979: 973: 968: 958: 953: 947: 942: 941: 938: 937: 934: 933: 928: 927: 926: 921: 916: 911: 906: 901: 896: 891: 889:MultiMediaCard 886: 881: 876: 866: 865: 864: 859: 854: 849: 843: 837: 825: 820: 819: 818: 813: 803: 798: 792: 787: 786: 783: 782: 776: 775: 772: 771: 765: 759: 754: 751:Selectron tube 748: 742: 736: 729: 726: 725: 722: 721: 718: 717: 716: 715: 705: 700: 695: 689: 684: 679: 678: 677: 667: 666: 665: 660: 655: 650: 645: 640: 635: 630: 625: 620: 615: 605: 604: 603: 598: 591:Hardware cache 587: 582: 581: 578: 577: 571: 570: 567: 566: 561: 556: 551: 546: 544:Edge computing 541: 536: 531: 526: 524:Grid computing 521: 519:Bank switching 516: 511: 506: 501: 496: 491: 486: 481: 476: 471: 466: 464:Virtual memory 461: 456: 451: 446: 441: 436: 431: 429:Disk mirroring 426: 421: 416: 411: 406: 401: 396: 391: 386: 384:Temporary file 381: 376: 371: 366: 361: 356: 351: 346: 341: 336: 334:Knowledge base 331: 326: 324:Storage record 321: 319:Memory refresh 316: 311: 306: 304:Data structure 301: 296: 291: 286: 281: 276: 271: 266: 261: 256: 251: 246: 241: 236: 231: 226: 221: 216: 211: 206: 201: 199:Data integrity 196: 191: 189:Data cleansing 186: 181: 176: 171: 166: 161: 156: 151: 146: 145: 144: 139: 129: 124: 122:Object storage 119: 114: 109: 104: 103: 102: 92: 87: 82: 77: 72: 67: 62: 56: 53: 52: 49: 48: 26: 9: 6: 4: 3: 2: 8353: 8342: 8339: 8337: 8334: 8333: 8331: 8316: 8313: 8311: 8308: 8306: 8303: 8301: 8300:DRAM timeline 8298: 8297: 8295: 8291: 8285: 8282: 8280: 8277: 8275: 8272: 8270: 8267: 8266: 8264: 8262: 8258: 8252: 8249: 8247: 8244: 8242: 8239: 8238: 8236: 8234: 8230: 8222: 8219: 8217: 8214: 8212: 8209: 8207: 8204: 8202: 8199: 8197: 8194: 8192: 8189: 8188: 8187: 8184: 8182: 8179: 8177: 8174: 8172: 8169: 8168: 8166: 8162: 8156: 8153: 8149: 8146: 8144: 8141: 8139: 8136: 8134: 8131: 8129: 8126: 8125: 8124: 8121: 8119: 8116: 8114: 8111: 8108: 8105: 8102: 8099: 8095: 8092: 8090: 8087: 8085: 8082: 8080: 8077: 8076: 8075: 8072: 8070: 8067: 8066: 8064: 8062: 8058: 8052: 8049: 8047: 8044: 8043: 8041: 8037: 8032: 8025: 8020: 8018: 8013: 8011: 8006: 8005: 8002: 7996: 7993: 7991: 7988: 7986: 7983: 7980: 7977: 7975: 7971: 7968: 7967: 7946: 7942: 7936: 7921:. Tech Report 7920: 7913: 7897: 7893: 7887: 7872: 7868: 7867: 7862: 7856: 7841: 7840: 7835: 7828: 7826: 7810: 7809: 7804: 7797: 7778: 7774: 7767: 7761: 7745: 7741: 7740: 7735: 7729: 7713: 7709: 7703: 7687: 7683: 7682: 7677: 7671: 7669: 7652: 7648: 7647: 7642: 7636: 7620: 7616: 7609: 7593: 7589: 7588: 7581: 7562: 7558: 7557: 7549: 7543: 7527: 7523: 7522: 7517: 7511: 7495: 7491: 7485: 7470: 7466: 7465: 7460: 7454: 7438: 7434: 7428: 7413: 7409: 7408: 7403: 7397: 7388: 7380: 7376: 7372: 7366: 7350: 7346: 7345: 7340: 7334: 7326: 7320: 7304: 7303: 7298: 7292: 7276: 7272: 7271: 7266: 7260: 7245: 7241: 7235: 7233: 7231: 7229: 7227: 7225: 7223: 7203: 7199: 7192: 7186: 7184: 7168: 7164: 7163: 7158: 7152: 7150: 7133: 7132: 7127: 7121: 7119: 7117: 7100: 7096: 7095: 7090: 7084: 7082: 7080: 7060: 7056: 7049: 7043: 7028: 7024: 7018: 7016: 7000: 6996: 6990: 6988: 6986: 6977: 6976:Imagine Media 6973: 6972: 6964: 6945: 6941: 6934: 6928: 6926: 6910:. August 1992 6909: 6905: 6899: 6884: 6880: 6874: 6872: 6870: 6868: 6866: 6858: 6854: 6851: 6846: 6830: 6826: 6825: 6820: 6814: 6812: 6810: 6794: 6790: 6786: 6785: 6778: 6776: 6760: 6756: 6750: 6734: 6730: 6729: 6722: 6720: 6703: 6699: 6698: 6691: 6689: 6671: 6664: 6663: 6655: 6644: 6637: 6636: 6628: 6615:on 2012-04-26 6611: 6604: 6603: 6595: 6582:on 2012-04-26 6578: 6571: 6570: 6562: 6548: 6547: 6539: 6525: 6521: 6514: 6506: 6502: 6496: 6488: 6484: 6478: 6463: 6457: 6442: 6438: 6431: 6416: 6412: 6405: 6390: 6386: 6380: 6366:on 2009-07-13 6365: 6361: 6355: 6340: 6336: 6330: 6322: 6318: 6312: 6304: 6300: 6294: 6286: 6282: 6276: 6270: 6265: 6257: 6250: 6242: 6235: 6227: 6221: 6213: 6209: 6202: 6194: 6188: 6179: 6173: 6158: 6154: 6147: 6145: 6143: 6133: 6118: 6111: 6105: 6098: 6095:refer to the 6094: 6090: 6086: 6082: 6076: 6074: 6072: 6070: 6068: 6066: 6064: 6062: 6060: 6052: 6048: 6044: 6043: 6038: 6032: 6030: 6021: 6017: 6013: 6009: 6005: 6001: 5993: 5985: 5983:9780080553849 5979: 5975: 5974: 5966: 5958: 5956:9780080553849 5952: 5948: 5947: 5939: 5931: 5929:9781786305633 5925: 5921: 5920: 5912: 5908: 5897: 5893: 5890: 5887: 5884: 5881: 5879: 5876: 5874: 5870: 5866: 5862: 5858: 5854: 5850: 5847: 5846: 5836: 5833: 5831: 5828: 5826: 5823: 5820: 5817: 5813: 5810: 5807: 5802: 5801: 5798: 5796: 5795: 5791: 5788: 5785: 5782: 5779: 5776: 5774: 5773: 5769: 5766: 5765: 5762: 5760: 5759: 5755: 5752: 5750: 5747: 5744: 5742: 5739: 5736: 5734: 5733: 5729: 5724: 5723: 5720: 5717: 5714: 5711: 5709: 5706: 5703: 5699: 5696: 5693: 5688: 5687: 5684: 5681: 5679: 5678: 5674: 5672: 5671: 5667: 5664: 5663: 5658: 5657: 5648: 5647: 5641: 5635: 5632: 5630: 5629: 5625: 5622: 5621: 5618: 5615: 5612: 5610: 5609: 5605: 5602: 5599: 5596: 5593: 5590: 5589: 5586: 5583: 5580: 5577: 5574: 5572: 5571: 5567: 5564: 5563: 5560: 5557: 5554: 5551: 5547: 5544: 5542: 5541: 5537: 5534: 5533: 5528: 5527: 5518: 5517: 5513: 5511: 5508: 5505: 5502: 5500: 5499: 5495: 5492: 5491: 5488: 5486: 5485: 5481: 5478: 5476: 5475: 5471: 5468: 5465: 5461: 5458: 5456: 5455: 5451: 5446: 5445: 5442: 5439: 5436: 5434: 5433: 5429: 5426: 5424:SGRAM (GDDR) 5423: 5420: 5417: 5412: 5411: 5407: 5403: 5402: 5397: 5396: 5387: 5386: 5376: 5371: 5370: 5362: 5359: 5357: 5356: 5352: 5349: 5347: 5346: 5342: 5339: 5336: 5332: 5329: 5327: 5326: 5322: 5319: 5318: 5315: 5312: 5309: 5307: 5306: 5302: 5299: 5296: 5293: 5290: 5287: 5286: 5283: 5281: 5280: 5276: 5273: 5271: 5270: 5266: 5264: 5261: 5258: 5254: 5251: 5249: 5248: 5244: 5239: 5238: 5235: 5232: 5229: 5226: 5223: 5220: 5217: 5214: 5211: 5210: 5207: 5204: 5201: 5199: 5198: 5194: 5192: 5189: 5186: 5183: 5180: 5177:December 1994 5175: 5174: 5171: 5168: 5166: 5163: 5161: 5158: 5156: 5153: 5150: 5146: 5143: 5140: 5137: 5134:November 1994 5132: 5131: 5125: 5120: 5117: 5115: 5109: 5106: 5103: 5099: 5096: 5093: 5092: 5088: 5084: 5077:SGRAM and HBM 5070: 5068: 5067: 5063: 5060: 5057: 5054: 5051: 5048: 5047: 5044: 5042: 5041: 5037: 5035: 5032: 5030: 5027: 5024: 5022: 5019: 5016: 5014: 5013: 5005: 5002: 5000: 4999: 4995: 4992: 4989: 4986: 4983: 4980: 4978: 4977: 4973: 4970: 4969: 4966: 4964: 4963: 4959: 4956: 4953: 4950: 4947: 4944: 4942: 4941: 4937: 4934: 4933: 4930: 4928: 4927: 4923: 4920: 4918: 4915: 4912: 4910: 4907: 4905: 4904: 4900: 4898: 4897: 4893: 4890: 4889: 4886: 4884: 4883: 4879: 4876: 4874: 4871: 4868: 4866: 4863: 4860: 4859: 4856: 4854: 4853: 4849: 4846: 4843: 4840: 4837: 4834: 4832: 4831: 4823: 4820: 4817: 4814: 4811: 4808: 4807: 4802: 4801: 4792: 4789: 4786: 4783: 4781: 4780: 4776: 4774: 4773: 4765: 4762: 4761: 4757: 4754: 4751: 4748: 4745: 4742: 4740: 4739: 4735: 4732: 4731: 4726: 4725: 4721: 4718: 4715: 4712: 4709: 4706: 4704: 4703: 4699: 4694: 4693: 4690: 4689: 4685: 4682: 4680: 4677: 4675: 4674: 4670: 4668: 4667: 4663: 4660: 4659: 4654: 4653: 4643: 4640: 4637: 4634: 4632: 4631: 4627: 4624: 4623: 4620: 4618: 4617: 4613: 4610: 4607: 4604: 4601: 4598: 4596: 4595: 4591: 4590: 4587: 4585: 4584: 4580: 4577: 4574: 4571: 4568: 4565: 4563: 4560: 4559: 4556: 4553: 4550: 4548: 4545: 4542: 4539: 4536: 4534: 4531: 4527: 4524: 4522: 4521: 4517: 4514: 4511: 4508: 4505: 4502: 4500: 4499: 4495: 4492: 4491: 4488: 4486: 4485: 4481: 4478: 4476: 4475: 4471: 4468: 4465: 4462: 4461: 4458: 4456: 4455: 4451: 4448: 4446: 4443: 4441: 4438: 4437: 4434: 4432: 4431: 4427: 4424: 4422: 4421: 4417: 4414: 4407: 4404: 4402: 4401: 4397: 4394: 4391: 4388: 4386: 4383: 4380: 4378: 4377: 4372: 4369: 4366: 4363: 4361: 4358: 4355: 4352: 4349: 4347: 4344: 4340: 4337: 4335: 4334: 4330: 4327: 4325: 4324: 4320: 4317: 4314: 4311: 4309: 4308: 4304: 4301: 4300: 4297: 4295: 4294: 4290: 4287: 4285: 4282: 4279: 4277: 4274: 4272: 4271: 4267: 4266: 4263: 4261: 4260: 4256: 4253: 4251: 4250: 4246: 4243: 4240: 4237: 4235: 4234: 4226: 4223: 4220: 4217: 4215: 4212: 4210: 4206: 4203: 4201: 4198: 4195: 4193: 4190: 4187: 4186: 4183: 4181: 4180: 4176: 4173: 4171: 4168: 4165: 4162: 4159: 4158: 4155: 4153: 4152: 4148: 4145: 4143: 4142: 4138: 4135: 4132: 4129: 4127: 4126: 4118: 4115: 4113: 4112: 4108: 4105: 4103: 4102: 4098: 4095: 4092: 4089: 4088: 4085: 4083: 4082: 4078: 4075: 4073: 4072: 4068: 4065: 4062: 4059: 4057: 4056: 4048: 4045: 4043: 4042: 4038: 4035: 4033: 4032: 4028: 4025: 4023: 4020: 4017: 4015: 4014: 4010: 4005: 4004: 4001: 3999: 3998: 3994: 3991: 3989: 3988: 3984: 3982: 3979: 3976: 3973: 3971:Direct RDRAM 3970: 3965: 3964: 3961: 3958: 3955: 3953: 3952: 3948: 3945: 3942: 3939: 3936: 3933: 3932: 3929: 3927: 3926: 3922: 3920: 3917: 3915: 3914: 3910: 3908: 3905: 3902: 3899: 3897: 3896: 3892: 3889: 3888: 3885: 3883: 3882: 3878: 3875: 3873: 3870: 3868: 3865: 3862: 3859: 3857: 3856: 3852: 3851: 3848: 3846: 3845: 3841: 3838: 3836: 3835: 3831: 3829: 3826: 3823: 3820: 3818: 3815: 3814: 3811: 3808: 3805: 3803: 3802: 3798: 3796: 3793: 3791: 3788: 3785: 3782: 3778: 3775: 3773: 3772: 3768: 3766: 3763: 3761: 3760: 3756: 3754: 3751: 3749: 3746: 3744: 3740: 3737: 3734: 3733: 3727: 3722: 3719: 3717: 3711: 3708: 3705: 3701: 3698: 3695: 3694: 3677: 3674:December 2023 3665: 3660: 3651: 3650: 3646: 3642: 3638: 3628: 3626: 3622: 3618: 3614: 3610: 3605: 3595: 3593: 3589: 3581: 3579: 3575: 3571: 3567: 3563: 3559: 3555: 3551: 3547: 3543: 3539: 3535: 3529: 3519: 3517: 3513: 3509: 3505: 3501: 3497: 3488: 3486: 3482: 3478: 3474: 3470: 3466: 3462: 3452: 3448: 3445: 3441: 3437: 3433: 3429: 3427: 3423: 3419: 3414: 3410: 3400: 3397: 3393: 3391: 3387: 3379: 3376: 3373: 3370: 3367: 3364: 3363: 3362: 3359: 3352: 3349: 3346: 3343: 3340: 3337: 3336: 3318: 3317: 3307: 3306: 3290: 3289: 3273: 3272: 3268: 3265: 3262: 3259: 3256: 3253: 3250: 3247: 3244: 3241: 3238: 3237: 3231: 3228: 3224: 3222: 3218: 3213: 3212:open standard 3202: 3199: 3190: 3182: 3177: 3167: 3165: 3161: 3157: 3153: 3148: 3146: 3142: 3137: 3135: 3131: 3126: 3123: 3119: 3113: 3103: 3099: 3097: 3093: 3088: 3083: 3073: 3070: 3066: 3061: 3051: 3047: 3045: 3040: 3037: 3030: 3020: 3018: 3013: 3009: 3005: 3001: 2997: 2988: 2984: 2982: 2978: 2975: 2971: 2967: 2963: 2959: 2951: 2945: 2935: 2933: 2929: 2928:Intel Celeron 2925: 2924:PowerBook G3s 2921: 2917: 2913: 2909: 2908:Intel Pentium 2904: 2902: 2898: 2894: 2890: 2886: 2877: 2875: 2871: 2866: 2862: 2858: 2856: 2852: 2848: 2840: 2836: 2833: 2828: 2807: 2805: 2801: 2795: 2789: 2787: 2783: 2779: 2762: 2760: 2756: 2749: 2745: 2739: 2730: 2728: 2725: 2722: 2721: 2719: 2717: 2713: 2707: 2703: 2694: 2693: 2691: 2687: 2679: 2665: 2662: 2659: 2656: 2653: 2650: 2647: 2644: 2641: 2638: 2637: 2636: 2633: 2631: 2626: 2622: 2618: 2614: 2612: 2608: 2604: 2601: 2596: 2591: 2589: 2579: 2577: 2571: 2567: 2559: 2556: 2547: 2534: 2526: 2523: 2519: 2516: 2513: 2512: 2511: 2508: 2502:Mode register 2499: 2495: 2493: 2488: 2484: 2479: 2475: 2473: 2469: 2465: 2455: 2452: 2448: 2444: 2440: 2437: 2428: 2425: 2400: 2397: 2388: 2380: 2377: 2372: 2369: 2364: 2362: 2358: 2353: 2351: 2347: 2343: 2335: 2331: 2326: 2324: 2319: 2314: 2311: 2301: 2281: 2278: 2275: 2272: 2269: 2266: 2263: 2260: 2259: 2258: 2242: 2229: 2203: 2177: 2164: 2151: 2141: 2128: 2121: 2115: 2102: 2095: 2089: 2076: 2069: 2063: 2050: 2043: 2037: 2024: 1998: 1995:No operation 1972: 1946: 1942: 1940: 1936: 1933: 1931: 1927: 1922: 1917: 1912: 1907: 1906: 1903: 1895: 1887: 1867: 1862: 1851: 1846: 1835: 1831: 1826: 1825: 1815: 1811: 1808: 1805: 1800: 1796: 1793: 1792: 1791: 1789: 1779: 1775: 1771: 1769: 1764: 1748: 1744: 1728: 1726: 1722: 1718: 1714: 1709: 1707: 1703: 1699: 1694: 1692: 1688: 1684: 1680: 1676: 1671: 1669: 1665: 1660: 1658: 1654: 1650: 1646: 1639: 1635: 1631: 1627: 1623: 1618: 1611: 1607: 1602: 1593: 1590: 1586: 1584: 1580: 1579: 1573: 1569: 1565: 1561: 1557: 1552: 1550: 1546: 1542: 1538: 1534: 1526: 1515: 1510: 1508: 1503: 1501: 1496: 1495: 1493: 1492: 1484: 1481: 1478: 1477:Bubble memory 1475: 1472: 1469: 1466: 1463: 1460: 1457: 1454: 1451: 1448: 1445: 1442: 1439: 1436: 1433: 1431: 1428: 1425: 1422: 1419: 1416: 1413: 1410: 1409: 1403: 1402: 1395: 1392: 1390: 1387: 1385: 1382: 1380: 1377: 1375: 1372: 1370: 1367: 1363: 1360: 1359: 1358: 1355: 1353: 1350: 1348: 1345: 1343: 1340: 1338: 1335: 1333: 1330: 1328: 1325: 1324: 1318: 1317: 1310: 1307: 1303: 1300: 1298: 1295: 1293: 1290: 1288: 1285: 1283: 1280: 1278: 1275: 1273: 1270: 1268: 1265: 1263: 1260: 1258: 1255: 1253: 1250: 1248: 1245: 1243: 1240: 1238: 1235: 1233: 1230: 1228: 1225: 1223: 1220: 1218: 1215: 1213: 1210: 1208: 1205: 1202: 1199: 1197: 1194: 1192: 1189: 1188: 1187: 1184: 1183: 1180: 1175: 1174: 1167: 1164: 1160: 1157: 1155: 1152: 1150: 1147: 1145: 1142: 1140: 1137: 1135: 1132: 1130: 1127: 1125: 1122: 1120: 1117: 1115: 1112: 1110: 1107: 1105: 1104:Cassette tape 1102: 1100: 1099:Videocassette 1097: 1095: 1092: 1089: 1086: 1084: 1081: 1079: 1076: 1074: 1071: 1069: 1068:Magnetic tape 1066: 1064: 1061: 1060: 1059: 1056: 1054: 1051: 1049: 1046: 1044: 1041: 1039: 1036: 1035: 1032: 1027: 1026: 1019: 1016: 1014: 1011: 1009: 1006: 1005: 1002: 996: 995: 988: 985: 983: 980: 977: 974: 972: 969: 966: 962: 959: 957: 954: 952: 949: 948: 945: 940: 939: 932: 929: 925: 922: 920: 917: 915: 912: 910: 907: 905: 902: 900: 897: 895: 892: 890: 887: 885: 882: 880: 877: 875: 872: 871: 870: 867: 863: 860: 858: 855: 853: 850: 847: 844: 841: 838: 835: 832: 831: 829: 826: 824: 823:ROM cartridge 821: 817: 814: 812: 809: 808: 807: 804: 802: 799: 797: 794: 793: 790: 785: 784: 781: 778: 777: 769: 766: 763: 760: 758: 755: 752: 749: 746: 743: 740: 737: 734: 731: 730: 724: 723: 714: 711: 710: 709: 706: 704: 701: 699: 696: 693: 690: 688: 685: 683: 680: 676: 673: 672: 671: 668: 664: 661: 659: 656: 654: 651: 649: 646: 644: 641: 639: 636: 634: 631: 629: 626: 624: 621: 619: 616: 614: 611: 610: 609: 606: 602: 599: 597: 594: 593: 592: 589: 588: 585: 580: 579: 576: 573: 572: 565: 562: 560: 557: 555: 552: 550: 549:Dew computing 547: 545: 542: 540: 539:Fog computing 537: 535: 534:Cloud storage 532: 530: 527: 525: 522: 520: 517: 515: 514:Memory paging 512: 510: 507: 505: 502: 500: 497: 495: 492: 490: 487: 485: 482: 480: 477: 475: 472: 470: 467: 465: 462: 460: 457: 455: 452: 450: 447: 445: 442: 440: 437: 435: 432: 430: 427: 425: 422: 420: 417: 415: 412: 410: 407: 405: 402: 400: 397: 395: 392: 390: 387: 385: 382: 380: 377: 375: 372: 370: 367: 365: 362: 360: 357: 355: 352: 350: 349:File deletion 347: 345: 342: 340: 339:Computer file 337: 335: 332: 330: 327: 325: 322: 320: 317: 315: 312: 310: 307: 305: 302: 300: 297: 295: 292: 290: 287: 285: 282: 280: 277: 275: 272: 270: 267: 265: 262: 260: 257: 255: 252: 250: 247: 245: 242: 240: 237: 235: 232: 230: 227: 225: 222: 220: 219:Data recovery 217: 215: 212: 210: 207: 205: 204:Data security 202: 200: 197: 195: 192: 190: 187: 185: 182: 180: 177: 175: 172: 170: 167: 165: 162: 160: 157: 155: 152: 150: 147: 143: 140: 138: 135: 134: 133: 130: 128: 125: 123: 120: 118: 115: 113: 110: 108: 105: 101: 100:floating-gate 98: 97: 96: 93: 91: 88: 86: 83: 81: 78: 76: 73: 71: 68: 66: 63: 61: 58: 57: 51: 50: 46: 42: 39: 38: 33: 19: 8103:(Mobile DDR) 8068: 8060: 8039:Asynchronous 7949:. Retrieved 7944: 7935: 7923:. Retrieved 7912: 7900:. Retrieved 7886: 7874:. Retrieved 7864: 7855: 7843:. Retrieved 7837: 7812:. Retrieved 7806: 7796: 7784:. Retrieved 7760: 7748:. Retrieved 7737: 7728: 7716:. Retrieved 7714:. March 2005 7702: 7690:. Retrieved 7679: 7655:. Retrieved 7644: 7635: 7623:. Retrieved 7618: 7608: 7596:. Retrieved 7586: 7580: 7568:. Retrieved 7554: 7542: 7530:. Retrieved 7526:the original 7519: 7510: 7498:. Retrieved 7484: 7472:. Retrieved 7462: 7453: 7441:. Retrieved 7436: 7427: 7415:. Retrieved 7405: 7396: 7387: 7374: 7365: 7353:. Retrieved 7342: 7333: 7307:. Retrieved 7302:The Inquirer 7300: 7291: 7279:. Retrieved 7268: 7259: 7247:. Retrieved 7243: 7209:. Retrieved 7170:. Retrieved 7160: 7136:. Retrieved 7129: 7103:. Retrieved 7092: 7066:. Retrieved 7042: 7030:. Retrieved 7026: 7002:. Retrieved 6998: 6969: 6963: 6951:. Retrieved 6912:. Retrieved 6898: 6886:. Retrieved 6882: 6845: 6833:. Retrieved 6822: 6796:. Retrieved 6783: 6762:. Retrieved 6758: 6749: 6737:. Retrieved 6727: 6706:. Retrieved 6696: 6677:, retrieved 6661: 6659:NEC (1999), 6654: 6634: 6627: 6617:, retrieved 6610:the original 6601: 6594: 6584:, retrieved 6577:the original 6568: 6561: 6551:, retrieved 6545: 6538: 6527:. Retrieved 6523: 6513: 6495: 6486: 6477: 6466:. Retrieved 6456: 6445:. Retrieved 6441:the original 6430: 6419:. Retrieved 6415:the original 6404: 6393:. Retrieved 6391:. 2011-08-22 6379: 6368:. Retrieved 6364:the original 6354: 6343:. Retrieved 6339:the original 6329: 6321:heise online 6320: 6311: 6302: 6293: 6284: 6275: 6264: 6249: 6243:. Anandtech. 6234: 6220: 6211: 6201: 6187: 6172: 6161:. Retrieved 6156: 6132: 6121:. Retrieved 6119:. April 2003 6116: 6104: 6092: 6088: 6084: 6080: 6050: 6046: 6040: 6003: 5999: 5992: 5972: 5965: 5945: 5938: 5918: 5911: 5834:225 mm 5804:January 2018 5793: 5792: 5771: 5770: 5757: 5756: 5731: 5730: 5718:140 mm 5676: 5675: 5669: 5668: 5655: 5654: 5645: 5644: 5627: 5626: 5616:100 mm 5607: 5606: 5569: 5568: 5539: 5538: 5525: 5524: 5515: 5514: 5497: 5496: 5483: 5482: 5473: 5472: 5453: 5452: 5448:October 2005 5431: 5430: 5394: 5393: 5384: 5383: 5368: 5367: 5354: 5353: 5344: 5343: 5324: 5323: 5313:280 mm 5304: 5303: 5297:SGRAM (SDR) 5278: 5277: 5268: 5267: 5246: 5245: 5233:280 mm 5227:350 nm 5221:SGRAM (SDR) 5205:280 mm 5196: 5195: 5187:SGRAM (SDR) 5085:(SGRAM) and 5065: 5064: 5039: 5038: 5011: 5010: 4997: 4996: 4975: 4974: 4961: 4960: 4939: 4938: 4925: 4924: 4902: 4901: 4895: 4894: 4881: 4880: 4851: 4850: 4829: 4828: 4799: 4798: 4778: 4777: 4771: 4770: 4759: 4758: 4737: 4736: 4723: 4722: 4701: 4700: 4687: 4686: 4672: 4671: 4665: 4664: 4651: 4650: 4629: 4628: 4615: 4614: 4593: 4592: 4582: 4581: 4519: 4518: 4497: 4496: 4483: 4482: 4473: 4472: 4453: 4452: 4429: 4428: 4419: 4418: 4399: 4398: 4375: 4374: 4332: 4331: 4322: 4321: 4306: 4305: 4292: 4291: 4269: 4268: 4258: 4257: 4248: 4247: 4232: 4231: 4221:279 mm 4178: 4177: 4150: 4149: 4140: 4139: 4124: 4123: 4110: 4109: 4100: 4099: 4080: 4079: 4070: 4069: 4054: 4053: 4040: 4039: 4030: 4029: 4012: 4011: 3996: 3995: 3986: 3985: 3959:325 mm 3950: 3949: 3924: 3923: 3912: 3911: 3894: 3893: 3880: 3879: 3854: 3853: 3843: 3842: 3833: 3832: 3809:325 mm 3800: 3799: 3770: 3769: 3758: 3757: 3671: 3663: 3607: 3582: 3531: 3489: 3465:framebuffers 3458: 3449: 3446: 3442: 3438: 3434: 3430: 3406: 3398: 3394: 3383: 3360: 3356: 3294:Command code 3229: 3225: 3208: 3196: 3188: 3179: 3149: 3144: 3140: 3138: 3127: 3115: 3100: 3089: 3085: 3071: 3067: 3063: 3048: 3043: 3041: 3032: 3010:and 144-pin 2995: 2994: 2985: 2977:form factors 2972:and 144-pin 2957: 2956: 2916:Power Mac G3 2905: 2899:and 144-pin 2884: 2883: 2867: 2863: 2859: 2846: 2844: 2741:2.5 - 7.5 ns 2634: 2627: 2623: 2619: 2615: 2592: 2585: 2572: 2568: 2560: 2557: 2553: 2540: 2537:Auto refresh 2531: 2509: 2505: 2496: 2487:exclusive or 2480: 2476: 2461: 2453: 2449: 2445: 2441: 2438: 2434: 2426: 2406: 2395: 2389: 2381: 2375: 2373: 2367: 2365: 2360: 2356: 2354: 2349: 2345: 2341: 2333: 2329: 2327: 2317: 2315: 2309: 2306: 2256: 1938: 1929: 1901: 1893: 1884: 1863: 1847: 1833: 1827: 1813: 1809: 1801: 1794: 1785: 1776: 1772: 1765: 1734: 1710: 1706:workstations 1695: 1672: 1661: 1619: 1615: 1587: 1576: 1563: 1560:asynchronous 1559: 1553: 1549:clock signal 1540: 1536: 1532: 1531: 1424:Punched tape 1418:Punched card 1384:Time crystal 1252:Hyper CD-ROM 1191:Optical disc 1083:Tape library 1018:FeFET memory 999:Early-stage 879:CompactFlash 874:Memory Stick 834:Flash memory 796:Diode matrix 780:Non-volatile 617: 564:Kryder's law 554:Amdahl's law 479:Software rot 454:Logical disk 354:File copying 289:Data storage 244:File sharing 229:Data cluster 8061:Synchronous 6006:(5): 1118. 5808:K4ZAF325BM 5786:20 nm 5712:20 nm 5594:K4W1G1646G 5440:77 mm 5418:K4D553238F 5291:KM4132G112 5215:μPD4811650 5169:58 mm 5107:SDRAM type 5058:10 nm 4990:20 nm 4954:20 nm 4844:40 nm 4835:16384 Mbit 4752:50 nm 4743:16384 Mbit 4716:50 nm 4644:60 nm 4608:80 nm 4575:90 nm 4562:Xenos eDRAM 4554:86 mm 4533:EE+GS eDRAM 4512:80 nm 4392:90 nm 4367:86 mm 4346:EE+GS eDRAM 3872:150 nm 3783:MSM5718C50 3738:KM48SL2000 3709:SDRAM type 3615:SDRAM from 3508:PlayStation 3473:bit masking 3469:video cards 3467:, found on 3422:northbridge 3096:CAS latency 2979:. PC100 is 2770:1.25 - 5 ns 2671:Generations 2468:cache lines 1768:CAS latency 1632:released a 1583:interleaved 1564:synchronous 1483:Floppy disk 1435:Drum memory 869:Memory card 836:is used in: 770:(2002–2010) 735:(1946–1947) 559:Moore's law 404:Boot sector 344:Object file 249:File system 60:Memory cell 8330:Categories 7925:18 January 6679:2012-07-17 6619:2011-12-27 6586:2011-12-27 6553:2011-01-01 6529:2020-07-15 6468:2011-03-13 6447:2009-06-17 6421:2009-06-16 6395:2011-01-06 6370:2009-06-16 6345:2011-01-03 6163:2021-04-13 6123:2015-08-02 5903:References 5749:20 nm 5690:March 2016 5633:4096 Mbit 5597:1024 Mbit 5585:40 nm 5575:2048 Mbit 5559:60 nm 5545:1024 Mbit 5414:March 2005 5181:μPD481850 5138:HM5283206 5100:Capacity ( 5097:Chip name 5017:8192 Mbit 4945:8192 Mbit 4873:30 nm 4861:2048 Mbit 4809:2048 Mbit 4707:8192 Mbit 4696:April 2008 4635:1024 Mbit 4503:2048 Mbit 4463:1024 Mbit 4160:1024 Mbit 3967:March 1998 3937:MD5764802 3900:1024 Mbit 3867:Mitsubishi 3860:1024 Mbit 3702:Capacity ( 3699:Chip name 3635:See also: 3613:3D-stacked 3538:GDDR SDRAM 3528:GDDR SDRAM 3390:ECC memory 3176:DDR5 SDRAM 3118:DDR3 SDRAM 3112:DDR4 SDRAM 3082:DDR3 SDRAM 3060:DDR2 SDRAM 2944:NEC PC-100 2835:sound card 2664:DDR5 SDRAM 2658:DDR4 SDRAM 2652:DDR3 SDRAM 2646:DDR2 SDRAM 2588:data words 2576:Mobile DDR 2483:burst mode 2323:refreshing 1788:active low 1698:registered 1691:DDR3 SDRAM 1640:, chip (64 1589:Pipelining 1406:Historical 1078:Tape drive 904:SmartMedia 727:Historical 424:Disk image 419:Disk array 294:Data store 95:MOS memory 85:Memory map 32:NEC PC-100 8310:Bandwidth 8251:XDR2 DRAM 8074:DDR SDRAM 7974:AnandTech 7839:AnandTech 7808:AnandTech 7437:SlashGear 7319:cite news 7157:"History" 6524:AnandTech 6117:intel.com 5726:June 2016 5503:512 Mbit 5459:256 Mbit 5421:256 Mbit 5374:256 Mbit 5330:128 Mbit 5049:128 Gbit 4599:512 Mbit 4409:512 Mbit 4312:256 Mbit 4238:288 Mbit 4130:128 Mbit 4090:128 Mbit 4007:June 1998 3817:N64 RDRAM 3594:in 1998. 3542:DDR SDRAM 3532:Graphics 3516:SCPH-5000 3485:dual-port 3280:Device ID 3217:DDR SDRAM 3139:DDR4 did 3029:DDR SDRAM 3004:SDR SDRAM 2772:per cycle 2743:per cycle 2640:DDR SDRAM 1668:bandwidth 1638:DDR SDRAM 1543:) is any 1465:Disk pack 1430:Plugboard 1267:DVD-Video 1196:LaserDisc 1094:Videotape 965:3D XPoint 956:Memristor 596:CPU cache 364:Core dump 284:Data bank 234:Directory 18:SDR SDRAM 8246:XDR DRAM 8164:Graphics 8051:EDO DRAM 8046:FPM DRAM 7945:Wccftech 7777:Archived 7561:Archived 7379:Archived 7202:Archived 7131:Phys.org 7059:Archived 6995:"Memory" 6944:Archived 6853:Archived 6670:archived 6643:archived 6487:TechSpot 5843:See also 5821:Samsung 5811:16 Gbit 5783:Samsung 5777:64 Gbit 5745:Samsung 5737:32 Gbit 5640:SK Hynix 5603:Samsung 5469:Samsung 5427:Samsung 5380:Samsung 5340:Samsung 5300:Samsung 5294:32 Mbit 5252:16 Mbit 5218:16 Mbit 5055:Samsung 5025:Samsung 4987:Samsung 4981:12 Gbit 4951:Samsung 4913:Samsung 4749:Samsung 4713:Samsung 4605:Samsung 4566:80 Mbit 4537:32 Mbit 4509:Samsung 4389:Samsung 4381:72 Mbit 4350:32 Mbit 4280:Samsung 4196:32 Mbit 4192:GS eDRAM 4166:Samsung 4136:Samsung 4096:Samsung 4066:Hyundai 4060:64 Mbit 4026:Samsung 4018:64 Mbit 3974:72 Mbit 3940:64 Mbit 3821:36 Mbit 3786:18 Mbit 3631:Timeline 3625:SK Hynix 2918:, early 2792:Signal: 2776:Signal: 2746:Signal: 2704:Signal: 1943:Command 1898:Commands 1717:SK Hynix 1653:SK Hynix 1394:UltraRAM 1272:DVD card 1227:Video CD 1212:CD Video 982:Nano-RAM 951:Memistor 924:XQD card 899:SIM card 757:Dekatron 643:XDR DRAM 638:EDO DRAM 575:Volatile 369:Hex dump 279:Database 174:Metadata 169:Big data 8279:UniDIMM 8143:HBM-PIM 8109:(FCRAM) 7951:16 July 7902:15 July 7896:Samsung 7876:16 July 7871:Samsung 7845:29 June 7814:16 July 7786:10 July 7744:Samsung 7718:10 July 7692:26 June 7686:Samsung 7657:10 July 7651:Samsung 7625:10 July 7598:10 July 7570:10 July 7532:4 April 7494:Samsung 7474:25 June 7469:Samsung 7443:25 June 7417:25 June 7412:Samsung 7355:25 June 7349:Samsung 7309:25 June 7281:25 June 7275:Samsung 7249:4 April 7244:az5miao 7211:26 June 7172:19 June 7167:Samsung 7138:23 June 7105:23 June 7099:Samsung 7068:21 June 7032:4 April 7027:az5miao 7004:25 June 6953:21 June 6914:19 June 6908:Samsung 6888:4 April 6883:az5miao 6835:23 June 6829:Samsung 6798:21 June 6764:10 July 6755:"PU-18" 6739:10 July 6708:10 July 6702:Hitachi 6008:Bibcode 5814:SGRAM ( 5700:SGRAM ( 5697:8 Gbit 5548:SGRAM ( 5462:SGRAM ( 5404:SGRAM ( 5333:SGRAM ( 5263:Samsung 5255:SGRAM ( 5184:8 Mbit 5155:Hitachi 5141:8 Mbit 5114:Process 5061:FinFET 4984:LPDDR4 4948:LPDDR4 4209:Toshiba 3907:Hyundai 3753:Samsung 3716:Process 3664:updated 3617:Samsung 3536:SDRAM ( 3496:Hitachi 3331:Column 3156:Samsung 3152:Samsung 3092:latency 3012:SO-DIMM 2974:SO-DIMM 2901:SO-DIMM 2813:≤ 1.2 V 2794:SSTL_15 2780:(1.8V) 2778:SSTL_18 2736:= 2.5 V 2700:= 3.3 V 2595:bitline 2366:When a 1702:servers 1630:Samsung 1612:package 1606:Hyundai 1596:History 1479:(~1970) 1473:(~1968) 1455:(1960s) 1292:Blu-ray 1282:MiniDVD 1277:DVD-RAM 1237:Mini CD 1179:Optical 1139:U-matic 1134:MicroMV 1114:Betamax 978:(ECRAM) 919:MicroP2 894:SD card 884:PC Card 675:1T-SRAM 633:QDRSRAM 224:Storage 54:General 8233:Rambus 8118:RLDRAM 8033:(DRAM) 7750:8 July 7500:8 July 7055:Rambus 6759:PSXDEV 6079:Here, 5980: 5953: 5926: 5830:FinFET 5708:Micron 5702:GDDR5X 5581:Hynix 5555:Hynix 5160:350 nm 5119:MOSFET 5089:(HBM) 5034:FinFET 5021:LPDDR5 4909:LPDDR4 4869:Hynix 4841:Hynix 4815:Hynix 4787:Hynix 4683:Hynix 4679:LPDDR2 4641:Hynix 4569:eDRAM 4540:eDRAM 4469:Hynix 4445:110 nm 4440:Elpida 4415:Hynix 4353:eDRAM 4318:Hynix 4284:100 nm 4244:Hynix 4241:RDRAM 4214:180 nm 4170:140 nm 3981:Rambus 3977:RDRAM 3943:RDRAM 3824:RDRAM 3721:MOSFET 3643:, and 3585: 3578:GDDR6W 3574:GDDR6X 3566:GDDR5X 3492: 3386:caches 3365:CMD5=0 3160:Gbit/s 2920:iBooks 2912:AMD K6 2889:memory 2839:Micron 2796:(1.5V) 2750:(2.5V) 2748:SSTL_2 2689:SDRAM 2472:bursts 2396:active 2342:active 2318:active 2122:column 2096:column 2070:column 2044:column 1731:Timing 1723:, and 1642: 1604:Eight 1485:(1971) 1467:(1962) 1461:(1962) 1449:(1957) 1443:(1949) 1437:(1932) 1426:(1725) 1420:(1725) 1414:(1725) 1287:HD DVD 1247:CD-ROM 1203:(CDDA) 1129:MiniDV 848:(SSHD) 830:(SSS) 816:EEPROM 764:(2009) 753:(1952) 747:(1951) 741:(1947) 359:Backup 8336:SDRAM 8293:Lists 8241:RDRAM 8221:GDDR7 8216:GDDR6 8211:GDDR5 8206:GDDR4 8201:GDDR3 8196:GDDR2 8186:SGRAM 8181:MDRAM 8148:HBM3E 8133:HBM2E 8113:eDRAM 8101:LPDDR 8069:SDRAM 7861:"HBM" 7780:(PDF) 7769:(PDF) 7564:(PDF) 7551:(PDF) 7205:(PDF) 7194:(PDF) 7062:(PDF) 7051:(PDF) 6947:(PDF) 6936:(PDF) 6673:(PDF) 6666:(PDF) 6646:(PDF) 6639:(PDF) 6613:(PDF) 6606:(PDF) 6580:(PDF) 6573:(PDF) 6505:JEDEC 6389:JEDEC 6303:Alphr 6113:(PDF) 6091:, or 5873:GDDR7 5869:GDDR6 5865:GDDR5 5861:GDDR4 5857:GDDR3 5853:GDDR2 5825:10 nm 5816:GDDR6 5789:CMOS 5780:HBM2 5767:2017 5753:CMOS 5715:CMOS 5665:2013 5651:CMOS 5623:2012 5613:CMOS 5591:2010 5565:2009 5550:GDDR5 5535:2007 5521:CMOS 5510:Hynix 5493:2005 5479:CMOS 5464:GDDR4 5437:CMOS 5406:GDDR3 5390:CMOS 5364:2003 5350:CMOS 5335:GDDR2 5320:2002 5310:CMOS 5288:1999 5274:CMOS 5230:CMOS 5212:1997 5202:CMOS 5145:SGRAM 5123:Area 5052:DDR4 5029:10 nm 5007:2018 4993:CMOS 4971:2015 4957:CMOS 4935:2014 4921:CMOS 4917:20 nm 4891:2013 4877:CMOS 4847:CMOS 4838:DDR3 4825:2011 4819:40 nm 4812:DDR3 4795:CMOS 4791:44 nm 4784:DDR3 4767:2009 4755:CMOS 4746:DDR3 4733:2008 4719:CMOS 4710:DDR3 4661:2008 4647:CMOS 4638:DDR2 4625:2006 4611:CMOS 4602:DDR3 4578:CMOS 4551:CMOS 4547:65 nm 4529:2005 4515:CMOS 4506:DDR2 4493:2004 4479:CMOS 4466:DDR2 4449:CMOS 4425:CMOS 4412:DDR2 4395:CMOS 4364:CMOS 4360:90 nm 4342:2003 4328:CMOS 4302:2002 4288:CMOS 4254:CMOS 4228:2001 4218:CMOS 4200:eDRAM 4188:2000 4174:CMOS 4146:CMOS 4120:1999 4106:CMOS 4076:CMOS 4050:1998 4036:CMOS 3992:CMOS 3956:CMOS 3934:1998 3890:1997 3876:CMOS 3839:CMOS 3806:CMOS 3790:RDRAM 3780:1996 3735:1992 3725:Area 3686:SDRAM 3570:GDDR6 3562:GDDR5 3558:GDDR4 3554:GDDR3 3550:GDDR2 3510:(PS) 3413:RDRAM 3286:CMD5 3198:RDRAM 3000:JEDEC 2996:PC133 2991:PC133 2966:JEDEC 2958:PC100 2938:PC100 2893:JEDEC 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