144:
84:, usually by name or number. The primary task of the router is to create geometries such that all terminals assigned to the same net are connected, no terminals assigned to different nets are connected, and all design rules are obeyed. A router can fail by not connecting terminals that should be connected (an open), by mistakenly connecting two terminals that should not be connected (a short), or by creating a design rule violation. In addition, to correctly connect the nets, routers may also be expected to make sure the design meets timing, has no
157:(DRC). Some more advanced interactive routers have "push and shove" (aka "shove-aside" or "automoving") features in an interactive router; the EDA tool pushes other nets out of the way, if possible, in order to place a new wire where the drafter wants it and still avoid violating DRC. Modern PCB design software also typically provides "autorouters" that route all remaining unrouted connections without human intervention.
152:
The earliest types of EDA routers were "manual routers"—the drafter clicked a mouse on the endpoint of each line segment of each net. Modern PCB design software typically provides "interactive routers"—the drafter selects a pad and clicks a few places to give the EDA tool an idea of where to go, and
373:
An alternative approach is to treat shorts, design rule violations, obstructions, etc. on a similar footing as excess wire length—that is, as finite costs to be reduced (at first) rather than as absolutes to be avoided. This multi-pass "iterative-improvement" routing method is described by the
395:
Most routers assign wiring layers to carry predominantly "x" or "y" directional wiring, though there have been routers which avoid or reduce the need for such assignment. There are advantages and disadvantages to each approach. Restricted directions make power supply design and the control of
126:
Design rules sometimes vary considerably from layer to layer. For example, the allowed width and spacing on the lower layers may be four or more times smaller than the allowed widths and spacings on the upper layers. This introduces many additional complications not faced by routers for other
381:
Prescribe or adjust the weight parameters of an "objective function" (having a weight parameter value for each unit of excess wire length, and for each type of violation). E.g., for the first pass, excess wire length may typically be given a high cost, while design violations such as shorts,
147:
A PCB as a design on a computer (left) and realized as a board assembly populated with components (right). The board is double sided, with through-hole plating, green solder resist and a white legend. Both surface mount and through-hole components have been
365:
If not all nets can be successfully routed, apply any of a variety of "cleanup" methods, in which selected routings are removed, the order of the remaining nets to be routed is changed, and the remaining routings are attempted
388:"Rip up" (if previously routed) and reroute each net in turn, so as to minimize the value of the objective function for that net. (Some of the routings will in general have shorts or other design violations.)
844:
65:, which determines the location of each active element of an IC or component on a PCB. After placement, the routing step adds wires needed to properly connect the placed components while obeying all
1156:
1131:
343:, and may optionally include layer assignment. Global routing limits the size and complexity of the following detailed routing steps, which can be done grid square by grid square.
382:
adjacency, etc. are given a low cost. In later passes, the relative ordering of costs is changed so that violations are high-cost, or may be prohibited absolutely.
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135:
design. Particular difficulties ensue if the rules are not simple multiples of each other, and when vias must traverse between layers with different rules.
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225:
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993:
201:
391:
Proceed to the next iterative pass until routing is complete and correct, is not further improved, or some other termination criterion is satisfied.
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217:
396:
inter-layer crosstalk easier, but allowing arbitrary routes can reduce the need for vias and decrease the number of required wiring layers.
80:(also called terminals) on cells, and optionally some pre-existing wiring called preroutes. Each of these polygons are associated with a
1592:
1630:
618:
62:
592:
1532:
1260:
658:
Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005).
107:, both in the case where all angles are allowed or if routing is restricted to only horizontal and vertical wires. Variants of
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problem, of finding the shortest route for one net in one layer with no obstacles and no design rules is known to be
842:
Reed, James B.; Sangiovanni-Vincentelli, Alberto; Santamauro, Mauro (1985). "A new symbolic channel router: YACR2".
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119:, and so on. Routers therefore seldom attempt to find an optimum result. Instead, almost all routing is based on
96:
674:
1652:
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17:
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339:
First, determine an approximate course for each net, often by routing on a coarse grid. This step is called
1346:
405:
120:
31:
1769:
1664:
1053:
1333:
1684:
1642:
1167:
92:, and so on. This long list of often conflicting objectives is what makes routing extremely difficult.
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The task of all routers is the same. They are given some pre-existing polygons consisting of
54:
1252:
616:
Lee, Chester Y. (September 1961). "An algorithm for path connections and its applications".
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1679:
1674:
1657:
1377:
770:
Hightower, David W. (1969). "A solution to line-routing problems on the continuous plane".
322:
SimplifyPCB (a topological router with a focus on bundle routing with hand-routing results)
154:
8:
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Select (or randomly choose) a sequence in which nets are to be routed during this pass.
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58:
153:
the EDA tool tries to place wires as close to that path as possible without violating
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This process repeats until all nets are routed or the program (or user) gives up.
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1485:
1445:
1090:"Computer-Partner Kiel GmbH: "Bloodhound" entflechtet Leiterplatten auf 16 Lagen"
420:
70:
69:
for the IC. Together, the placement and routing steps of IC design are known as
1555:
1233:
1210:
893:
886:
Shankar, Ravi; Fernandez, Eduardo B. (2014-01-12). Einspruch, Norman G. (ed.).
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294:
196:
108:
89:
857:
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1719:
1714:
1094:
989:
971:
949:
Finch, Alan C.; Mackenzie, Ken J.; Balsdon, G. J.; Symonds, G. (1985-06-23).
845:
IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems
627:
495:
IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems
475:
538:
451:
788:(NB. This contains one of the first descriptions of a "line probe router".)
737:
100:
66:
783:
1126:
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164:
111:
have also been shown to be NP-complete, as well as routing which reduces
104:
1291:
Scheffer, Louis K.; Lavagno, Luciano; Martin, Grant (2006). "Chapter 8:
1273:
1196:"Simplify Design Automation – the next generation in design methodology"
1774:
1440:
1385:
1218:
660:"11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards"
298:
290:
1338:
1253:"An iterative-improvement penalty-function-driven wire routing system"
958:. 22nd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA.
1400:
1334:
http://www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/10-grid-routing.pdf
1300:
841:
775:
772:
DAC'69: Proceedings of the 6th Annual
Conference on Design Automation
670:
316:
304:
112:
88:
problems, meets any metal density requirements, does not suffer from
85:
753:
A computer program for optimal routing of printed circuit connectors
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312:
243:
692:
657:
229:
566:
30:
This article is about designing integrated circuits, as part of
284:
1297:
Electronic Design
Automation For Integrated Circuits Handbook
1019:"A Tribute to Alan Finch, the Father of Gridless Autorouting"
756:
276:
270:
237:
1195:
1157:"1.6. Rechnergestützter Leiterplattenentwurf - Entflechtung"
948:
95:
Almost every problem associated with routing is known to be
960:
Design
Automation Conference, 2009. Dac '09. 46th ACM/IEEE
892:. VLSI Electronics Microstructure Science. Vol. 20.
266:
1150:
1148:
952:
A Method for
Gridless Routing of Printed Circuit Boards
1329:
http://www.eecs.northwestern.edu/~haizhou/357/lec6.pdf
335:
Many routers execute the following overall algorithm:
1290:
1113:
452:"The Rectilinear Steiner Tree Problem is NP-Complete"
359:
Select a sequence in which the nets are to be routed.
1215:
Proceedings of the 16th Design
Automation Conference
1145:
1122:"A lifetime designing PCBs: From design to software"
347:For detailed routing, the most common technique is
1082:
665:. In Whitaker, Jerry C.; Dorf, Richard C. (eds.).
123:which try to find a solution that is good enough.
1234:"An iterative technique for printed wire routing"
1787:
885:
540:Printed Circuit Board Design with Microcomputers
881:
879:
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759:Proceedings. Vol. H47. pp. 1745–1478.
653:
651:
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545:Intertext Publications/Multiscience Press, Inc.
800:
798:
796:
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61:(ICs). It builds on a preceding step, called
1244:
962:. Newtown, Tewkesbury, Gloucestershire, UK:
874:
642:
532:
530:
528:
526:
524:
449:
1238:Proceedings 11th Design Automation Workshop
1202:
1188:
791:
722:"A shortest path algorithm for grid graphs"
713:
573:
99:. The simplest routing problem, called the
1361:
1347:
1225:
942:
744:
1010:
835:
769:
521:
488:
922:
808:Electronic Materials Handbook: Packaging
619:IRE Transactions on Electronic Computers
142:
1533:Application-specific integrated circuit
1368:
1261:IBM Journal of Research and Development
1250:
751:Mikami, Koichi; Tabuchi, Kinya (1968).
719:
609:
579:
491:"Dogleg Channel Routing is NP-Complete"
293:(Anthony Blake's open-source router in
14:
1788:
1208:
804:
1342:
1299:. Vol. II. Boca Raton, FL, USA:
1231:
1119:
1046:Graph Theory Based Routing Algorithms
536:
450:Garey, M. R.; Johnson, D. S. (1977).
378:For each of several iterative passes:
1468:Three-dimensional integrated circuit
1016:
1154:
615:
456:SIAM Journal on Applied Mathematics
330:
160:The main types of autorouters are:
138:
24:
1480:Erasable programmable logic device
1284:
1042:
426:Auto polarity (differential pairs)
34:. For other kinds of routing, see
27:Stage of electronic circuit design
25:
1807:
1515:Complex programmable logic device
1322:
582:"PCB routers and routing methods"
580:Ritchey, Lee W. (December 1999).
720:Hadlock, Frank O. (1977-12-01).
591:(February 1999). Speeding Edge.
283:-based autorouter, also used in
1527:Field-programmable object array
1463:Mixed-signal integrated circuit
1134:from the original on 2018-10-21
1102:from the original on 2018-10-21
1025:from the original on 2018-10-22
999:from the original on 2018-10-22
931:from the original on 2021-05-18
702:from the original on 2017-09-25
675:Taylor & Francis Group, LLC
598:from the original on 2018-10-22
307:(the topological pre-router in
889:VLSI and Computer Architecture
482:
443:
13:
1:
1653:Hardware description language
1521:Field-programmable gate array
1120:Pfeil, Charles (2017-11-02).
923:McLellan, Paul (2012-04-23).
543:(1 ed.). New York, USA:
489:Szymanski, Thomas G. (1985).
436:
250:) (gridless since version 10)
53:, is a step in the design of
1017:Webb, Darrell (2012-12-20).
406:Electronic design automation
32:electronic design automation
7:
1665:Formal equivalence checking
1054:Western Michigan University
805:Minges, Merrill L. (1989).
537:Byers, T. J. (1991-08-01).
399:
10:
1812:
1685:Hierarchical state machine
1643:Transaction-level modeling
1168:Ernst-Abbe-Hochschule Jena
925:"Channel Routing Memories"
362:Route each net in sequence
222:Graph theory-based router
29:
1762:
1695:
1611:
1586:Digital signal processing
1571:Logic in computer science
1548:
1497:Programmable logic device
1457:Hybrid integrated circuit
1376:
1098:(in German). 1992-03-13.
858:10.1109/TCAD.1985.1270117
507:10.1109/tcad.1985.1270096
431:Auto crossover (Ethernet)
416:Integrated circuit design
49:, commonly called simply
1598:Switching circuit theory
1503:Programmable Array Logic
1491:Programmable logic array
972:10.1109/DAC.1985.1585990
667:The Electronics Handbook
628:10.1109/TEC.1961.5219222
549:McGraw-Hill Book Company
36:routing (disambiguation)
1648:Register-transfer level
1251:Linsker, Ralph (1984).
209:Spine and stitch router
1539:Tensor Processing Unit
1217:. San Diego, CA, USA:
738:10.1002/net.3230070404
622:. EC-10 (3): 346–365.
269:-based autorouter for
149:
55:printed circuit boards
1754:Electronic literature
1708:Hardware acceleration
1576:Computer architecture
1474:Emitter-coupled logic
1411:Printed circuit board
1232:Rubin, Frank (1974).
1209:Soukup, Jirí (1979).
1170:(EAH). Archived from
1043:Wu, Bo (April 1992).
784:10.1145/800260.809014
374:following algorithm:
185:Mikami–Tahuchi router
146:
129:printed circuit board
127:applications such as
1680:Finite-state machine
1658:High-level synthesis
1593:Circuit minimization
1305:Taylor & Francis
155:design rule checking
1727:Digital photography
1509:Generic Array Logic
1431:Combinational logic
1406:Printed electronics
1370:Digital electronics
1274:10.1147/rd.285.0613
1221:. pp. 481–489.
551:. pp. 99–101.
255:Topological router
59:integrated circuits
1675:Asynchronous logic
1451:Integrated circuit
1416:Electronic circuit
1240:. pp. 308–13.
966:pp. 509–515.
589:PC Design Magazine
349:rip-up and reroute
248:Allegro PCB Router
150:
1783:
1782:
1732:Digital telephone
1703:Computer hardware
1670:Synchronous logic
1314:978-0-8493-3096-4
1155:Redlich, Detlef.
822:978-0-87170-285-2
813:ASM International
778:. pp. 1–24.
684:978-0-8493-1889-4
558:978-0-07-009558-8
411:Design flow (EDA)
226:Bloodhound router
181:Line-probe router
133:multi-chip module
43:electronic design
16:(Redirected from
1803:
1436:Sequential logic
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1164:Schaltungsdesign
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1064:. Archived from
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964:Racal-Redac Ltd.
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903:978-1-48321784-0
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677:. p. 1266.
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353:rip-up and retry
331:How routers work
287:'s Delta Design)
259:FreeStyle Router
214:Gridless router
202:Switchbox router
188:Hightower router
139:Types of routers
21:
1811:
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1626:Place and route
1621:Logic synthesis
1607:
1603:Gate equivalent
1566:Logic synthesis
1561:Boolean algebra
1544:
1486:Macrocell array
1446:Boolean circuit
1372:
1367:
1325:
1315:
1287:
1285:Further reading
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1281:
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1211:"Global Router"
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811:. Vol. 1.
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468:10.1137/0132071
448:
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421:Place and route
402:
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141:
109:channel routing
90:antenna effects
71:place and route
39:
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1323:External links
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1268:(5): 613–624.
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894:Academic Press
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852:(3): 203–219.
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732:(4): 323–334.
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669:(2 ed.).
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197:Channel router
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193:Pattern router
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172:Hadlock router
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1763:Design issues
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1737:Digital video
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18:Routing (EDA)
1696:Applications
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1179:. Retrieved
1172:the original
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1136:. Retrieved
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1084:
1073:. Retrieved
1066:the original
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1001:. Retrieved
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501:(1): 31–41.
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206:River router
175:Flood router
159:
151:
125:
115:, number of
101:Steiner tree
94:
75:
67:design rules
50:
47:wire routing
46:
40:
1796:Autorouters
1426:Memory cell
1127:EDN Network
319:and higher)
234:Racal-Redac
218:Area router
165:Maze router
105:NP-complete
97:intractable
57:(PCBs) and
1775:Runt pulse
1747:television
1441:Logic gate
1386:Transistor
1378:Components
1219:IEEE Press
1181:2018-10-20
1138:2018-10-20
1106:2018-10-20
1075:2018-10-22
1052:(Thesis).
1029:2018-10-22
1003:2018-10-22
935:2022-01-01
909:2018-10-22
828:2017-09-27
706:2017-09-25
693:2004057106
602:2018-10-22
437:References
299:gEDA suite
291:Toporouter
169:Lee router
121:heuristics
1631:Placement
1421:Flip-flop
1401:Capacitor
1301:CRC Press
990:0738-100X
776:ACM Press
671:CRC Press
476:0036-1399
317:EAGLE 7.0
305:TopRouter
113:crosstalk
86:crosstalk
63:placement
1790:Category
1396:Inductor
1391:Resistor
1132:Archived
1100:Archived
1023:Archived
994:Archived
929:Archived
866:17065773
726:Networks
697:Archived
636:40700386
593:Archived
567:91-72187
515:17511882
400:See also
313:Autodesk
263:SpeedWay
244:Specctra
1636:Routing
1470:(3D IC)
1293:Routing
1062:3357923
309:CadSoft
297:of the
281:Windows
230:CADSTAR
51:routing
1613:Design
1549:Theory
1535:(ASIC)
1529:(FPOA)
1523:(FPGA)
1517:(CPLD)
1482:(EPLD)
1311:
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978:
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366:again.
285:Eremex
1720:radio
1541:(TPU)
1511:(GAL)
1505:(PAL)
1499:(PLD)
1493:(PLA)
1476:(ECL)
1459:(HIC)
1256:(PDF)
1175:(PDF)
1160:(PDF)
1069:(PDF)
1058:S2CID
1050:(PDF)
997:(PDF)
956:(PDF)
862:S2CID
757:IFIPS
700:(PDF)
663:(PDF)
632:S2CID
596:(PDF)
585:(PDF)
511:S2CID
277:TopoR
271:P-CAD
261:(aka
246:(aka
238:Zuken
148:used.
1453:(IC)
1309:ISBN
986:ISSN
976:ISBN
898:ISBN
817:ISBN
689:LCCN
679:ISBN
563:LCCN
553:ISBN
472:ISSN
351:aka
265:, a
117:vias
78:pins
1295:".
1270:doi
968:doi
854:doi
780:doi
734:doi
624:doi
503:doi
464:doi
315:'s
295:PCB
279:(a
267:DOS
232:by
131:or
82:net
41:In
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