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168:. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package.
211:
mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example
445:
An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat
532:
It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square
889:
371:
772:
558:
537:. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as
788:
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922:
326:. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a
573:
The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1
248:
faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the
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476:. Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.
68:
1343:
It is relatively common to find packages that contain other components than their designated ones, such as diodes or
1286:
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A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on
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42:
121:
75:
46:
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The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by
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Proceedings of the
International Conference on Nano-electronics, Circuits & Communication Systems
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mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the
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300:. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some
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661:
1322:
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983:
687:"Intel Releases New Design for sub-$ 1,000 PCs". Philippine Daily Inquirer. April 24, 2000.
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276:
184:
818:
16:
Type of integrated circuit packaging with the pins mounted on the underside of the package
8:
1249:
972:
297:
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Plastic pin grid array (PPGA) packaging was used by Intel for late-model
Mendocino core
1276:
1266:
549:
A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in
388:
553:. The polymer stud grid array or plastic stud grid array was developed jointly by the
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183:. PGAs allow for more pins per integrated circuit than older packages, such as
134:
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Underside of an 80486 with lid removed shows die and wire bonded connections.
895:
614:
323:
204:
150:
789:"Molex Sockets for Servers, Desktops and Notebooks Earn Intel® Validation"
244:
pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the
129:
900:
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The staggered pin grid array (SPGA) is used by Intel processors based on
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Robert Bruce
Thompson; Barbara Fritchman Thompson (24 July 2003).
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The underside of a FC-PGA package (The die is on the other side.)
1080:
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A ceramic pin grid array (CPGA) is a type of packaging used by
1032:
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An example of a socket for a staggered pin grid array package
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An organic pin grid array (OPGA) is a type of connection for
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256:
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213:
195:
1008:
1002:
996:
516:
456:
410:
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722:
PC Hardware in a
Nutshell: A Desktop Quick Reference
712:
49:. Unsourced material may be challenged and removed.
513:used a partial SPGA layout on half the processor.
1356:
528:View of the socket 7 321-pin connectors of a CPU
358:133 MHz Pentium chip in a ceramic package
873:Ball Grid Arrays: the High-Pincount Workhorses
816:
133:The pin grid array at the bottom of prototype
916:
413:which make the requisite connections to the
1318:List of integrated circuit packaging types
930:
923:
909:
851:"SURFACE MOUNT NOMENCLATURE AND PACKAGING"
659:
330:substrate with pins arranged in an array.
283:; similar packages were also used by AMD.
109:Learn how and when to remove this message
890:Elektronik, Produktion & Prüftechnik
523:
515:
478:
455:
367:
231:
194:
140:
128:
120:
975:(SOD-123 / SOD-323 / SOD-523 / SOD-923)
653:
617:- chip packaging and package types list
555:Interuniversity Microelectronics Centre
145:The pin grid array on the bottom of an
125:Closeup of the pins of a pin grid array
1357:
835:"XSERIES 335 XEON DP-2.4G 512 MB"
402:is attached to a plate made out of an
904:
559:Laboratory for Production Technology
304:that use CPGA packaging are the AMD
275:in 2013. FC-PGA processors fit into
149:X4 9750 processor that uses the AMD
47:adding citations to reliable sources
18:
725:. O'Reilly Media, Inc. p. 44.
379:Demonstration of a PGA-ZIF socket (
346:microprocessor in a ceramic package
13:
868:Intel CPU Processor Identification
14:
1376:
875:, John Baliga, associate editor,
861:
817:Thomas, Andrew (August 4, 2010).
819:"What the Hell is… a flip-chip?"
496:
438:
422:
409:which is pierced by an array of
351:
335:
190:
23:
255:FC-PGA CPUs were introduced by
34:needs additional citations for
957:(DO-7 / DO-26 / DO-35 / DO-41)
781:
760:
739:
680:
1:
646:
491:
259:in 1999, for Coppermine core
1347:in transistor packages, etc.
1313:Integrated circuit packaging
660:Vijay Nath (24 March 2017).
252:or other cooling mechanism.
227:
166:integrated circuit packaging
7:
885:Spot on component packaging
878:Semiconductor International
596:
286:
10:
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577:mm, as opposed to the 1.27
451:
363:
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271:, and were produced until
179:method or inserted into a
171:PGAs are often mounted on
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1217:
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666:. Springer. p. 304.
1328:Surface-mount technology
837:. CNET. October 26, 2002
775:October 1, 2011, at the
551:surface-mount technology
1333:Through-hole technology
639:Zig-zag in-line package
568:
544:
963:(MELF / SOD-80 / LL34)
932:Semiconductor packages
633:Single in-line package
610:Centered square number
529:
521:
488:
465:
464:-400 in a PPGA packing
384:
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173:printed circuit boards
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1323:Printed circuit board
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459:
378:
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144:
132:
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1308:Electronic packaging
621:Dual in-line package
472:processors based on
277:zero insertion force
267:processors based on
185:dual in-line package
43:improve this article
747:"BGA socket/BGA 소켓"
429:The underside of a
389:integrated circuits
298:integrated circuits
281:motherboard sockets
220:Ryzen CPUs for the
1345:voltage regulators
530:
522:
489:
466:
385:
238:
201:
154:
139:
127:
1352:
1351:
1101:(Super-247) (SMT)
1095:(Super-220) (SMT)
969:(SMA / SMB / SMC)
732:978-0-596-55234-3
700:Missing or empty
673:978-981-10-2999-8
460:The topside of a
391:, and especially
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119:
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791:. Archived from
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487:in a PGA package
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58:"Pin grid array"
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627:Land grid array
604:Ball grid array
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539:microprocessors
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483:Underside of a
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342:A 1.2 GHz
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164:) is a type of
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1301:Related topics
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1167:TSSOP / HTSSOP
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862:External links
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433:-400 in a PPGA
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158:pin grid array
137:microprocessor
135:Motorola 68020
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1365:Chip carriers
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1089:(D3PAK) (SMT)
1088:
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1083:(D2PAK) (SMT)
1082:
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1077:(I2PAK) (SMT)
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795:on 2019-12-09
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497:Staggered pin
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191:Chip mounting
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99:December 2011
91:
88:
84:
81:
77:
74:
70:
67:
63:
60: –
59:
55:
54:Find sources:
48:
44:
38:
37:
32:This article
30:
26:
21:
20:
1292:WL-CSP / WLP
1239:
1162:TSOP / HTSOP
1071:(DPAK) (SMT)
1065:(IPAK) (SMT)
1059:(TH / Panel)
1053:(TH / Panel)
1047:(TH / Panel)
1041:(TH / Panel)
1029:(TH / Panel)
999:(TH / Panel)
888:
876:
841:December 30,
839:. Retrieved
825:December 30,
823:. Retrieved
797:. Retrieved
793:the original
783:
762:
751:. Retrieved
741:
721:
714:
682:
662:
655:
615:Chip carrier
572:
548:
531:
500:
467:
395:, where the
386:
317:
295:
254:
239:
205:wire bonding
202:
177:through hole
170:
161:
157:
155:
105:
96:
86:
79:
72:
65:
53:
41:Please help
36:verification
33:
1210:QUIP / QUIL
896:Terminology
887:, 08/1998,
770:(in German)
749:. Jsits.com
557:(IMEC) and
324:Socket AM2+
261:Pentium III
207:or through
151:AM2+ socket
1218:Grid array
1157:SOP / SSOP
1109:Single row
992:SOT / TSOT
881:, 9/1/1999
799:2016-03-15
753:2015-06-05
702:|url=
647:References
563:Siemens AG
492:Pin layout
474:Socket 370
320:Socket AM2
269:Socket 370
222:AM4 socket
175:using the
147:AMD Phenom
69:newspapers
1272:Flip Chip
1191:QIP / QIL
1152:SO / SOIC
1142:Flat Pack
1137:DIP / DIL
1116:SIP / SIL
984:3...5-pin
593:sockets.
485:Pentium 4
273:Socket G3
242:flip-chip
228:Flip chip
209:flip chip
1359:Category
1181:Quad row
1125:Dual row
773:Archived
693:cite web
597:See also
511:Socket 8
507:Socket 7
503:Socket 5
311:and the
306:Socket A
287:Material
250:heatsink
951:(DO-27)
939:Single
811:Sources
535:lattice
470:Celeron
462:Celeron
452:Plastic
431:Celeron
407:plastic
404:organic
397:silicon
381:AMD 754
364:Organic
328:ceramic
309:Athlons
292:Ceramic
265:Celeron
187:(DIP).
83:scholar
1099:TO-274
1093:TO-273
1087:TO-268
1081:TO-263
1075:TO-262
1069:TO-252
1063:TO-251
1057:TO-247
1051:TO-220
1045:TO-202
1039:TO-126
967:DO-214
961:DO-213
955:DO-204
949:DO-201
729:
670:
589:, and
579:
575:
415:socket
344:VIA C3
279:(ZIF)
181:socket
85:
78:
71:
64:
56:
1250:Wafer
1033:TO-92
1027:TO-66
1021:TO-39
1015:TO-18
941:diode
854:(PDF)
641:(ZIP)
635:(SIP)
629:(LGA)
623:(DIP)
606:(BGA)
446:sink.
313:Duron
257:Intel
218:Zen 3
214:Zen 2
90:JSTOR
76:books
1287:UICC
1230:eWLB
1196:PLCC
1147:MSOP
1035:(TH)
1023:(TH)
1017:(TH)
1011:(TH)
1009:TO-8
1005:(TH)
1003:TO-5
997:TO-3
843:2011
827:2011
767:link
727:ISBN
706:help
668:ISBN
569:rPGA
545:Stud
505:and
411:pins
393:CPUs
322:and
302:CPUs
263:and
216:and
62:news
1277:PoP
1267:CSP
1263:COG
1260:COF
1257:COB
1240:PGA
1235:LGA
1225:BGA
1206:QFP
1201:QFN
1187:LCC
1172:ZIP
1132:DFN
973:SOD
509:.
400:die
246:die
162:PGA
45:by
1361::
1282:QP
697::
695:}}
691:{{
591:G3
587:G2
585:,
583:G1
565:.
561:,
541:.
417:.
315:.
240:A
224:.
156:A
924:e
917:t
910:v
856:.
845:.
829:.
802:.
756:.
735:.
708:)
704:(
676:.
383:)
160:(
112:)
106:(
101:)
97:(
87:·
80:·
73:·
66:·
39:.
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
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