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Exclusive or
Modified state first, by invalidating all other cached copies. (If the cache line was Owned before, the invalidate response will indicate this, and the state will become Modified, so the obligation to eventually write the data back to memory is not forgotten.) It may also be discarded (changed to the Invalid state) at any time.
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While MOESI can quickly share dirty cache lines from cache, it may struggle to quickly share clean lines from cache. If a cache line is clean with respect to memory and in the shared state, then there is no obvious single candidate cache to respond to a read request, so it is normal to let the read
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If a processor wishes to write to an Owned cache line, it must notify the other processors which are sharing that cache line. The standard implementation simply tells them to invalidate their copies, moving its own copy to the
Modified state when this is complete, but alternatively it may use a
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when another processor tries to read it. Instead, the Owned state allows a processor to supply the modified data directly to the other processor. This is beneficial when the communication between two CPUs is significantly better than to main memory. An example would be multi-core CPUs with
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be dirty with respect to memory; if it is, one cache has a copy in the Owned state, and that cache is responsible for eventually updating main memory. If no cache holds the line in the Owned state, the memory copy is up to date. The cache line may not be written, but must be changed to the
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the line is modified (dirty) relative to main memory, and this cache has the exclusive responsibility for ensuring main memory is eventually updated. The cache line may be changed to the
Modified state after invalidating all shared copies, or changed to the Shared state by
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states, there is a fifth "Owned" state representing data that is both modified and shared. This avoids the need to write modified data back to main memory before sharing it. While the data must still be written back eventually, the write-back may be deferred .
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In order for this to be possible, direct cache-to-cache transfers of data must be possible, so a cache with the data in the modified state can supply that data to another reader without transferring it to memory.
454:, telling them to update their copies with the new contents. This is a partial write-through which does not go as far as main memory; the processor's own copy remains in the Owned state.
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This line is one of several copies in the system. This cache does not have permission to modify the copy. Unlike the MESI protocol, a shared cache line
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This cache has the only valid copy of the cache line, and has made changes to that copy. The cached copy may be further modified freely.
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This cache has the only copy of the line, but the line is clean (unmodified). It may be written to, changing to the
Modified state.
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protocol that encompasses all of the possible states commonly used in other protocols. In addition to the four common
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of read requests. Because these two variants are fully compatible, they may both be used in the same system based on
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426:(The order in which the states are normally listed serves only to make the acronym "MOESI" pronounceable.)
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This line is one of several copies in the system. This cache does not have permission to modify the copy
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For any given pair of caches, the permitted states of a given cache line are as follows:
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like the cache's estimate of the number of active readers of this cache line.
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This block is not valid; it must be fetched to satisfy any attempted access.
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lock; one broadcast write is less communication than separate replies to a
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In computing, MOESI ("Modified Owned
Exclusive Shared Invalid") is a full
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request with data, to ensure the stale copy in main memory is not used.
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523:"AMD64 Architecture Programmer's Manual Vol 2 'System Programming'"
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request be filled from memory. (This is solved by the
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This protocol, a more elaborate version of the simpler
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there are multiple active readers of e.g. a heavily
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46:Architecture Programmer's Manual Vol. 2
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21:Cache coherency protocols (examples)
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528:. pp. 169–172. Archived from
84:to main memory. Owned cache lines
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457:The latter reduces cache traffic
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19:(For a detailed description see
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82:writing the modifications back
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60:is in one of five states:
16:Cache coherence protocol
452:write-through policy
438:per-core L2 caches.
51:System Programming
566:Cache (computing)
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535:on June 19, 2017
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444:MESIF protocol
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32:MESI protocol
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537:. Retrieved
530:the original
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488:MSI protocol
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435:main memory
555:Categories
539:August 28,
509:References
471:heuristics
58:cache line
463:contended
97:Exclusive
477:See also
64:Modified
118:Invalid
56:, each
105:Shared
533:(PDF)
526:(PDF)
90:snoop
72:Owned
54:'
48:'
44:AMD64
541:2015
86:must
110:may
77:but
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459:if
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419:Y
409:Y
399:Y
389:Y
379:Y
364:Y
354:Y
344:N
334:Y
324:N
309:Y
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289:N
279:N
269:N
254:Y
244:Y
234:N
224:N
214:N
199:Y
189:N
179:N
169:N
159:N
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