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179:. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package.
222:
mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example
456:
An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat
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It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square
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382:
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548:. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as
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337:. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a
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The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1
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faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the
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487:. Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.
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It is relatively common to find packages that contain other components than their designated ones, such as diodes or
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A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on
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The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by
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Proceedings of the
International Conference on Nano-electronics, Circuits & Communication Systems
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mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the
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311:. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some
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698:"Intel Releases New Design for sub-$ 1,000 PCs". Philippine Daily Inquirer. April 24, 2000.
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27:
Type of integrated circuit packaging with the pins mounted on the underside of the package
8:
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Plastic pin grid array (PPGA) packaging was used by Intel for late-model
Mendocino core
1287:
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A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in
399:
564:. The polymer stud grid array or plastic stud grid array was developed jointly by the
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194:. PGAs allow for more pins per integrated circuit than older packages, such as
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Underside of an 80486 with lid removed shows die and wire bonded connections.
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334:
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800:"Molex Sockets for Servers, Desktops and Notebooks Earn Intel® Validation"
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pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the
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The staggered pin grid array (SPGA) is used by Intel processors based on
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Robert Bruce
Thompson; Barbara Fritchman Thompson (24 July 2003).
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The underside of a FC-PGA package (The die is on the other side.)
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A ceramic pin grid array (CPGA) is a type of packaging used by
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An example of a socket for a staggered pin grid array package
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An organic pin grid array (OPGA) is a type of connection for
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1007:
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733:
PC Hardware in a
Nutshell: A Desktop Quick Reference
723:
60:. Unsourced material may be challenged and removed.
524:used a partial SPGA layout on half the processor.
1367:
539:View of the socket 7 321-pin connectors of a CPU
369:133 MHz Pentium chip in a ceramic package
884:Ball Grid Arrays: the High-Pincount Workhorses
827:
144:The pin grid array at the bottom of prototype
927:
424:which make the requisite connections to the
1329:List of integrated circuit packaging types
941:
934:
920:
862:"SURFACE MOUNT NOMENCLATURE AND PACKAGING"
670:
341:substrate with pins arranged in an array.
294:; similar packages were also used by AMD.
120:Learn how and when to remove this message
901:Elektronik, Produktion & Prüftechnik
534:
526:
489:
466:
378:
242:
205:
151:
139:
131:
986:(SOD-123 / SOD-323 / SOD-523 / SOD-923)
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628:- chip packaging and package types list
566:Interuniversity Microelectronics Centre
156:The pin grid array on the bottom of an
136:Closeup of the pins of a pin grid array
14:
1368:
846:"XSERIES 335 XEON DP-2.4G 512 MB"
413:is attached to a plate made out of an
915:
570:Laboratory for Production Technology
315:that use CPGA packaging are the AMD
286:in 2013. FC-PGA processors fit into
160:X4 9750 processor that uses the AMD
58:adding citations to reliable sources
29:
736:. O'Reilly Media, Inc. p. 44.
390:Demonstration of a PGA-ZIF socket (
357:microprocessor in a ceramic package
24:
879:Intel CPU Processor Identification
25:
1387:
886:, John Baliga, associate editor,
872:
828:Thomas, Andrew (August 4, 2010).
830:"What the Hell is… a flip-chip?"
507:
449:
433:
420:which is pierced by an array of
362:
346:
201:
34:
266:FC-PGA CPUs were introduced by
45:needs additional citations for
968:(DO-7 / DO-26 / DO-35 / DO-41)
792:
771:
750:
691:
13:
1:
657:
502:
270:in 1999, for Coppermine core
1358:in transistor packages, etc.
1324:Integrated circuit packaging
671:Vijay Nath (24 March 2017).
263:or other cooling mechanism.
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177:integrated circuit packaging
7:
896:Spot on component packaging
889:Semiconductor International
607:
297:
10:
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588:mm, as opposed to the 1.27
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282:, and were produced until
190:method or inserted into a
182:PGAs are often mounted on
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677:. Springer. p. 304.
1339:Surface-mount technology
848:. CNET. October 26, 2002
786:October 1, 2011, at the
562:surface-mount technology
1344:Through-hole technology
650:Zig-zag in-line package
579:
555:
974:(MELF / SOD-80 / LL34)
943:Semiconductor packages
644:Single in-line package
621:Centered square number
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532:
499:
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475:-400 in a PPGA packing
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184:printed circuit boards
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18:Ceramic Pin Grid Array
1334:Printed circuit board
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1319:Electronic packaging
632:Dual in-line package
483:processors based on
288:zero insertion force
278:processors based on
196:dual in-line package
54:improve this article
758:"BGA socket/BGA 소켓"
440:The underside of a
400:integrated circuits
309:integrated circuits
292:motherboard sockets
231:Ryzen CPUs for the
1356:voltage regulators
541:
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477:
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249:
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1362:
1112:(Super-247) (SMT)
1106:(Super-220) (SMT)
980:(SMA / SMB / SMC)
743:978-0-596-55234-3
711:Missing or empty
684:978-981-10-2999-8
471:The topside of a
402:, and especially
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16:(Redirected from
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802:. Archived from
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498:in a PGA package
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69:"Pin grid array"
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638:Land grid array
615:Ball grid array
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494:Underside of a
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353:A 1.2 GHz
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1312:Related topics
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1178:TSSOP / HTSSOP
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873:External links
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832:. The Register
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444:-400 in a PPGA
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169:pin grid array
148:microprocessor
146:Motorola 68020
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1100:(D3PAK) (SMT)
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1094:(D2PAK) (SMT)
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1088:(I2PAK) (SMT)
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806:on 2019-12-09
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508:Staggered pin
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202:Chip mounting
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110:December 2011
102:
99:
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92:
88:
85:
81:
78:
74:
71: –
70:
66:
65:Find sources:
59:
55:
49:
48:
43:This article
41:
37:
32:
31:
19:
1303:WL-CSP / WLP
1250:
1173:TSOP / HTSOP
1082:(DPAK) (SMT)
1076:(IPAK) (SMT)
1070:(TH / Panel)
1064:(TH / Panel)
1058:(TH / Panel)
1052:(TH / Panel)
1040:(TH / Panel)
1010:(TH / Panel)
899:
887:
852:December 30,
850:. Retrieved
836:December 30,
834:. Retrieved
808:. Retrieved
804:the original
794:
773:
762:. Retrieved
752:
732:
725:
693:
673:
666:
626:Chip carrier
583:
559:
542:
511:
478:
406:, where the
397:
328:
306:
265:
250:
216:wire bonding
213:
188:through hole
181:
172:
168:
166:
116:
107:
97:
90:
83:
76:
64:
52:Please help
47:verification
44:
1221:QUIP / QUIL
907:Terminology
898:, 08/1998,
781:(in German)
760:. Jsits.com
568:(IMEC) and
335:Socket AM2+
272:Pentium III
218:or through
162:AM2+ socket
1229:Grid array
1168:SOP / SSOP
1120:Single row
1003:SOT / TSOT
892:, 9/1/1999
810:2016-03-15
764:2015-06-05
713:|url=
658:References
574:Siemens AG
503:Pin layout
485:Socket 370
331:Socket AM2
280:Socket 370
233:AM4 socket
186:using the
158:AMD Phenom
80:newspapers
1283:Flip Chip
1202:QIP / QIL
1163:SO / SOIC
1153:Flat Pack
1148:DIP / DIL
1127:SIP / SIL
995:3...5-pin
604:sockets.
496:Pentium 4
284:Socket G3
253:flip-chip
239:Flip chip
220:flip chip
1370:Category
1192:Quad row
1136:Dual row
784:Archived
704:cite web
608:See also
522:Socket 8
518:Socket 7
514:Socket 5
322:and the
317:Socket A
298:Material
261:heatsink
962:(DO-27)
950:Single
822:Sources
546:lattice
481:Celeron
473:Celeron
463:Plastic
442:Celeron
418:plastic
415:organic
408:silicon
392:AMD 754
375:Organic
339:ceramic
320:Athlons
303:Ceramic
276:Celeron
198:(DIP).
94:scholar
1110:TO-274
1104:TO-273
1098:TO-268
1092:TO-263
1086:TO-262
1080:TO-252
1074:TO-251
1068:TO-247
1062:TO-220
1056:TO-202
1050:TO-126
978:DO-214
972:DO-213
966:DO-204
960:DO-201
740:
681:
600:, and
590:
586:
426:socket
355:VIA C3
290:(ZIF)
192:socket
96:
89:
82:
75:
67:
1261:Wafer
1044:TO-92
1038:TO-66
1032:TO-39
1026:TO-18
952:diode
865:(PDF)
652:(ZIP)
646:(SIP)
640:(LGA)
634:(DIP)
617:(BGA)
457:sink.
324:Duron
268:Intel
229:Zen 3
225:Zen 2
101:JSTOR
87:books
1298:UICC
1241:eWLB
1207:PLCC
1158:MSOP
1046:(TH)
1034:(TH)
1028:(TH)
1022:(TH)
1020:TO-8
1016:(TH)
1014:TO-5
1008:TO-3
854:2011
838:2011
778:link
738:ISBN
717:help
679:ISBN
580:rPGA
556:Stud
516:and
422:pins
404:CPUs
333:and
313:CPUs
274:and
227:and
73:news
1288:PoP
1278:CSP
1274:COG
1271:COF
1268:COB
1251:PGA
1246:LGA
1236:BGA
1217:QFP
1212:QFN
1198:LCC
1183:ZIP
1143:DFN
984:SOD
520:.
411:die
257:die
173:PGA
56:by
1372::
1293:QP
708::
706:}}
702:{{
602:G3
598:G2
596:,
594:G1
576:.
572:,
552:.
428:.
326:.
251:A
235:.
167:A
935:e
928:t
921:v
867:.
856:.
840:.
813:.
767:.
746:.
719:)
715:(
687:.
394:)
171:(
123:)
117:(
112:)
108:(
98:·
91:·
84:·
77:·
50:.
20:)
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.
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