168:
66:
398:
25:
277:
would have an even larger loss. To ameliorate the loss, some machines implement branch target prediction: given the address of a branch, they predict the target of that branch. A refinement of the idea predicts the start of a sequential run of instructions given the address of the start of the previous sequential run of instructions.
276:
In machines where this recurrence takes two cycles, the machine loses one full cycle of fetch after every predicted taken branch. As predicted branches happen every 10 instructions or so, this can force a substantial drop in fetch bandwidth. Some machines with longer instruction cache latencies
294:
As the predictor RAM can be 5–10% of the size of the instruction cache, the fetch happens much faster than the instruction cache fetch, and so this recurrence is much faster. If it were not fast enough, it could be parallelized, by predicting target addresses of target branches.
130:
102:
83:
38:
439:
322:
316:
109:
227:
is the part of a processor that predicts the target, i.e. the address of the instruction that is executed next, of a taken
253:
latency grows longer and the fetch width grows wider, branch target extraction becomes a bottleneck. The recurrence is:
116:
310:
206:
149:
52:
98:
463:
458:
87:
44:
432:
177:
123:
413:
304:
232:
76:
359:
242:
which attempts to guess whether a conditional branch will be taken or not-taken (i.e., binary).
425:
287:
Fetch the prediction for the addresses of the targets of branches in that run of instructions
220:
8:
184:
Please help update this article to reflect recent events or newly available information.
246:
228:
372:
269:
250:
239:
405:
409:
346:
The
Behavior of Efficient Virtual Machine Interpreters on Modern Architectures
452:
368:
65:
397:
290:
Select the address corresponding to the branch predicted taken
260:
Instructions in block are scanned to identify branches
235:
is computed by the execution unit of the processor.
90:. Unsourced material may be challenged and removed.
373:"The microarchitecture of Intel, AMD and VIA CPUs"
284:Hash the address of the first instruction in a run
231:or an unconditional branch instruction before the
180:may be compromised due to out-of-date information
450:
280:This predictor reduces the recurrence above to:
257:Instruction cache fetches block of instructions
433:
335:
238:Branch target prediction is not the same as
53:Learn how and when to remove these messages
440:
426:
263:First predicted taken branch is identified
343:
207:Learn how and when to remove this message
150:Learn how and when to remove this message
323:Single thread indirect branch predictor
451:
317:Indirect branch restricted speculation
392:
161:
88:adding citations to reliable sources
59:
18:
338:Accurate Indirect Branch Prediction
13:
329:
311:Indirect branch prediction barrier
14:
475:
352:
266:Target of that branch is computed
34:This article has multiple issues.
396:
233:target of the branch instruction
166:
64:
23:
367:
75:needs additional citations for
42:or discuss these issues on the
1:
412:. You can help Knowledge by
16:Part of a computer processor
7:
298:
10:
480:
391:
272:restarts at branch target
99:"Branch target predictor"
336:Driesen; Hölzle (1992),
360:"Branch Target Buffers"
305:Indirect branch control
225:branch target predictor
464:Computer science stubs
459:Instruction processing
221:computer architecture
344:Ertl; Gregg (2001),
84:improve this article
247:parallel processor
229:conditional branch
421:
420:
270:Instruction fetch
251:instruction cache
240:branch prediction
217:
216:
209:
199:
198:
160:
159:
152:
134:
57:
471:
442:
435:
428:
406:computer science
400:
393:
385:
383:
382:
377:
363:
348:
340:
249:designs, as the
212:
205:
194:
191:
185:
178:factual accuracy
170:
169:
162:
155:
148:
144:
141:
135:
133:
92:
68:
60:
49:
27:
26:
19:
479:
478:
474:
473:
472:
470:
469:
468:
449:
448:
447:
446:
389:
380:
378:
375:
358:
355:
332:
330:Further reading
301:
213:
202:
201:
200:
195:
189:
186:
183:
175:This article's
171:
167:
156:
145:
139:
136:
93:
91:
81:
69:
28:
24:
17:
12:
11:
5:
477:
467:
466:
461:
445:
444:
437:
430:
422:
419:
418:
401:
387:
386:
365:
354:
353:External links
351:
350:
349:
341:
331:
328:
327:
326:
320:
314:
308:
300:
297:
292:
291:
288:
285:
274:
273:
267:
264:
261:
258:
215:
214:
197:
196:
174:
172:
165:
158:
157:
72:
70:
63:
58:
32:
31:
29:
22:
15:
9:
6:
4:
3:
2:
476:
465:
462:
460:
457:
456:
454:
443:
438:
436:
431:
429:
424:
423:
417:
415:
411:
408:article is a
407:
402:
399:
395:
394:
390:
374:
370:
366:
361:
357:
356:
347:
342:
339:
334:
333:
324:
321:
318:
315:
312:
309:
306:
303:
302:
296:
289:
286:
283:
282:
281:
278:
271:
268:
265:
262:
259:
256:
255:
254:
252:
248:
243:
241:
236:
234:
230:
226:
222:
211:
208:
193:
181:
179:
173:
164:
163:
154:
151:
143:
132:
129:
125:
122:
118:
115:
111:
108:
104:
101: –
100:
96:
95:Find sources:
89:
85:
79:
78:
73:This article
71:
67:
62:
61:
56:
54:
47:
46:
41:
40:
35:
30:
21:
20:
414:expanding it
403:
388:
379:. Retrieved
345:
337:
293:
279:
275:
244:
237:
224:
218:
203:
187:
176:
146:
140:October 2007
137:
127:
120:
113:
106:
94:
82:Please help
77:verification
74:
50:
43:
37:
36:Please help
33:
453:Categories
381:2017-08-09
369:Fog, Agner
190:March 2017
110:newspapers
39:improve it
45:talk page
299:See also
245:In more
364:(EE461)
325:(STIBP)
124:scholar
319:(IBRS)
313:(IBPB)
126:
119:
112:
105:
97:
404:This
376:(PDF)
307:(IBC)
131:JSTOR
117:books
410:stub
223:, a
103:news
219:In
86:by
455::
371:.
48:.
441:e
434:t
427:v
416:.
384:.
362:.
210:)
204:(
192:)
188:(
182:.
153:)
147:(
142:)
138:(
128:·
121:·
114:·
107:·
80:.
55:)
51:(
Text is available under the Creative Commons Attribution-ShareAlike License. Additional terms may apply.