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Dual-ported video RAM

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377:, meaning that the act of reading a row also causes the data in it to be erased. To make the data permanent, any reading has to be followed by the DRAM writing the same data back to that row. To accomplish this, separate latches for the entire row have to be included, and the data is written back to the row while the CPU is reading out the requested byte. When one considers the process as a whole, this means the DRAM is repeatedly reading entire rows of data, selecting a single byte from that data and discarding the rest, and then writing it all back again. 179: 77: 36: 270: 258:(VDC), which sends a timing signal to the memory and receives data in the correct sequence as it draws the screen. Because the CPU and VDC access the memory simultaneously on different ports, dual-ported RAM does not require the CPU to pause while the VDC uses memory, thereby eliminating the associated 294:
input. To work with such a display it is extremely important that the video hardware output a very accurately timed signal. At the speeds that contemporary memory worked at, reading data to feed to the video hardware used up much of the possible performance of the memory devices. This conflicted with
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VRAM operates by not discarding the excess bits in the row. Instead, the data read into the row storage is also sent to a second set of latches and an associated bit shifter. From that point, the data can be read out a bit at a time by triggering the shifter, and doing so only requires a single pin.
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system, which set a new standard for graphics displays. Prior to the development of VRAM, dual-ported memory was quite expensive, limiting higher resolution bitmapped graphics to high-end workstations. VRAM improved the overall framebuffer throughput, allowing low cost, high-resolution, high-speed,
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Two general solutions were used to avoid timing issues. For higher-priced systems, the video systems had their own dedicated memory and used a separate system for the CPU to store data into it. This eliminated any possibility of contention for memory, but at the cost of requiring separate memory in
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Dual-ported RAM was common from the mid-1980s into the mid-1990s. After that date, new forms of high-performance memory began to be used that eventually replaced dual-ported designs. As these other forms of memory are also known as video memory, and thus VRAM, it sometimes confused with this older
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Such operation is described in the paper "All points addressable raster display memory" by R. Matick, D. Ling, S. Gupta, and F. Dill, IBM Journal of R&D, Vol 28, No. 4, July 1984, pp. 379–393. To use the video port, the controller first uses the DRAM port to select the row of the memory array
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technologies gradually became affordable, dense, and fast enough to displace VRAM, even though it is only single-ported and more overhead is required. Nevertheless, many of the VRAM concepts of internal, on-chip buffering and organization have been used and improved in modern graphics adapters.
385:, meaning that the CPU and graphics still have to interleave their accesses to the chip, but as a whole row of data is read out to the graphics driver, and that row might represent multiple scan lines on the screen, the number of times it has to interrupt the CPU can be greatly reduced. 405:, in strict address order, from the shift register to the video port. For simplicity, the graphics adapter is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display. 311:, was to use a single shared bank of memory and allow the video hardware to control access to memory, pausing the CPU when needed. This may lead to slower computing performance as the CPU is repeatedly put into these " 253:
Dual-ported RAM allows the CPU to read and write data to memory as if it were a conventional DRAM chip, while adding a second port that reads out data in a serial fashion. This makes it easy to interface with a
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in 1980, with a patent issued in 1985 (US Patent 4,541,075). The first commercial use of VRAM was in a high-resolution graphics adapter introduced in 1986 by IBM for its
322:(GUIs) that required high resolution and high overall performance, made the performance of the video system an increasingly difficult problem. Complex systems like the 329:
The solution was to use memory that could be access by the CPU and video hardware at the same time. It was invented by F. Dill, D. Ling and R. Matick at
362:. To read a byte for the CPU, the DRAM decodes the provided address into a series of eight cells, reads the entire row containing those cells, and 858: 315:", but it had the advantage of being less expensive and allowing the CPU to more rapidly update the display and thus provide more interactivity. 397:. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the 822: 17: 307:
that limited the speed that changes to the screen could be made, making interactive graphics difficult. The other solution, used by most
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emerged to carefully control access to memory and reduce contention, but while these reduced the problem they did not eliminate it.
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By the early 1980s, the introduction of much higher-resolution monitors that demanded larger framebuffers, and the newly introduced
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color graphics. Modern GUI-based operating systems benefitted from this and thus it provided a key ingredient for proliferation of
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Through the 1990s, many graphic subsystems used VRAM, with the number of megabits touted as a selling point. In the late 1990s,
94: 49: 120: 496: 127: 214: 160: 63: 299:(CPU) to write data to memory for the video system to read, as both could not use the same memory at the same time. 868: 109: 539: 98: 863: 688: 548: 358:. In typical use, a CPU accessing a DRAM will ask for a small amount of data at a time, possibly a single 427: 55: 339: 319: 255: 134: 363: 323: 296: 87: 817: 853: 640: 801: 832: 8: 192:
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an era when memory was very expensive. It also almost always communicated over a slow
401:(SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next 402: 624: 291: 235: 451: 394: 475: 847: 778: 693: 525: 389:
that is to be displayed. The VRAM then copies that entire row to an internal
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Dynamic RAM is internally arranged in an array of rows and columns of
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or a simple conversion of a television that accepted
370:. At the time, rows were commonly 1,024 cells wide. 286:to store video data to be output to a conventional 101:. Unsourced material may be challenged and removed. 242:(DRAM), which was once commonly used to store the 845: 533: 366:the requested data so it can be read on the 64:Learn how and when to remove these messages 540: 526: 342:(GUIs) throughout the world at that time. 262:and improving overall system performance. 215:Learn how and when to remove this message 161:Learn how and when to remove this message 268: 14: 859:Computer-related introductions in 1980 846: 498:SM55161A 262144×16 bit VRAM data sheet 521: 172: 99:adding citations to reliable sources 70: 29: 24: 27:Dual-ported variant of dynamic RAM 25: 880: 408: 381:VRAM generally does not have two 45:This article has multiple issues. 177: 75: 34: 86:needs additional citations for 53:or discuss these issues on the 489: 468: 440: 345: 13: 1: 461: 549:Dynamic random-access memory 18:Video RAM (dual-ported DRAM) 7: 446:And in some early systems, 421: 10: 885: 428:Video random-access memory 277: 810: 777: 749: 681: 577: 556: 340:graphical user interfaces 320:graphical user interfaces 186:This article needs to be 433: 273:Samsung Electronics VRAM 256:video display controller 869:20th-century inventions 297:central processing unit 110:"Dual-ported video RAM" 504:, Austin Semiconductor 274: 282:Early computers used 272: 228:Dual-ported video RAM 95:improve this article 864:American inventions 673:Hybrid Memory Cube 275: 841: 840: 373:DRAM devices are 295:the need for the 248:graphics adapters 225: 224: 217: 207: 206: 171: 170: 163: 145: 68: 16:(Redirected from 876: 833:Transistor count 542: 535: 528: 519: 518: 512: 511: 510: 509: 503: 493: 487: 486: 485: 484: 477:Patent US4541075 472: 455: 444: 415:synchronous DRAM 266:form of memory. 220: 213: 202: 199: 193: 181: 180: 173: 166: 159: 155: 152: 146: 144: 103: 79: 71: 60: 38: 37: 30: 21: 884: 883: 879: 878: 877: 875: 874: 873: 844: 843: 842: 837: 806: 773: 745: 677: 625:Fast Cycle DRAM 573: 552: 546: 516: 515: 507: 505: 501: 495: 494: 490: 482: 480: 474: 473: 469: 464: 459: 458: 452:shift registers 445: 441: 436: 424: 411: 348: 292:composite video 280: 221: 210: 209: 208: 203: 197: 194: 191: 182: 178: 167: 156: 150: 147: 104: 102: 92: 80: 39: 35: 28: 23: 22: 15: 12: 11: 5: 882: 872: 871: 866: 861: 856: 839: 838: 836: 835: 830: 825: 823:SDRAM timeline 820: 814: 812: 808: 807: 805: 804: 799: 794: 789: 783: 781: 779:Memory modules 775: 774: 772: 771: 766: 761: 755: 753: 747: 746: 744: 743: 742: 741: 736: 731: 726: 721: 716: 711: 701: 696: 691: 685: 683: 679: 678: 676: 675: 670: 669: 668: 663: 658: 653: 648: 638: 633: 628: 622: 616: 615: 614: 609: 604: 599: 589: 583: 581: 575: 574: 572: 571: 566: 560: 558: 554: 553: 545: 544: 537: 530: 522: 514: 513: 488: 466: 465: 463: 460: 457: 456: 438: 437: 435: 432: 431: 430: 423: 420: 410: 409:Shift to SDRAM 407: 395:shift register 347: 344: 309:home computers 279: 276: 223: 222: 205: 204: 185: 183: 176: 169: 168: 83: 81: 74: 69: 43: 42: 40: 33: 26: 9: 6: 4: 3: 2: 881: 870: 867: 865: 862: 860: 857: 855: 852: 851: 849: 834: 831: 829: 826: 824: 821: 819: 818:DRAM timeline 816: 815: 813: 809: 803: 800: 798: 795: 793: 790: 788: 785: 784: 782: 780: 776: 770: 767: 765: 762: 760: 757: 756: 754: 752: 748: 740: 737: 735: 732: 730: 727: 725: 722: 720: 717: 715: 712: 710: 707: 706: 705: 702: 700: 697: 695: 692: 690: 687: 686: 684: 680: 674: 671: 667: 664: 662: 659: 657: 654: 652: 649: 647: 644: 643: 642: 639: 637: 634: 632: 629: 626: 623: 620: 617: 613: 610: 608: 605: 603: 600: 598: 595: 594: 593: 590: 588: 585: 584: 582: 580: 576: 570: 567: 565: 562: 561: 559: 555: 550: 543: 538: 536: 531: 529: 524: 523: 520: 500: 499: 492: 479: 478: 471: 467: 453: 449: 443: 439: 429: 426: 425: 419: 416: 406: 404: 400: 396: 392: 386: 384: 383:address buses 378: 376: 371: 369: 365: 361: 357: 353: 343: 341: 336: 332: 327: 325: 321: 316: 314: 310: 306: 300: 298: 293: 289: 285: 271: 267: 263: 261: 257: 251: 249: 245: 241: 237: 233: 229: 219: 216: 201: 198:February 2018 189: 184: 175: 174: 165: 162: 154: 143: 140: 136: 133: 129: 126: 122: 119: 115: 112: –  111: 107: 106:Find sources: 100: 96: 90: 89: 84:This article 82: 78: 73: 72: 67: 65: 58: 57: 52: 51: 46: 41: 32: 31: 19: 854:Types of RAM 621:(Mobile DDR) 557:Asynchronous 506:, retrieved 497: 491: 481:, retrieved 476: 470: 442: 412: 398: 390: 387: 379: 374: 372: 355: 349: 331:IBM Research 328: 317: 301: 281: 264: 252: 231: 227: 226: 211: 195: 187: 157: 148: 138: 131: 124: 117: 105: 93:Please help 88:verification 85: 61: 54: 48: 47:Please help 44: 579:Synchronous 399:shift clock 393:which is a 375:destructive 346:Description 324:Amiga Agnus 313:wait states 284:dynamic RAM 260:wait states 244:framebuffer 240:dynamic RAM 238:variant of 236:dual-ported 848:Categories 508:2009-03-02 483:2017-06-07 462:References 448:static RAM 391:row-buffer 352:capacitors 305:system bus 288:television 151:April 2009 121:newspapers 50:improve it 828:Bandwidth 769:XDR2 DRAM 592:DDR SDRAM 56:talk page 764:XDR DRAM 682:Graphics 569:EDO DRAM 564:FPM DRAM 422:See also 403:data bit 368:data bus 797:UniDIMM 661:HBM-PIM 627:(FCRAM) 364:latches 278:History 234:) is a 188:updated 135:scholar 751:Rambus 636:RLDRAM 551:(DRAM) 137:  130:  123:  116:  108:  811:Lists 759:RDRAM 739:GDDR7 734:GDDR6 729:GDDR5 724:GDDR4 719:GDDR3 714:GDDR2 704:SGRAM 699:MDRAM 666:HBM3E 651:HBM2E 631:eDRAM 619:LPDDR 587:SDRAM 502:(PDF) 434:Notes 335:RT PC 142:JSTOR 128:books 802:CAMM 792:DIMM 787:SIMM 709:GDDR 694:WRAM 689:VRAM 656:HBM3 646:HBM2 612:DDR5 607:DDR4 602:DDR3 597:DDR2 360:byte 356:cell 232:VRAM 114:news 641:HBM 450:or 246:in 97:by 850:: 250:. 59:. 541:e 534:t 527:v 454:. 230:( 218:) 212:( 200:) 196:( 190:. 164:) 158:( 153:) 149:( 139:· 132:· 125:· 118:· 91:. 66:) 62:( 20:)

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Video RAM (dual-ported DRAM)
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dual-ported
dynamic RAM
framebuffer
graphics adapters
video display controller
wait states

dynamic RAM
television
composite video
central processing unit
system bus
home computers
wait states

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