268:
234:
tags are located on-die to enable it be clocked at the microprocessor's clock frequency. This increases bandwidth for accessing the cache tags, enabling the UltraSPARC to scale to higher clock frequencies easily. Part of the increased bandwidth to the cache tags is used by cache coherency traffic, which is required in the multiprocessor systems the UltraSPARC III is designed to be used in. As the maximum capacity of L2 cache is 8 MB, the L2 cache tags is 90 KB in size.
34:
902:
291:. This enabled it to operate at 750 to 900 MHz. The die is packaged using the Controlled Collapse Chip Connection method and is the first Sun microprocessor to do so. Unlike most other microprocessors bonded in such a way, the majority of the solder bumps are placed in a peripheral ring instead of being distributed across the die. It was packaged in a 1368-pad
376:
The UltraSPARC IV combined two UltraSPARC III cores onto a single piece of silicon and offered increased clock rates. The CPU's packaging was nearly identical, offering the difference of a single pin, simplifying board manufacturing and system design. Some systems which used UltraSPARC III processors
233:
with a 32-byte cache line. The external L2 cache has a maximum capacity of 8 MB. It is accessed via a dedicated 256-bit bus operating at up 200 MHz for a peak bandwidth of 6.4 GB/s. The cache is built synchronous static random access memory clocked at frequencies up to 200 MHz. The L2 cache
323:
The UltraSPARC IIIi has a unified 1 MB L2 cache that operates at half of the microprocessor's clock frequency. As such, it has a six-cycle latency and a two-cycle throughput. The load to use latency is 15 cycles. The tag store is protected by parity and the data by ECC. For every 64-byte cache
221:(ALUs), a load and store unit and two floating-point units. One of the ALUs can only execute simple integer instructions and loads. The two floating point units are also not equal. One can only execute simple instructions such as adds while the other executes multiplies, divides and square roots.
324:
line, there are 36 ECC bits, enabling the correction of one-bit errors and the detection of any error within a four bits. The cache is four-way set-associative, has a 64-byte line size and is physically indexed and tagged. It uses a 2.76 ÎĽm SRAM cell and consists of 63 million transistors.
216:
It fetches up to four instructions per cycle from the instruction cache. Decoded instructions are sent to a dispatch unit at up to six at a time. The dispatch unit issues the instructions to the appropriate execution units depending on operand and resource availability. The execution resources
327:
The on-die memory controller supports 256 MB to 16 GB of 133 MHz DDR-I SDRAM. The memory is accessed via a 137-bit memory bus, of which 128 bits are for data and 9 are for ECC. The memory bus has a peak bandwidth of 4.2 GB/s. The microprocessor was designed to support four-way
319:
The UltraSPARC IIIi, code named "Jalapeño", is a derivative of the UltraSPARC III for workstations and low-end (one to four processor) servers introduced in 2003. It operates at 1064 to 1593 MHz, has an on-die L2 cache and an integrated memory controller, and is capable of four-way
258:
and implements a dedicated 128-bit bus operating at 150 MHz to access up to 4 GB of "local" memory. The integrated memory controller is used to reduce latency and thus improve performance, unlike some other UltraSPARC microprocessors that use the feature to reduce cost.
320:
multiprocessing with a glue-less system bus optimized for the function. It contains 87.5 million transistors and has a 178.5 mm die. It was fabricated by Texas
Instruments in a 0.13 ÎĽm, seven-layer metal (copper) CMOS process with low-k dielectric.
307:, code-named "Cheetah+", is a further development of the original UltraSPARC III that operated at higher clock frequencies of 1002 to 1200 MHz. It has a die size of 232 mm and was fabricated in a 0.13 ÎĽm, 7-layer
336:
The UltraSPARC IIIi+, code-named "Serrano", was a further development of the UltraSPARC IIIi. It was scheduled for introduction in the second half of 2005, but was cancelled in the same year in favor of the
328:
multiprocessing. Jbus is used to connect up to four microprocessors. It is a 128-bit address and data multiplexed bus that operates at one half or one third of the microprocessor's clock frequency.
181:(Merced). This was not to be the case as it was delayed until 2001. Despite being late, it was awarded the Analysts' Choice Award for Best Server/Workstation Processor of 2001 by
173:
When presented at the '97 Microprocessor Forum, the probable introduction date for the UltraSPARC III was 1999, and it would have competed with
Digital Equipment Corporation's
229:
The UltraSPARC III has split primary instruction and data caches. The instruction cache has a capacity of 32 KB. The data cache has a capacity of 64 KB and is four-way
472:
1353:
280:
213:
performance, and it has several features that aid in achieving that goal: an integrated memory controller and a dedicated multiprocessing bus.
275:
The UltraSPARC III consisted of 16 million transistors, of which 75% are contained in the caches and tags. It was initially fabricated by
246:
operating at 150 MHz. The data bus is not used to access memory, but the memory of other microprocessors and the shared I/O devices.
1164:
454:
207:
1368:
1209:
349:. Its cancellation was not known until 31 August 2006. Improvements were higher clock frequencies in the range of 2
1373:
1118:
386:
Konstadinidis, Georgios K. et al. (2002). "Implementation of a Third-Generation 1.1-GHz 64-bit
Microprocessor".
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8:
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311:, CMOS process by Texas Instruments. It was packaged in a 1,368-pad ceramic LGA package.
161:. It was introduced in 2001 and operates at 600 to 900 MHz. It was succeeded by the
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The external interface consists of a 128-bit data bus and a 43-bit
88:
393:
Song, Peter (27 October 1997). "UltraSparc-3 Aims at MP Servers".
283:(CMOS) process with a 0.18 ÎĽm feature size and six-levels of
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178:
146:, code-named "Cheetah", is a microprocessor that implements the
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The UltraSPARC III family of processors was succeeded by the
147:
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MB) on-die L2 cache, support for DDR-333 SDRAM, and a new 90
287:. In 2001, it was fabricated in a 0.13 ÎĽm process with
1282:
960:
837:
816:
1051:
206:
microprocessor. The UltraSPARC III was designed for
281:
complementary metal–oxide–semiconductor
404:"Sun kills off much delayed UltraSPARC IIIi+ chip"
165:in 2004. Gary Lauterbach was the chief architect.
1345:
377:could accept UltraSPARC IV CPU board upgrades.
448:
16:Microprocessor developed by Sun Microsystems
1165:Common Development and Distribution License
900:
455:
441:
266:
1354:Computer-related introductions in 2001
1346:
436:
237:
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388:IEEE Journal of Solid-State Circuits
298:
249:
331:
13:
314:
14:
1385:
254:The UltraSPARC has an integrated
402:Vance, Ashlee (31 August 2006).
32:
78:Architecture and classification
271:A prototype UltraSPARC III die
194:
1:
1200:Open Source University Meetup
1109:Sun Microsystems Laboratories
416:"UltraSPARC III Cu Processor"
380:
364:
151:instruction set architecture
73:600 MHz to 900 MHz
7:
1369:Superscalar microprocessors
1319:The Network is the Computer
421:
262:
10:
1390:
519:SPARCstation/server/center
168:
18:
1332:
1311:
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1132:
1101:
1065:
1029:
1001:Sun Secure Global Desktop
909:
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279:in their C07a process, a
199:The UltraSPARC III is an
130:
120:
115:
99:
94:
82:
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63:
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48:
43:
31:
1324:Write once, run anywhere
868:System Service Processor
224:
19:Not to be confused with
883:Ultra Port Architecture
390:, Volume 37, Number 11.
289:aluminium interconnects
95:Physical specifications
1374:64-bit microprocessors
1170:Java Community Process
1037:StorageTek 5800 System
888:Visual Instruction Set
285:aluminium interconnect
272:
219:arithmetic logic units
1359:SPARC microprocessors
1124:Project Looking Glass
396:Microprocessor Report
270:
184:Microprocessor Report
1083:Visualization System
1078:Constellation System
309:copper metallization
84:Instruction set
1364:Sun microprocessors
971:Java Desktop System
153:(ISA) developed by
44:General information
28:
858:Modular Datacenter
473:Acquired by Oracle
273:
238:External interface
157:and fabricated by
38:Sun UltraSPARC III
26:
1341:
1340:
1288:Procom Technology
1268:Lighthouse Design
1241:
1240:
1223:Andy Bechtolsheim
1042:StorageTek SL8500
896:
895:
773:UltraSPARC III Cu
650:Blade workstation
305:UltraSPARC III Cu
299:UltraSPARC III Cu
277:Texas Instruments
256:memory controller
250:Memory controller
217:consisted of two
159:Texas Instruments
140:
139:
1381:
1273:Montalvo Systems
1253:Afara Websystems
1158:
1157:
904:
697:Java Workstation
687:SPARC Enterprise
484:
483:
464:Sun Microsystems
457:
450:
443:
434:
433:
360:
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353:GHz, a larger (4
352:
332:UltraSPARC IIIi+
155:Sun Microsystems
53:Sun Microsystems
36:
29:
25:
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1388:
1384:
1383:
1382:
1380:
1379:
1378:
1344:
1343:
1342:
1337:
1328:
1307:
1258:Cobalt Networks
1237:
1204:
1149:
1128:
1097:
1061:
1025:
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892:
821:
776:UltraSPARC IIIi
716:
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315:UltraSPARC IIIi
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295:(LGA) package.
293:land grid array
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231:set-associative
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211:multiprocessing
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189:multiprocessing
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1180:OpenOffice.org
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792:UltraSPARC T2
790:
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787:UltraSPARC T1
785:
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782:UltraSPARC IV
780:
775:
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371:UltraSPARC IV
362:
348:
347:UltraSPARC T2
344:
343:UltraSPARC T1
340:
329:
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321:
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306:
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208:shared memory
205:
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163:UltraSPARC IV
160:
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149:
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135:UltraSPARC IV
133:
129:
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125:UltraSPARC II
123:
119:
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107:
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87:
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81:
76:
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67:
62:
57:
54:
51:
47:
42:
35:
30:
22:
1246:Acquisitions
1233:Vinod Khosla
1047:Open Storage
768:
645:Blade server
576:SPARCclassic
409:The Register
407:
394:
387:
375:
368:
361:nm process.
335:
326:
322:
318:
304:
302:
274:
253:
241:
228:
215:
198:
182:
177:and Intel's
172:
143:
141:
1185:OpenSolaris
1088:Grid Engine
1066:Performance
996:Java System
966:OpenWindows
707:Cobalt Qube
692:JavaStation
244:address bus
204:superscalar
195:Description
175:Alpha 21264
121:Predecessor
59:Performance
49:Designed by
1348:Categories
1303:Tarantella
1298:StorageTek
1021:VirtualBox
986:StarOffice
748:UltraSPARC
743:SuperSPARC
738:microSPARC
721:Processors
712:Cobalt RaQ
633:Enterprise
381:References
365:Successors
191:features.
69:clock rate
1190:OpenSPARC
1154:Community
1133:Education
1016:GlassFish
843:Fireplane
428:Fireplane
131:Successor
1335:Category
1278:MySQL AB
1263:Gridware
1218:Bill Joy
1175:NetBeans
1119:Fortress
1114:picoJava
1102:Research
910:Software
848:LOM port
807:SPARC T5
802:SPARC T4
797:SPARC T3
480:Hardware
422:See also
373:series.
263:Physical
201:in-order
187:for its
148:SPARC V9
89:SPARC V9
1312:Slogans
1195:OpenJDK
1030:Storage
991:iPlanet
956:SunView
922:Solaris
863:Neptune
733:MB86900
509:Sun386i
487:Systems
179:Itanium
169:History
116:History
1293:SavaJe
1210:People
1093:Lustre
976:Studio
763:Gemini
359:
355:
351:
1145:BlueJ
1073:Cloud
1006:MySQL
917:SunOS
833:Sun4d
826:Other
728:SPARC
680:X4500
675:T2000
638:10000
586:Ultra
581:Netra
514:Sun-4
504:Sun-3
499:Sun-2
494:Sun-1
225:Cache
101:Cores
64:Max.
1283:Pixo
1140:SCPs
981:Java
961:NeWS
949:ZFS+
932:NIS+
878:SPOT
853:MBus
838:SBus
817:MAJC
812:Rock
670:E25K
655:Fire
345:and
303:The
142:The
1057:ZFS
1052:QFS
1011:xVM
944:ZFS
939:NFS
927:NIS
702:Ray
665:15K
660:12K
559:IPX
554:IPC
66:CPU
1350::
626:80
621:60
616:30
611:24
606:10
569:ZX
564:LX
549:20
544:10
406:.
341:,
601:5
596:2
591:1
539:5
534:4
529:2
524:1
456:e
449:t
442:v
412:.
399:.
108:1
23:.
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