170:
processors to work with each other more efficiently, and allows a logical processor to borrow resources from a stalled logical core (assuming both logical cores are associated with the same physical core). A processor stalls when it must wait for data it has requested, in order to finish processing the present thread. The degree of benefit seen when using a hyper-threaded, or multi-core, processor depends on the needs of the software, and how well it and the operating system are written to manage the processor efficiently.
151:
4625:
185:" processor to the host operating system (HTT-unaware operating systems see two "physical" processors), allowing the operating system to schedule two threads or processes simultaneously and appropriately. When execution resources in a hyper-threaded processor are not in use by the current task, and especially when the processor is stalled, those execution resources can be used to execute another scheduled task. (The processor may stall due to a
33:
640:, includes list of Operating Systems that include optimizations for Hyper-Threading Technology; they are Windows XP Professional 64, Windows XP MCE, Windows XP Home, Windows XP Professional, some versions of Linux such as COSIX Linux 4.0, RedHat Linux 9 (Professional and Personal versions), RedFlag Linux Desktop 4.0 and SuSe Linux 8.2 (Professional and Personal versions)
352:
significantly increased due to hyper-threading, with the negative effects becoming smaller as there are more simultaneous threads that can effectively use the additional hardware resource utilization provided by hyper-threading. A similar performance analysis is available for the effects of hyper-threading when used to handle tasks related to managing network traffic, such as for processing
257:. It was also included on the 3.06 GHz Northwood-based Pentium 4 in the same year, and then remained as a feature in every Pentium 4 HT, Pentium 4 Extreme Edition and Pentium Extreme Edition processor since. The Intel Core & Core 2 processor lines (2006) that succeeded the Pentium 4 model line didn't utilize hyper-threading. The processors based on the
213:
share execution resources, while the other processor would remain idle, leading to poorer performance than if the threads were scheduled on different physical processors. This problem can be avoided by improving the scheduler to treat logical processors differently from physical processors, which is, in a sense, a limited form of the scheduler changes required for
308: 9300 launched with eight threads per processor (two threads per core) through enhanced hyper-threading technology. The next model, the Itanium 9500 (Poulson), features a 12-wide issue architecture, with eight CPU cores with support for eight more virtual cores via hyper-threading. The Intel Xeon 5500 server chips also utilize two-way hyper-threading.
166:. Architecturally, a processor with Hyper-Threading Technology consists of two logical processors per core, each of which has its own processor architectural state. Each logical processor can be individually halted, interrupted or directed to execute a specified thread, independently from the other logical processor sharing the same physical core.
239:(HEP) in 1982. The HEP pipeline could not hold multiple instructions from the same process. Only one instruction from a given process was allowed to be present in the pipeline at any point in time. Should an instruction from a given process block the pipe, instructions from other processes would continue after the pipeline drained.
300:(Core i7) in November 2008, in which hyper-threading made a return. The first generation Nehalem processors contained four physical cores and effectively scaled to eight threads. Since then, both two- and six-core models have been released, scaling four and twelve threads respectively. Earlier
212:
is unaware of hyper-threading, it will treat all four logical processors the same. If only two threads are eligible to run, it might choose to schedule those threads on the two logical processors that happen to belong to the same physical processor. That processor would be extremely busy, and would
347:
of the
Pentium 4 tying up valuable execution resources, equalizing the processor resources between the two programs, which adds a varying amount of execution time. The Pentium 4 "Prescott" and the Xeon "Nocona" processors received a replay queue that reduces execution time needed for the
337:
applications, but not all. Depending on the cluster configuration and, most importantly, the nature of the application running on the cluster, performance gains can vary or even be negative. The next step is to use performance tools to understand what areas contribute to performance gains and what
447:, as the malicious thread measures the time of only its own execution. Potential solutions to this include the processor changing its cache eviction strategy or the operating system preventing the simultaneous execution, on the same physical core, of threads with different privileges. In 2018 the
169:
Unlike a traditional dual-processor configuration that uses two separate physical processors, the logical processors in a hyper-threaded core share the execution resources. These resources include the execution engine, caches, and system bus interface; the sharing of resources allows two logical
1174:
Per-cpu load can be observed using the mpstat utility, but note that on processors with hyperthreading (HT), each hyperthread is represented as a separate CPU. For interrupt handling, HT has shown no benefit in initial tests, so limit the number of queues to the number of CPU cores in the
351:
According to a
November 2009 analysis by Intel, performance impacts of hyper-threading result in increased overall latency in case the execution of threads does not result in significant overall throughput gains, which vary by the application. In other words, overall processing latency is
342:
As a result, performance improvements are very application-dependent; however, when running two programs that require full attention of the processor, it can actually seem like one or both of the programs slows down slightly when Hyper-Threading
Technology is turned on. This is due to the
325:
states: "In some cases a P4 running at 3.0 GHz with HT on can even beat a P4 running at 3.6 GHz with HT turned off." Intel also claims significant performance improvements with a hyper-threading-enabled
Pentium 4 processor in some artificial-intelligence algorithms.
207:
It is possible to optimize operating system behavior on multi-processor, hyper-threading capable systems. For example, consider an SMP system with two physical processors that are both hyper-threaded (for a total of four logical processors). If the operating system's thread
1595:
770:
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than the comparable non-hyperthreaded processor, but the performance was 15–30% better. Intel claims up to a 30% performance improvement compared with an otherwise identical, non-simultaneous multithreading
Pentium 4.
125:
addresses two virtual (logical) cores and shares the workload between them when possible. The main function of hyper-threading is to increase the number of independent instructions in the pipeline; it takes advantage of
419:, Intel temporarily moved away from including hyper-threading in mainstream Core i7 desktop processors except for highest-end Core i9 parts or Pentium Gold CPUs. It also began to recommend disabling hyper-threading, as
138:
scheduling of two processes per core. In addition, two or more processes can use the same resources: If resources for one process are not available, then another process can continue if its resources are available.
941:
375:(a specialized, low-power, CPU design company), stated that simultaneous multithreading can use up to 46% more power than ordinary dual-core designs. Furthermore, they claimed that SMT increases
142:
In addition to requiring simultaneous multithreading support in the operating system, hyper-threading can be properly utilized only with an operating system specifically optimized for it.
386:
In 2010, ARM said it might include simultaneous multithreading in its future chips; however, this was rejected in favor of their 2012 64-bit design. ARM produced SMT cores in 2018.
1101:
901:
637:
964:"Summary: In Some Cases The P4 3.0HT Can Even Beat The 3.6 GHz Version : Single CPU in Dual Operation: P4 3.06 GHz with Hyper-Threading Technology"
1443:
225:
The first published paper describing what is now known as hyper-threading in a general purpose computer was written by Edward S. Davidson and
Leonard. E. Shar in 1973.
528:
368:
When the first HT processors were released, many operating systems were not optimized for hyper-threading technology (e.g. Windows 2000 and Linux older than 2.4).
949:
3951:
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Overall the performance history of hyper-threading was a mixed one in the beginning. As one commentary on high-performance computing from
November 2002 notes:
1015:
616:
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791:
228:
2782:
1965:
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750:"A multiminiprocessor system implemented through pipelining", by Leonard Shar and Edward Davidson, IEEE Computer, Feb. 1974, pp. 42-51, vol. 7
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36:
In this high-level depiction of HTT, instructions are fetched from RAM (differently colored boxes represent the instructions of four different
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590:
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operating system has disabled hyper-threading "in order to avoid data potentially leaking from applications to other software" caused by the
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204:(SMP) support in the operating system, since the logical processors appear no different to the operating system than physical processors.
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2207:
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This technology is transparent to operating systems and programs. The minimum that is required to take advantage of hyper-threading is
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1987:
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708:,, Bakos, Jason D.,, Colwell, Robert P.,, Bhattacharjee, Abhishek, 1984-, Conte, Thomas M., 1964- (Sixth ed.). Cambridge, MA.
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processor cores, as they found this gave better performance with better power efficiency than a lower number of cores with SMT.
304:
cores were in-order processors, sometimes with hyper-threading ability, for low power mobile PCs and low-price desktop PCs. The
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Deborah T. Marr; Frank Binns; David L. Hill; Glenn Hinton; David A. Koufaty; J. Alan Miller; Michael Upton (12 December 2006).
232:
159:
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of another thread with which it shares a cache, allowing the theft of cryptographic information. This is not actually a
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44:), and passed to the execution core capable of executing instructions from two different programs during the same
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360:(NICs). Another paper claims no performance improvements when hyper-threading is used for interrupt handling.
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2009:
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2004:
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Intel
Required Components Interchangeability List for the Intel Pentium 4 Processor with HT Technology
357:
1318:
1188:"Hyper-Threading Technology – Operating systems that include optimizations for Hyper-Threading Technology"
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United States Patent: 5361337 - Method and apparatus for rapidly switching processes in a computer system
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181:. This allows a hyper-threading processor to appear as the usual "physical" processor plus an extra "
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A 3 GHz model of the Intel
Pentium 4 processor that incorporates Hyper-Threading Technology
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Intel implemented hyper-threading on an x86 architecture processor in 2002 with the Foster MP-based
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591:"Intel Pentium 4 3.06GHz CPU with Hyper-Threading Technology: Killing Two Birds with a Stone."
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did not have hyper-threading because the Core microarchitecture was a descendant of the older
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265:. The P6 microarchitecture was used in earlier iterations of Pentium processors, namely, the
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technology introduced by Intel, while the concept behind the technology has been patented by
127:
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650:
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processors had a bug in their implementation of hyper-threading that could cause data loss.
173:
Hyper-threading works by duplicating certain sections of the processor—those that store the
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1617:
The Impact of Hyper-Threading on
Processor Resource Utilization in Production Applications
134:. With HTT, one physical core appears as two processors to the operating system, allowing
8:
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process technology was not advanced enough to allow for a cost-effective implementation.
174:
37:
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1975:
1703:
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131:
102:
desktop processors in November 2002. Since then, Intel has included this technology in
942:"How to Determine the Effectiveness of Hyper-Threading Technology with an Application"
705:
459:
led to security experts recommending the disabling of hyper-threading on all devices.
4590:
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3701:
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3320:
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2014:
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1908:
1886:
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1750:
1668:
1016:"Maximized performance: Comparing the effects of Hyper-Threading, software updates"
526:
468:
243:
242:
US patent for the technology behind hyper-threading was granted to Kenneth Okin at
163:
122:
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4404:
4339:
4186:
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376:
194:
1236:. theinquirer.net. 2 August 2006. Archived from the original on 6 September 2009
435:
demonstrated that a malicious thread on a Pentium 4 can use a timing-based
186:
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4411:
4068:
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3548:
3382:
3365:
3358:
3254:
3111:
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2276:
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2187:
2182:
2177:
1891:
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432:
316:
According to Intel, the first hyper-threading implementation used only 5% more
290:
182:
178:
150:
118:
41:
1425:"Intel 9th Gen Core Processors: All the Desktop and Mobile 45W CPUs Announced"
371:
In 2006, hyper-threading was criticised for energy inefficiency. For example,
4644:
4484:
4361:
3655:
3343:
3259:
2299:
2281:
2074:
1767:
1544:"Meltdown Redux: Intel Flaw Lets Hackers Siphon Secrets from Millions of PCs"
920:
723:
675:
444:
344:
2202:
1468:
1212:. Information Resources Management Association. December 2013. p. 666.
4084:
3660:
3553:
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2817:
1755:
1400:
504:
372:
286:
4605:
3665:
3338:
3302:
3013:
2985:
2843:
2698:
1621:
985:
Tau Leng; Rizwan Ali; Jenwei Hsieh; Christopher Stanton (November 2002).
416:
274:
266:
45:
669:"The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms"
3747:
3706:
3620:
3224:
3214:
3209:
3191:
3091:
3064:
2326:
2159:
2129:
1849:
1396:"Skylake, Kaby Lake Chips Have a Crash Bug with Hyperthreading Enabled"
1161:
986:
394:
301:
270:
111:
107:
1210:
Sustainable Practices: Concepts, Methodologies, Tools and Applications
130:
architecture, in which multiple instructions operate on separate data
4479:
4454:
3871:
3814:
3794:
3670:
3640:
3315:
3312:
3054:
2124:
2102:
1301:"ARM launches first 64bit processor core for servers and smartphones"
569:
409:
405:
380:
99:
32:
4529:
4509:
4434:
3610:
3564:
3330:
2149:
1497:"OpenBSD disables Intel's hyper-threading over CPU data leak fears"
1371:"Intel's Skylake and Kaby Lake CPUs have nasty hyper-threading bug"
1158:"Linux kernel documentation: Scaling in the Linux Networking Stack"
987:"A Study of Hyper-Threading in High-Performance Computing Clusters"
792:"Extreme Gaming with the Intel® Core™ i7 Processor Extreme Edition"
500:"Introduction to Multithreading, Superthreading and Hyperthreading"
752:
https://www.computer.org/csdl/magazine/co/1974/02/4251/13rRUyoyhIt
4534:
4514:
4489:
4124:
2139:
2097:
448:
305:
278:
103:
40:), decoded and reordered by the front end (white boxes represent
1041:"CPU Performance Evaluation - Benchmark - Pentium 4 2.8 and 3.0"
423:
attacks were revealed which could be mitigated by disabling HT.
348:
replay system and completely overcomes the performance penalty.
4504:
4499:
2154:
2119:
2084:
1345:"Deep inside Intel's first viable mobile processor: Silvermont"
566:"The Haswell Front End – Intel's Haswell Architecture Analyzed"
529:"Hyper-Threading Technology Architecture and Microarchitecture"
27:
Proprietary simultaneous multithreading implementation by Intel
1606:
ZDnet: Hyperthreading hurts server performance, say developers
3716:
3711:
3595:
2612:
2144:
2114:
1548:
1444:"Intel's New Spectre-Like Flaw Affects Chips Made Since 2008"
1105:
72:
4539:
4469:
4459:
3737:
3476:
2624:
2544:
2134:
1319:"Arm launches first SMT-capable Cortex core | bit-tech.net"
282:
254:
247:
91:
1102:"Performance Insights to Intel Hyper-Threading Technology"
700:
Hennessy, John L.; Patterson, David A. (7 December 2017).
617:"Intel® Hyper-Threading Technology (Intel® HT Technology)"
4449:
4426:
2064:
2054:
1518:"'Disable SMT/Hyperthreading in all Intel BIOSes' - MARC"
87:
1271:"About MIPS and MIPS | TOP500 Supercomputing Sites"
1071:"Replay: Unknown Features of the NetBurst Core. Page 15"
674:. Texas A&M University. p. 23. Archived from
1009:
1007:
158:
Hyper-Threading Technology is a form of simultaneous
333:
Hyper-Threading can improve the performance of some
1004:
412:updates were later released to address the issue.
699:
4642:
1574:Intel Demonstrates Breakthrough Processor Design
563:
1580:Intel – high level overview of Hyper-threading
836:"Intel Discloses New Itanium Poulson Features"
702:Computer Architecture: A Quantitative Approach
3887:
3580:
1637:
1342:
1075:Replay: Unknown Features of the NetBurst Core
662:
660:
338:areas contribute to performance degradation.
1601:Merom, Conroe, Woodcrest lose HyperThreading
86:(doing multiple tasks at once) performed on
2642:Computer performance by orders of magnitude
1013:
3894:
3880:
3733:Advanced Programmable Interrupt Controller
3697:Intel Communication Streaming Architecture
3587:
3573:
1651:
1644:
1630:
814:"Intel® Atom™ Processor Microarchitecture"
736:: CS1 maint: location missing publisher (
666:
657:
3775:High-bandwidth Digital Content Protection
1541:
1535:
1466:
1388:
1368:
1268:
667:Thomadakis, Michael E. (17 March 2011).
293:have added support for hyper-threading.
149:
31:
1422:
880:"Intel Xeon Processor 5500 Series"
389:In 2013, Intel dropped SMT in favor of
14:
4643:
3901:
3820:Platform Environment Control Interface
1441:
1099:
497:
400:In 2017, it was revealed that Intel's
90:microprocessors. It was introduced on
3875:
3568:
1625:
643:
311:
82:(SMT) implementation used to improve
3594:
2613:Floating-point operations per second
1613:- Outlines problems of SMT solutions
1100:Valles, Antonio (20 November 2009).
966:. Tomshardware.com. 14 November 2002
762:
651:"Intel Processor Spec Finder: SL6WK"
564:Anand Lal Shimpi (5 October 2012).
24:
3805:Host Embedded Controller Interface
1576:, a press release from August 2001
1469:"Cache Missing for Fun and Profit"
1369:Chirgwin, Richard (25 June 2017).
838:. Tomshardware.com. 24 August 2011
25:
4667:
1567:
1269:Jermoluk, Tom (13 October 2010).
1234:"ARM is no fan of HyperThreading"
763:Okin, Kenneth (1 November 1994),
246:in November 1994. At that time,
4624:
4623:
3539:Semiconductor device fabrication
1585:Hyper-threading on MSDN Magazine
1132:"Network Tuning and Performance"
121:that is physically present, the
4095:Analysis of parallel algorithms
3514:History of general-purpose CPUs
1741:Nondeterministic Turing machine
1611:ARM is no fan of HyperThreading
1542:Greenberg, Andy (14 May 2019).
1510:
1489:
1467:Percival, Colin (14 May 2005).
1460:
1435:
1416:
1362:
1336:
1311:
1293:
1262:
1226:
1202:
1180:
1150:
1124:
1093:
1063:
1033:
978:
956:
948:. 28 April 2011. Archived from
934:
894:
872:
850:
828:
806:
784:
756:
744:
237:Heterogeneous Element Processor
84:parallelization of computations
1694:Deterministic finite automaton
1442:Armasu, Lucian (14 May 2019).
1423:Cutress, Ian (23 April 2019).
1190:. Intel.com. 19 September 2011
693:
631:
609:
583:
557:
520:
498:Stokes, Jon (3 October 2002).
491:
177:—but not duplicating the main
13:
1:
4042:Simultaneous and heterogenous
2485:Simultaneous and heterogenous
858:"Server Processor Index Page"
484:
358:network interface controllers
4630:Category: Parallel computing
3763:Active Management Technology
3692:MultiProcessor Specification
3169:Integrated memory controller
3151:Translation lookaside buffer
2350:Memory dependence prediction
1793:Random-access stored program
1746:Probabilistic Turing machine
1343:Rik Myslewski (8 May 2013).
1014:Joel Hruska (24 July 2012).
902:"Hyper-Threading Technology"
363:
7:
2625:Synaptic updates per second
462:
455:vulnerabilities. In 2019 a
426:
383:results in a 37% decrease.
145:
80:simultaneous multithreading
10:
4672:
3937:High-performance computing
3029:Heterogeneous architecture
1951:Orthogonal instruction set
1721:Alternating Turing machine
1709:Quantum cellular automaton
1596:US Patent Number 4,847,755
1077:. Xbitlabs. Archived from
860:. Intel.com. 18 March 2011
816:. Intel.com. 18 March 2011
593:X-bit labs. Archived from
285:derivatives at the time).
220:
57:Hyper-Threading Technology
4619:
4571:Automatic parallelization
4563:
4425:
4265:
4215:
4207:Application checkpointing
4169:
4133:
4077:
4021:
3970:
3909:
3853:
3725:
3679:
3603:
3519:Microprocessor chronology
3506:
3482:Dynamic frequency scaling
3455:
3391:
3329:
3283:
3235:
3190:
3110:
3037:
3006:
2911:
2832:
2796:
2750:
2650:
2637:Cache performance metrics
2576:
2510:
2460:
2371:
2362:
2335:
2290:
2257:
2229:
2220:
2040:
1943:
1932:
1803:
1659:
1254:: CS1 maint: unfit URL (
298:Nehalem microarchitecture
202:symmetric multiprocessing
3800:Serial Digital Video Out
3790:Rapid Storage Technology
3534:Hardware security module
2877:Digital signal processor
2854:Graphics processing unit
2666:Graphics processing unit
909:Intel Technology Journal
98:in February 2002 and on
4586:Embarrassingly parallel
4581:Deterministic algorithm
3845:Ultra Path Interconnect
3830:Platform Controller Hub
3758:Intel Management Engine
3487:Dynamic voltage scaling
3270:Memory address register
3164:Branch target predictor
3128:Address generation unit
2871:Physics processing unit
2660:Central processing unit
2619:Transactions per second
2607:Instructions per second
2530:Array processing (SIMT)
1674:Stored-program computer
915:(1). 14 February 2012.
4301:Associative processing
4257:Non-blocking algorithm
4063:Clustered multi-thread
3861:Silicon Photonics Link
3825:QuickPath Interconnect
3293:Hardwired control unit
3175:Memory management unit
3140:Memory management unit
2889:Secure cryptoprocessor
2883:Tensor Processing Unit
2865:Vision processing unit
2599:Cycles per instruction
2593:Instructions per cycle
2540:Associative processing
2231:Instruction pipelining
1653:Processor technologies
457:set of vulnerabilities
441:memory access patterns
391:out-of-order execution
340:
259:Core microarchitecture
155:
49:
4417:Hardware acceleration
4330:Superscalar processor
4320:Dataflow architecture
3917:Distributed computing
3835:System Management Bus
3780:High Definition Audio
3687:Common Building Block
3376:Sum-addressed decoder
3122:Arithmetic logic unit
2249:Classic RISC pipeline
2203:Epiphany architecture
2050:Motorola 68000 series
474:Computer multitasking
421:new CPU vulnerability
331:
153:
35:
4296:Pipelined processing
4245:Explicit parallelism
4240:Implicit parallelism
4230:Dataflow programming
3497:Performance per watt
3075:replacement policies
2741:Package on a package
2631:Performance per watt
2535:Pipelined processing
2305:Tomasulo's algorithm
2110:Clipper architecture
1966:Application-specific
1679:Finite-state machine
1590:introductory article
773:on 21 September 2015
545:on 23 September 2015
479:Multi-core processor
263:P6 microarchitecture
191:branch misprediction
114:CPUs, among others.
4651:Threads (computing)
4520:Parallel Extensions
4325:Pipelined processor
3529:Digital electronics
3182:Instruction decoder
3134:Floating-point unit
2788:Soft microprocessor
2735:System in a package
2310:Reservation station
1840:Transport-triggered
1112:on 17 February 2015
1051:on 24 February 2021
952:on 2 February 2010.
930:on 19 October 2012.
802:on 1 December 2008.
437:side-channel attack
296:Intel released the
179:execution resources
175:architectural state
63:and abbreviated as
55:(officially called
4394:Massively parallel
4372:distributed shared
4192:Cache invalidation
4156:Instruction window
3947:Manycore processor
3927:Massively parallel
3922:Parallel computing
3903:Parallel computing
3401:Integrated circuit
3245:Processor register
2899:Baseband processor
2244:Operand forwarding
1704:Cellular automaton
1307:. 30 October 2012.
1138:. 12 November 2013
946:software.intel.com
354:interrupt requests
312:Performance claims
156:
50:
4638:
4637:
4591:Parallel slowdown
4225:Stream processing
4115:Karp–Flatt metric
3869:
3868:
3743:Intel Turbo Boost
3702:Intel Inboard 386
3562:
3561:
3451:
3450:
3070:Instruction cache
3060:Scratchpad memory
2907:
2906:
2894:Network processor
2823:Network on a chip
2778:Ultra-low-voltage
2729:Multi-chip module
2572:
2571:
2358:
2357:
2345:Branch prediction
2322:Register renaming
2216:
2215:
2198:VISC architecture
2020:Quantum computing
2015:VISC architecture
1897:Secondary storage
1813:Microarchitecture
1773:Register machines
1592:from Ars Technica
1456:on 4 August 2019.
1305:Tech Design Forum
1164:. 1 December 2014
992:. Dell. p. 4
681:on 11 August 2014
16:(Redirected from
4663:
4656:X86 architecture
4627:
4626:
4601:Software lockout
4400:Computer cluster
4335:Vector processor
4290:Array processing
4275:Flynn's taxonomy
4182:Memory coherence
3957:Computer network
3896:
3889:
3882:
3873:
3872:
3785:Hub Architecture
3753:Intel Secure Key
3589:
3582:
3575:
3566:
3565:
3524:Processor design
3416:Power management
3298:Instruction unit
3159:Branch predictor
3108:
3107:
2806:System on a chip
2748:
2747:
2588:Transistor count
2512:Flynn's taxonomy
2369:
2368:
2227:
2226:
2030:Addressing modes
1941:
1940:
1887:Memory hierarchy
1751:Hypercomputation
1669:Abstract machine
1646:
1639:
1632:
1623:
1622:
1561:
1560:
1558:
1556:
1539:
1533:
1532:
1530:
1528:
1514:
1508:
1507:
1505:
1503:
1493:
1487:
1486:
1484:
1482:
1473:
1464:
1458:
1457:
1452:. Archived from
1439:
1433:
1432:
1420:
1414:
1413:
1411:
1409:
1392:
1386:
1385:
1383:
1381:
1366:
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1340:
1334:
1333:
1331:
1329:
1315:
1309:
1308:
1297:
1291:
1290:
1288:
1286:
1277:. Archived from
1266:
1260:
1259:
1253:
1245:
1243:
1241:
1230:
1224:
1223:
1206:
1200:
1199:
1197:
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1184:
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1177:
1171:
1169:
1154:
1148:
1147:
1145:
1143:
1128:
1122:
1121:
1119:
1117:
1108:. Archived from
1097:
1091:
1090:
1088:
1086:
1067:
1061:
1060:
1058:
1056:
1047:. Archived from
1045:users.telenet.be
1037:
1031:
1030:
1028:
1026:
1011:
1002:
1001:
999:
997:
991:
982:
976:
975:
973:
971:
960:
954:
953:
938:
932:
931:
929:
923:. Archived from
906:
898:
892:
891:
889:
887:
876:
870:
869:
867:
865:
854:
848:
847:
845:
843:
832:
826:
825:
823:
821:
810:
804:
803:
798:. Archived from
788:
782:
781:
780:
778:
769:, archived from
760:
754:
748:
742:
741:
735:
727:
697:
691:
690:
688:
686:
680:
673:
664:
655:
654:
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641:
635:
629:
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607:
606:
604:
602:
587:
581:
580:
578:
576:
561:
555:
554:
552:
550:
544:
538:. Archived from
533:
524:
518:
517:
515:
513:
495:
469:Barrel processor
379:by 42%, whereas
275:Pentium III
244:Sun Microsystems
164:Sun Microsystems
123:operating system
42:pipeline bubbles
21:
4671:
4670:
4666:
4665:
4664:
4662:
4661:
4660:
4641:
4640:
4639:
4634:
4615:
4559:
4465:Coarray Fortran
4421:
4405:Beowulf cluster
4261:
4211:
4202:Synchronization
4187:Cache coherence
4177:Multiprocessing
4165:
4129:
4110:Cost efficiency
4105:Gustafson's law
4073:
4017:
3966:
3942:Multiprocessing
3932:Cloud computing
3905:
3900:
3870:
3865:
3849:
3810:Hyper-threading
3721:
3675:
3599:
3593:
3563:
3558:
3544:Tick–tock model
3502:
3458:
3447:
3387:
3371:Address decoder
3325:
3279:
3275:Program counter
3250:Status register
3231:
3186:
3146:Load–store unit
3113:
3106:
3033:
3002:
2903:
2860:Image processor
2835:
2828:
2798:
2792:
2768:Microcontroller
2758:Embedded system
2746:
2646:
2579:
2568:
2506:
2456:
2354:
2331:
2315:Re-order buffer
2286:
2267:Data dependency
2253:
2212:
2042:
2036:
1935:
1934:Instruction set
1928:
1914:Multiprocessing
1882:Cache hierarchy
1875:Register/memory
1799:
1699:Queue automaton
1655:
1650:
1570:
1565:
1564:
1554:
1552:
1540:
1536:
1526:
1524:
1516:
1515:
1511:
1501:
1499:
1495:
1494:
1490:
1480:
1478:
1476:Daemonology.net
1471:
1465:
1461:
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1436:
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1417:
1407:
1405:
1394:
1393:
1389:
1379:
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1367:
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1341:
1337:
1327:
1325:
1317:
1316:
1312:
1299:
1298:
1294:
1284:
1282:
1281:on 13 June 2011
1267:
1263:
1247:
1246:
1239:
1237:
1232:
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1227:
1220:
1208:
1207:
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1186:
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1129:
1125:
1115:
1113:
1098:
1094:
1084:
1082:
1069:
1068:
1064:
1054:
1052:
1039:
1038:
1034:
1024:
1022:
1020:extremetech.com
1012:
1005:
995:
993:
989:
983:
979:
969:
967:
962:
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940:
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841:
839:
834:
833:
829:
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811:
807:
790:
789:
785:
776:
774:
761:
757:
749:
745:
729:
728:
716:
706:Asanović, Krste
698:
694:
684:
682:
678:
671:
665:
658:
649:
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632:
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548:
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531:
525:
521:
511:
509:
496:
492:
487:
465:
453:Foreshadow/L1TF
439:to monitor the
429:
377:cache thrashing
366:
314:
271:Pentium II
233:multi-threading
223:
195:data dependency
148:
112:Core 'i' Series
53:Hyper-threading
28:
23:
22:
18:Hyper-Threading
15:
12:
11:
5:
4669:
4659:
4658:
4653:
4636:
4635:
4633:
4632:
4620:
4617:
4616:
4614:
4613:
4608:
4603:
4598:
4596:Race condition
4593:
4588:
4583:
4578:
4573:
4567:
4565:
4561:
4560:
4558:
4557:
4552:
4547:
4542:
4537:
4532:
4527:
4522:
4517:
4512:
4507:
4502:
4497:
4492:
4487:
4482:
4477:
4472:
4467:
4462:
4457:
4452:
4447:
4442:
4437:
4431:
4429:
4423:
4422:
4420:
4419:
4414:
4409:
4408:
4407:
4397:
4391:
4390:
4389:
4384:
4379:
4374:
4369:
4364:
4354:
4353:
4352:
4347:
4340:Multiprocessor
4337:
4332:
4327:
4322:
4317:
4316:
4315:
4310:
4305:
4304:
4303:
4298:
4293:
4282:
4271:
4269:
4263:
4262:
4260:
4259:
4254:
4253:
4252:
4247:
4242:
4232:
4227:
4221:
4219:
4213:
4212:
4210:
4209:
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4199:
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4189:
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4179:
4173:
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4167:
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4164:
4163:
4158:
4153:
4148:
4143:
4137:
4135:
4131:
4130:
4128:
4127:
4122:
4117:
4112:
4107:
4102:
4097:
4092:
4087:
4081:
4079:
4075:
4074:
4072:
4071:
4069:Hardware scout
4066:
4060:
4055:
4050:
4044:
4039:
4033:
4027:
4025:
4023:Multithreading
4019:
4018:
4016:
4015:
4010:
4005:
4000:
3995:
3990:
3985:
3980:
3974:
3972:
3968:
3967:
3965:
3964:
3962:Systolic array
3959:
3954:
3949:
3944:
3939:
3934:
3929:
3924:
3919:
3913:
3911:
3907:
3906:
3899:
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3884:
3876:
3867:
3866:
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3857:
3855:
3851:
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3837:
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3827:
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3817:
3812:
3807:
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3797:
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3755:
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3673:
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3658:
3653:
3648:
3643:
3638:
3633:
3628:
3623:
3618:
3613:
3607:
3605:
3601:
3600:
3592:
3591:
3584:
3577:
3569:
3560:
3559:
3557:
3556:
3551:
3549:Pin grid array
3546:
3541:
3536:
3531:
3526:
3521:
3516:
3510:
3508:
3504:
3503:
3501:
3500:
3494:
3489:
3484:
3479:
3474:
3469:
3463:
3461:
3453:
3452:
3449:
3448:
3446:
3445:
3440:
3435:
3430:
3425:
3420:
3419:
3418:
3413:
3408:
3397:
3395:
3389:
3388:
3386:
3385:
3383:Barrel shifter
3380:
3379:
3378:
3373:
3366:Binary decoder
3363:
3362:
3361:
3351:
3346:
3341:
3335:
3333:
3327:
3326:
3324:
3323:
3318:
3310:
3305:
3300:
3295:
3289:
3287:
3281:
3280:
3278:
3277:
3272:
3267:
3262:
3257:
3255:Stack register
3252:
3247:
3241:
3239:
3233:
3232:
3230:
3229:
3228:
3227:
3222:
3212:
3207:
3202:
3196:
3194:
3188:
3187:
3185:
3184:
3179:
3178:
3177:
3166:
3161:
3156:
3155:
3154:
3148:
3137:
3131:
3125:
3118:
3116:
3105:
3104:
3099:
3094:
3089:
3084:
3083:
3082:
3077:
3072:
3067:
3062:
3057:
3047:
3041:
3039:
3035:
3034:
3032:
3031:
3026:
3021:
3016:
3010:
3008:
3004:
3003:
3001:
3000:
2999:
2998:
2988:
2983:
2978:
2973:
2968:
2963:
2958:
2953:
2948:
2943:
2938:
2933:
2928:
2923:
2917:
2915:
2909:
2908:
2905:
2904:
2902:
2901:
2896:
2891:
2886:
2880:
2874:
2868:
2862:
2857:
2851:
2849:AI accelerator
2846:
2840:
2838:
2830:
2829:
2827:
2826:
2820:
2815:
2812:Multiprocessor
2809:
2802:
2800:
2794:
2793:
2791:
2790:
2785:
2780:
2775:
2770:
2765:
2763:Microprocessor
2760:
2754:
2752:
2751:By application
2745:
2744:
2738:
2732:
2726:
2721:
2716:
2711:
2706:
2701:
2696:
2694:Tile processor
2691:
2686:
2681:
2676:
2675:
2674:
2663:
2656:
2654:
2648:
2647:
2645:
2644:
2639:
2634:
2628:
2622:
2616:
2610:
2604:
2603:
2602:
2590:
2584:
2582:
2574:
2573:
2570:
2569:
2567:
2566:
2565:
2564:
2554:
2549:
2548:
2547:
2542:
2537:
2532:
2522:
2516:
2514:
2508:
2507:
2505:
2504:
2499:
2494:
2489:
2488:
2487:
2482:
2480:Hyperthreading
2472:
2466:
2464:
2462:Multithreading
2458:
2457:
2455:
2454:
2449:
2444:
2443:
2442:
2432:
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2425:
2415:
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2279:
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2269:
2263:
2261:
2255:
2254:
2252:
2251:
2246:
2241:
2239:Pipeline stall
2235:
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2218:
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2214:
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2211:
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2200:
2195:
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2188:z/Architecture
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1930:
1929:
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1911:
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1900:
1899:
1894:
1892:Virtual memory
1884:
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1716:Turing machine
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1568:External links
1566:
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1509:
1488:
1459:
1449:Tom's Hardware
1434:
1415:
1404:. 26 June 2017
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1335:
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1179:
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1123:
1092:
1081:on 14 May 2011
1062:
1032:
1003:
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933:
893:
871:
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827:
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783:
755:
743:
715:978-0128119051
714:
692:
656:
642:
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597:on 31 May 2014
582:
556:
519:
508:. pp. 2–3
489:
488:
486:
483:
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481:
476:
471:
464:
461:
433:Colin Percival
428:
425:
415:In 2019, with
365:
362:
323:Tom's Hardware
313:
310:
291:Windows XP SP1
229:Denelcor, Inc.
222:
219:
160:multithreading
147:
144:
119:processor core
100:Pentium 4
26:
9:
6:
4:
3:
2:
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4485:Global Arrays
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3344:Demultiplexer
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3265:Memory buffer
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3260:Register file
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3200:Combinational
3198:
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2301:
2300:Scoreboarding
2298:
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2282:False sharing
2280:
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2250:
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2086:
2083:
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2075:Stanford MIPS
2073:
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2068:
2066:
2063:
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2018:
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1969:
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1936:architectures
1931:
1925:
1922:
1920:
1917:
1915:
1912:
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1905:
1904:Heterogeneous
1902:
1898:
1895:
1893:
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1880:
1876:
1873:
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1855:Memory access
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1841:
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1788:Random-access
1786:
1784:
1781:
1779:
1776:
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1774:
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1768:Stack machine
1766:
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1710:
1707:
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1697:
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1690:
1687:
1685:
1684:with datapath
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1219:9781466648524
1215:
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1103:
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1080:
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809:
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796:www.intel.com
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494:
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480:
477:
475:
472:
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467:
466:
460:
458:
454:
450:
446:
445:timing attack
442:
438:
434:
431:In May 2005,
424:
422:
418:
413:
411:
407:
403:
398:
396:
392:
387:
384:
382:
378:
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361:
359:
356:generated by
355:
349:
346:
345:replay system
339:
336:
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327:
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74:
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66:
62:
61:HT Technology
58:
54:
47:
43:
39:
34:
30:
19:
4170:Coordination
4100:Amdahl's law
4036:Simultaneous
3809:
3768:AMT versions
3680:Discontinued
3554:Chip carrier
3492:Clock gating
3411:Mixed-signal
3308:Write buffer
3285:Control unit
3097:Clock signal
2836:accelerators
2818:Cypress PSoC
2479:
2475:Simultaneous
2292:Out-of-order
1924:Neuromorphic
1805:Architecture
1763:Belt machine
1756:Zeno machine
1689:Hierarchical
1553:. Retrieved
1547:
1537:
1525:. Retrieved
1521:
1512:
1500:. Retrieved
1491:
1479:. Retrieved
1475:
1462:
1454:the original
1447:
1437:
1428:
1418:
1406:. Retrieved
1401:Ars Technica
1399:
1390:
1378:. Retrieved
1375:The Register
1374:
1364:
1352:. Retrieved
1349:The Register
1348:
1338:
1326:. Retrieved
1323:bit-tech.net
1322:
1313:
1304:
1295:
1283:. Retrieved
1279:the original
1274:
1264:
1238:. Retrieved
1228:
1209:
1204:
1192:. Retrieved
1182:
1173:
1166:. Retrieved
1152:
1140:. Retrieved
1135:
1126:
1114:. Retrieved
1110:the original
1095:
1083:. Retrieved
1079:the original
1074:
1065:
1053:. Retrieved
1049:the original
1044:
1035:
1023:. Retrieved
1019:
994:. Retrieved
980:
968:. Retrieved
958:
950:the original
945:
936:
925:the original
912:
908:
896:
884:. Retrieved
874:
862:. Retrieved
852:
840:. Retrieved
830:
818:. Retrieved
808:
800:the original
795:
786:
775:, retrieved
771:the original
765:
758:
746:
701:
695:
683:. Retrieved
676:the original
645:
633:
621:. Retrieved
611:
599:. Retrieved
595:the original
585:
575:30 September
573:. Retrieved
559:
549:30 September
547:. Retrieved
540:the original
535:
522:
512:30 September
510:. Retrieved
505:Ars Technica
503:
493:
430:
414:
399:
388:
385:
370:
367:
350:
341:
332:
328:
315:
295:
287:Windows 2000
277:(plus their
252:
241:
227:
224:
206:
199:
172:
168:
157:
141:
116:
68:
64:
60:
56:
52:
51:
29:
4606:Scalability
4367:distributed
4250:Concurrency
4217:Programming
4058:Cooperative
4047:Speculative
3983:Instruction
3840:Thunderbolt
3339:Multiplexer
3303:Data buffer
3014:Single-core
2986:bit slicing
2844:Coprocessor
2699:Coprocessor
2580:performance
2502:Cooperative
2492:Speculative
2452:Distributed
2411:Superscalar
2396:Instruction
2364:Parallelism
2337:Speculative
2169:System/3x0
2041:Instruction
1818:Von Neumann
1731:Post–Turing
1408:25 November
1240:29 February
1194:29 February
1142:26 February
1136:calomel.org
1116:26 February
996:12 November
882:. Intel.com
417:Coffee Lake
267:Pentium Pro
231:introduced
132:in parallel
128:superscalar
77:proprietary
46:clock cycle
4645:Categories
4611:Starvation
4350:asymmetric
4085:PRAM model
4053:Preemptive
3707:Intel Play
3646:Skulltrail
3616:Centrino 2
3598:technology
3459:management
3354:Multiplier
3215:Logic gate
3205:Sequential
3112:Functional
3092:Clock rate
3065:Data cache
3038:Components
3019:Multi-core
3007:Core count
2497:Preemptive
2401:Pipelining
2384:Bit-serial
2327:Wide-issue
2272:Structural
2194:Tilera ISA
2160:MicroBlaze
2130:ETRAX CRIS
2025:Comparison
1870:Load–store
1850:Endianness
1354:13 January
1328:2 December
1275:Top500.org
1162:kernel.org
623:24 October
485:References
395:Silvermont
302:Intel Atom
187:cache miss
136:concurrent
96:processors
4345:symmetric
4090:PEM model
3815:Omni-Path
3795:SpeedStep
3641:Ultrabook
3604:Platforms
3393:Circuitry
3313:Microcode
3237:Registers
3080:coherence
3055:CPU cache
2913:Word size
2578:Processor
2222:Execution
2125:DEC Alpha
2103:Power ISA
1919:Cognitive
1726:Universal
1527:24 August
1522:marc.info
1502:24 August
1429:AnandTech
921:1535-766X
732:cite book
724:983459758
570:AnandTech
536:cs.sfu.ca
410:Microcode
406:Kaby Lake
381:dual core
364:Drawbacks
235:with the
217:systems.
210:scheduler
117:For each
38:processes
4576:Deadlock
4564:Problems
4530:pthreads
4510:OpenHMPP
4435:Ateji PX
4396:computer
4267:Hardware
4134:Elements
4120:Slowdown
4031:Temporal
4013:Pipeline
3854:Upcoming
3611:Centrino
3331:Datapath
3024:Manycore
2996:variable
2834:Hardware
2470:Temporal
2150:OpenRISC
1845:Cellular
1835:Dataflow
1828:modified
1250:cite web
1085:24 April
1055:12 April
685:21 March
463:See also
427:Security
393:for its
318:die area
289:SP3 and
146:Overview
4535:RaftLib
4515:OpenACC
4490:GPUOpen
4480:C++ AMP
4455:Charm++
4197:Barrier
4141:Process
4125:Speedup
3910:General
3726:Current
3656:Galileo
3507:Related
3438:Quantum
3428:Digital
3423:Boolean
3321:Counter
3220:Quantum
2981:512-bit
2976:256-bit
2971:128-bit
2814:(MPSoC)
2799:on chip
2797:Systems
2615:(FLOPS)
2428:Process
2277:Control
2259:Hazards
2145:Itanium
2140:Unicore
2098:PowerPC
1823:Harvard
1783:Pointer
1778:Counter
1736:Quantum
1481:14 June
1285:5 April
1175:system.
1168:2 March
1025:2 March
970:5 April
886:5 April
864:5 April
820:5 April
619:. Intel
449:OpenBSD
402:Skylake
306:Itanium
279:Celeron
221:History
183:logical
104:Itanium
94:server
4628:
4505:OpenCL
4500:OpenMP
4445:Chapel
4362:shared
4357:Memory
4292:(SIMT)
4235:Models
4146:Thread
4078:Theory
4049:(SpMT)
4003:Memory
3988:Thread
3971:Levels
3661:Edison
3631:Tablet
3443:Switch
3433:Analog
3171:(IMC)
3142:(MMU)
2991:others
2966:64-bit
2961:48-bit
2956:32-bit
2951:24-bit
2946:16-bit
2941:15-bit
2936:12-bit
2773:Mobile
2689:Stream
2684:Barrel
2679:Vector
2668:(GPU)
2627:(SUPS)
2595:(IPC)
2447:Memory
2440:Vector
2423:Thread
2406:Scalar
2208:Others
2155:RISC-V
2120:SuperH
2089:Power
2085:MIPS-X
2060:PDP-11
1909:Fabric
1661:Models
1555:14 May
1380:4 July
1216:
919:
842:2 July
777:24 May
722:
712:
601:4 June
281:&
110:, and
4475:Dryad
4440:Boost
4161:Array
4151:Fiber
4065:(CMT)
4038:(SMT)
3952:GPGPU
3717:MMC-2
3712:MMC-1
3666:Curie
3596:Intel
3499:(PPW)
3457:Power
3349:Adder
3225:Array
3192:Logic
3153:(TLB)
3136:(FPU)
3130:(AGU)
3124:(ALU)
3114:units
3050:Cache
2931:8-bit
2926:4-bit
2921:1-bit
2885:(TPU)
2879:(DSP)
2873:(PPU)
2867:(VPU)
2856:(GPU)
2825:(NoC)
2808:(SoC)
2743:(PoP)
2737:(SiP)
2731:(MCM)
2672:GPGPU
2662:(CPU)
2652:Types
2633:(PPW)
2621:(TPS)
2609:(IPS)
2601:(CPI)
2372:Level
2183:S/390
2178:S/370
2173:S/360
2115:SPARC
2093:POWER
1976:TRIPS
1944:Types
1549:WIRED
1472:(PDF)
1106:Intel
990:(PDF)
928:(PDF)
905:(PDF)
679:(PDF)
672:(PDF)
543:(PDF)
532:(PDF)
193:, or
73:Intel
71:) is
4540:ROCm
4470:CUDA
4460:Cilk
4427:APIs
4387:COMA
4382:NUMA
4313:MIMD
4308:MISD
4285:SIMD
4280:SISD
4008:Loop
3998:Data
3993:Task
3748:vPro
3738:CNVi
3636:CULV
3621:Viiv
3477:ACPI
3210:Glue
3102:FIFO
3045:Core
2783:ASIP
2724:CPLD
2719:FPOA
2714:FPGA
2709:ASIC
2562:SPMD
2557:MIMD
2552:MISD
2545:SWAR
2525:SIMD
2520:SISD
2435:Data
2418:Task
2389:Word
2135:M32R
2080:MIPS
2043:sets
2010:ZISC
2005:NISC
2000:OISC
1995:MISC
1988:EPIC
1983:VLIW
1971:EDGE
1961:RISC
1956:CISC
1865:HUMA
1860:NUMA
1557:2019
1529:2018
1504:2018
1483:2016
1410:2017
1382:2017
1356:2014
1330:2023
1287:2011
1256:link
1242:2012
1214:ISBN
1196:2012
1170:2015
1144:2015
1118:2015
1087:2011
1057:2011
1027:2015
998:2012
972:2011
917:ISSN
888:2011
866:2011
844:2017
822:2011
779:2016
738:link
720:OCLC
710:ISBN
687:2014
625:2021
603:2014
577:2015
551:2015
514:2015
404:and
283:Xeon
273:and
255:Xeon
248:CMOS
215:NUMA
108:Atom
92:Xeon
4555:ZPL
4550:TBB
4545:UPC
4525:PVM
4495:MPI
4450:HPX
4377:UMA
3978:Bit
3671:Evo
3651:NUC
3626:MID
3472:APM
3467:PMU
3359:CPU
3316:ROM
3087:Bus
2704:PAL
2379:Bit
2165:LMC
2070:ARM
2065:x86
2055:VAX
373:ARM
335:MPI
197:.)
88:x86
75:'s
67:or
65:HTT
59:or
4647::
3406:3D
1546:.
1520:.
1474:.
1446:.
1427:.
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1347:.
1321:.
1303:.
1273:.
1252:}}
1248:{{
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